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OpenXG
OpenXG UE
Commits
78d4d9f8
Commit
78d4d9f8
authored
Feb 19, 2021
by
Florian Kaltenberger
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when PRACH config 4 is used (Benetel RRU) we only schedule UL slots 8 and 9
parent
d6b6afff
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-1
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+7
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
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78d4d9f8
...
...
@@ -370,7 +370,13 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
#define BIT(x) (1 << (x))
const
uint64_t
dlsch_in_slot_bitmap
=
BIT
(
1
)
|
BIT
(
2
)
|
BIT
(
3
)
|
BIT
(
4
)
|
BIT
(
5
)
|
BIT
(
6
)
|
BIT
(
11
)
|
BIT
(
12
)
|
BIT
(
13
)
|
BIT
(
14
)
|
BIT
(
15
)
|
BIT
(
16
);
const
uint64_t
ulsch_in_slot_bitmap
=
BIT
(
8
)
|
BIT
(
18
);
uint8_t
prach_config_index
=
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
rach_ConfigCommon
->
choice
.
setup
->
rach_ConfigGeneric
.
prach_ConfigurationIndex
;
uint64_t
ulsch_in_slot_bitmap
;
if
(
prach_config_index
==
4
)
//this is the PRACH config used in the Benetel RRU. TODO: make this generic for any PRACH config.
ulsch_in_slot_bitmap
=
BIT
(
8
)
|
BIT
(
9
);
else
ulsch_in_slot_bitmap
=
BIT
(
8
)
|
BIT
(
18
);
memset
(
RC
.
nrmac
[
module_idP
]
->
cce_list
[
bwp_id
][
0
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
// coreset0
memset
(
RC
.
nrmac
[
module_idP
]
->
cce_list
[
bwp_id
][
1
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
// coresetid 1
...
...
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