Commit 37b63f32 authored by Roberto Louro Magueta's avatar Roberto Louro Magueta

Implementation of compute_srs_resource_indicator function to be improved in future commits

parent e1198b3d
......@@ -2615,6 +2615,64 @@ uint8_t get_pusch_nb_antenna_ports(NR_PUSCH_Config_t *pusch_Config,
return n_antenna_port;
}
uint8_t compute_srs_resource_indicator(NR_UplinkConfig_t *uplinkConfig,
NR_PUSCH_Config_t *pusch_Config,
NR_SRS_Config_t *srs_config,
uint16_t *val) {
uint8_t nbits = 0;
if (srs_config && pusch_Config && pusch_Config->txConfig != NULL) {
int count=0;
if (*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook) {
for (int i=0; i<srs_config->srs_ResourceSetToAddModList->list.count; i++) {
if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_codebook)
count++;
}
if (count>1) {
nbits = 1;
}
} else {
int lmin = 0;
int Lmax = 0;
int lsum = 0;
if (uplinkConfig && uplinkConfig->pusch_ServingCellConfig != NULL) {
if (uplinkConfig->pusch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers != NULL) {
Lmax = *uplinkConfig->pusch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers;
} else {
AssertFatal(1==0,"MIMO on PUSCH not supported, maxMIMO_Layers needs to be set to 1\n");
}
} else {
AssertFatal(1==0,"MIMO on PUSCH not supported, maxMIMO_Layers needs to be set to 1\n");
}
for (int i=0; i<srs_config->srs_ResourceSetToAddModList->list.count; i++) {
if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_nonCodebook) {
count++;
}
if (count < Lmax) {
lmin = count;
} else {
lmin = Lmax;
}
for (int k=1;k<=lmin;k++) {
lsum += binomial(count,k);
}
}
nbits = (int)ceil(log2(lsum));
}
} else {
nbits = 0;
}
// TODO: Implement this.
if (val) {
*val = 0;
}
return nbits;
}
uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
const NR_BWP_UplinkCommon_t *initialUplinkBWP,
const NR_CellGroupConfig_t *cg,
......@@ -2631,6 +2689,11 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
long rbg_size_config;
int num_entries = 0;
NR_UplinkConfig_t *uplinkConfig = NULL;
if (cg && cg->spCellConfig && cg->spCellConfig->spCellConfigDedicated) {
uplinkConfig = cg->spCellConfig->spCellConfigDedicated->uplinkConfig;
}
const NR_BWP_DownlinkDedicated_t *bwpd = NULL;
const NR_BWP_UplinkDedicated_t *ubwpd = NULL;
const NR_BWP_DownlinkCommon_t *bwpc = NULL;
......@@ -2642,23 +2705,21 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
NR_SRS_Config_t *srs_config = NULL;
if(bwp_id > 0) {
AssertFatal(cg!=NULL,"Cellgroup is null and bwp_id!=0");
bwpd=cg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]->bwp_Dedicated;
bwpc=cg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]->bwp_Common;
ubwpd=cg->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]->bwp_Dedicated;
ubwpc=cg->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]->bwp_Common;
bwpd = cg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]->bwp_Dedicated;
bwpc = cg->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1]->bwp_Common;
ubwpd = uplinkConfig ? uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]->bwp_Dedicated : NULL;
ubwpc = uplinkConfig ? uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1]->bwp_Common : NULL;
pdsch_Config = (bwpd->pdsch_Config) ? bwpd->pdsch_Config->choice.setup : NULL;
pdcch_Config = (bwpd->pdcch_Config) ? bwpd->pdcch_Config->choice.setup : NULL;
pucch_Config = (ubwpd->pucch_Config) ? ubwpd->pucch_Config->choice.setup : NULL;
pusch_Config = (ubwpd->pusch_Config) ? ubwpd->pusch_Config->choice.setup : NULL;
srs_config = (ubwpd->srs_Config) ? ubwpd->srs_Config->choice.setup : NULL;
}
else if (cg){
} else if (cg) {
bwpc = initialDownlinkBWP;
ubwpc = initialUplinkBWP;
bwpd = cg->spCellConfig && cg->spCellConfig->spCellConfigDedicated ?
cg->spCellConfig->spCellConfigDedicated->initialDownlinkBWP : NULL;
ubwpd = cg->spCellConfig && cg->spCellConfig->spCellConfigDedicated && cg->spCellConfig->spCellConfigDedicated->uplinkConfig ?
cg->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP : NULL;
ubwpd = uplinkConfig ? uplinkConfig->initialUplinkBWP : NULL;
pdsch_Config = (bwpd && bwpd->pdsch_Config) ? bwpd->pdsch_Config->choice.setup : NULL;
pdcch_Config = (bwpd && bwpd->pdcch_Config) ? bwpd->pdcch_Config->choice.setup : NULL;
pucch_Config = (ubwpd && ubwpd->pucch_Config) ? ubwpd->pucch_Config->choice.setup : NULL;
......@@ -2756,55 +2817,15 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
size += dci_pdu->dai[1].nbits;
}
// SRS resource indicator
if (srs_config &&
pusch_Config &&
pusch_Config->txConfig != NULL){
int count=0;
if (*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook){
for (int i=0; i<srs_config->srs_ResourceSetToAddModList->list.count; i++) {
if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_codebook)
count++;
}
if (count>1) {
dci_pdu->srs_resource_indicator.nbits = 1;
size += dci_pdu->srs_resource_indicator.nbits;
}
}
else {
int lmin,Lmax = 0;
int lsum = 0;
if ( cg->spCellConfig->spCellConfigDedicated->uplinkConfig &&
cg->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig != NULL) {
if ( cg->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers != NULL)
Lmax = *cg->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers;
else
AssertFatal(1==0,"MIMO on PUSCH not supported, maxMIMO_Layers needs to be set to 1\n");
}
else
AssertFatal(1==0,"MIMO on PUSCH not supported, maxMIMO_Layers needs to be set to 1\n");
for (int i=0; i<srs_config->srs_ResourceSetToAddModList->list.count; i++) {
if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_nonCodebook)
count++;
if (count < Lmax) lmin = count;
else lmin = Lmax;
for (int k=1;k<=lmin;k++) {
lsum += binomial(count,k);
}
}
dci_pdu->srs_resource_indicator.nbits = (int)ceil(log2(lsum));
size += dci_pdu->srs_resource_indicator.nbits;
}
} else dci_pdu->srs_resource_indicator.nbits = 0;
LOG_D(NR_MAC,"dci_pdu->srs_resource_indicator.nbits %d\n",dci_pdu->srs_resource_indicator.nbits);
dci_pdu->srs_resource_indicator.nbits = compute_srs_resource_indicator(uplinkConfig, pusch_Config, srs_config, NULL);
size += dci_pdu->srs_resource_indicator.nbits;
LOG_D(NR_MAC,"dci_pdu->srs_resource_indicator.nbits %d\n", dci_pdu->srs_resource_indicator.nbits);
// Precoding info and number of layers
long transformPrecoder = get_transformPrecoding(initialUplinkBWP, pusch_Config, ubwpd, (uint8_t*)&format, rnti_type, 0);
uint8_t pusch_antenna_ports = get_pusch_nb_antenna_ports(pusch_Config, srs_config, dci_pdu->srs_resource_indicator);
dci_pdu->precoding_information.nbits=0;
if (pusch_Config &&
pusch_Config->txConfig != NULL){
if (*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook){
if (pusch_Config && pusch_Config->txConfig != NULL) {
if (*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook) {
if (pusch_antenna_ports > 1) {
if (pusch_antenna_ports == 4) {
if ((transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) && (*pusch_Config->maxRank>1))
......
......@@ -47,6 +47,11 @@ int is_nr_DL_slot(NR_TDD_UL_DL_ConfigCommon_t *tdd_UL_DL_ConfigurationCommon,slo
int is_nr_UL_slot(NR_TDD_UL_DL_ConfigCommon_t *tdd_UL_DL_ConfigurationCommon, slot_t slotP, frame_type_t frame_type);
uint8_t compute_srs_resource_indicator(NR_UplinkConfig_t *uplinkConfig,
NR_PUSCH_Config_t *pusch_Config,
NR_SRS_Config_t *srs_config,
uint16_t *val);
uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDLBWP,
const NR_BWP_UplinkCommon_t *initialULBWP,
const NR_CellGroupConfig_t *cg,
......
......@@ -888,6 +888,7 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
ubwp,
ubwpd,
scc,
NULL,
pusch_pdu,
&uldci_payload,
NR_UL_DCI_FORMAT_0_0,
......
......@@ -992,6 +992,7 @@ void config_uldci(const NR_SIB1_t *sib1,
const NR_BWP_Uplink_t *ubwp,
const NR_BWP_UplinkDedicated_t *ubwpd,
const NR_ServingCellConfigCommon_t *scc,
const NR_CellGroupConfig_t *cg,
const nfapi_nr_pusch_pdu_t *pusch_pdu,
dci_pdu_rel15_t *dci_pdu_rel15,
int dci_format,
......@@ -1035,7 +1036,14 @@ void config_uldci(const NR_SIB1_t *sib1,
ubwpd2->pusch_Config->choice.setup->txConfig != NULL) {
AssertFatal(*ubwpd2->pusch_Config->choice.setup->txConfig == NR_PUSCH_Config__txConfig_codebook,
"Non Codebook configuration non supported\n");
dci_pdu_rel15->srs_resource_indicator.val = 0; // taking resource 0 for SRS
NR_UplinkConfig_t *uplinkConfig = NULL;
if (cg && cg->spCellConfig && cg->spCellConfig->spCellConfigDedicated) {
uplinkConfig = cg->spCellConfig->spCellConfigDedicated->uplinkConfig;
}
compute_srs_resource_indicator(uplinkConfig,
ubwpd->pusch_Config ? ubwpd->pusch_Config->choice.setup : NULL,
ubwpd2 && ubwpd2->srs_Config ? ubwpd->srs_Config->choice.setup : NULL,
&dci_pdu_rel15->srs_resource_indicator.val);
}
dci_pdu_rel15->precoding_information.val= 0;
if (pusch_pdu->nrOfLayers == 2)
......@@ -1534,8 +1542,10 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
int dci_size = nr_dci_size(scc->downlinkConfigCommon->initialDownlinkBWP,scc->uplinkConfigCommon->initialUplinkBWP, CellGroup, dci_pdu_rel15, dci_format, rnti_type, N_RB, bwp_id, coreset_id, cset0_bwp_size);
pdcch_dci_pdu->PayloadSizeBits = dci_size;
AssertFatal(dci_size <= 64, "DCI sizes above 64 bits not yet supported");
if (dci_format == NR_DL_DCI_FORMAT_1_1 || dci_format == NR_UL_DCI_FORMAT_0_1)
if (dci_format == NR_DL_DCI_FORMAT_1_1 || dci_format == NR_UL_DCI_FORMAT_0_1) {
prepare_dci(CellGroup, dci_pdu_rel15, dci_format, bwp_id);
}
/// Payload generation
switch (dci_format) {
......
......@@ -1989,6 +1989,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
sched_ctrl->active_ubwp,
ubwpd,
scc,
cg,
pusch_pdu,
&uldci_payload,
ps->dci_format,
......@@ -1996,6 +1997,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
UE_info->UE_sched_ctrl[UE_id].tpc0,
n_ubwp,
bwp_id);
fill_dci_pdu_rel15(scc,
cg,
dci_pdu,
......
......@@ -195,6 +195,7 @@ void config_uldci(const NR_SIB1_t *sib1,
const NR_BWP_Uplink_t *ubwp,
const NR_BWP_UplinkDedicated_t *ubwpd,
const NR_ServingCellConfigCommon_t *scc,
const NR_CellGroupConfig_t *cg,
const nfapi_nr_pusch_pdu_t *pusch_pdu,
dci_pdu_rel15_t *dci_pdu_rel15,
int dci_format,
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment