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OpenXG-RAN
Commit 4a6f8a7d authored by Abhijith's avatar Abhijith
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Review comments incorporated

parent 698917bf
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.vscode/launch.json 0 → 100644
View file @ 4a6f8a7d
{
// Use IntelliSense to learn about possible attributes.
// Hover to view descriptions of existing attributes.
// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
"version": "0.2.0",
"configurations": [
{
"name": "(gdb) Launch",
"type": "cppdbg",
"request": "launch",
"program": "enter program name, for example ${workspaceFolder}/a.exe",
"args": [],
"stopAtEntry": false,
"cwd": "${workspaceFolder}",
"environment": [],
"externalConsole": false,
"MIMode": "gdb",
"miDebuggerPath": "/path/to/gdb",
"setupCommands": [
{
"description": "Enable pretty-printing for gdb",
"text": "-enable-pretty-printing",
"ignoreFailures": true
}
]
}
]
}
openair2/GNB_APP/gnb_config.c
View file @ 4a6f8a7d
......@@ -424,7 +424,7 @@ for (int j = 0 ;j < 4 ; j++)
/* This function checks dedicated serving cell configuration and performs fixes as needed */
void fix_scd(NR_ServingCellConfig_t *scd) {
// Check for DL PTRS parameters validity
for (int bwp_i = 0 ; bwp_i< MAX_NUM_BWP; bwp_i++)
for (int bwp_i = 0 ; bwp_i< 4; bwp_i++)
{
if (scd->downlinkBWP_ToAddModList->list.array[bwp_i]->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS) {
// If any of the frequencyDensity values are not set or are out of bounds, PTRS is assumed to be not present
......
openair2/LAYER2/NR_MAC_UE/config_ue.c
View file @ 4a6f8a7d
......@@ -418,7 +418,7 @@ void config_control_ue(NR_UE_MAC_INST_t *mac){
// check pdcch_Config, pdcch_ConfigCommon and DL BWP
// Check dedicated UL BWP and pass to MAC
for (int num_BWP = 0; num_BWP <MAX_NUM_BWP ;num_BWP++)
for (int num_BWP = 0; num_BWP <4 ;num_BWP++)
{
mac->DLbwp[num_BWP] = scd->downlinkBWP_ToAddModList->list.array[num_BWP];
mac->ULbwp[num_BWP] = uplinkBWP_ToAddModList->list.array[num_BWP];
......
openair2/LAYER2/NR_MAC_UE/mac_defs.h
View file @ 4a6f8a7d
......@@ -74,7 +74,7 @@
// ==========
#define NB_NR_UE_MAC_INST 1
#define MAX_NUM_BWP 4
#define MAX_NUM_BWP 5
#define NUM_SLOT_FRAME 10
/*!\brief value for indicating BSR Timer is not running */
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @ 4a6f8a7d
......@@ -325,54 +325,12 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
protocol_ctxt_t ctxt;
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame, slot,module_idP);
//int nb_periods_per_frame;
gNB_MAC_INST *gNB = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = gNB->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
const int bwp_id = *gNB->secondaryCellGroupCommon->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id;
// NR_TDD_UL_DL_Pattern_t *tdd_pattern = &scc->tdd_UL_DL_ConfigurationCommon->pattern1;
// switch(scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity) {
// case 0:
// nb_periods_per_frame = 20; // 10ms/0p5ms
// break;
// case 1:
// nb_periods_per_frame = 16; // 10ms/0p625ms
// break;
// case 2:
// nb_periods_per_frame = 10; // 10ms/1ms
// break;
// case 3:
// nb_periods_per_frame = 8; // 10ms/1p25ms
// break;
// case 4:
// nb_periods_per_frame = 5; // 10ms/2ms
// break;
// case 5:
// nb_periods_per_frame = 4; // 10ms/2p5ms
// break;
// case 6:
// nb_periods_per_frame = 2; // 10ms/5ms
// break;
// case 7:
// nb_periods_per_frame = 1; // 10ms/10ms
// break;
// default:
// AssertFatal(1==0,"Undefined tdd period %ld\n", scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity);
// }
if (slot==0 && (*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]>=257)) {
const NR_TDD_UL_DL_Pattern_t *tdd = &scc->tdd_UL_DL_ConfigurationCommon->pattern1;
const int n = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
......@@ -397,8 +355,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
nr_rrc_trigger(&ctxt, 0 /*CC_id*/, frame, slot >> *scc->ssbSubcarrierSpacing);
}
memset(RC.nrmac[module_idP]->cce_list[bwp_id-1][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
memset(RC.nrmac[module_idP]->cce_list[bwp_id-1][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
NR_UE_info_t *UE_info = &RC.nrmac[module_idP]->UE_info;
for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id])
for (int i=0; i<MAX_NUM_CORESET; i++)
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @ 4a6f8a7d
......@@ -962,7 +962,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
// look up the PDCCH PDU for this CC, BWP, and CORESET. If it does not exist, create it. This is especially
// important if we have multiple RAs, and the DLSCH has to reuse them, so we need to mark them
const int coresetid = coreset->controlResourceSetId;
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id-1][coresetid];
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id][coresetid];
if (!pdcch_pdu_rel15) {
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset(dl_tti_pdcch_pdu, 0, sizeof(nfapi_nr_dl_tti_request_pdu_t));
......@@ -971,7 +971,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
dl_req->nPDUs += 1;
pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
nr_configure_pdcch(pdcch_pdu_rel15, ss, coreset, scc, bwp);
nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id-1][coresetid] = pdcch_pdu_rel15;
nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id][coresetid] = pdcch_pdu_rel15;
}
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
......@@ -1284,7 +1284,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
// look up the PDCCH PDU for this CC, BWP, and CORESET. If it does not exist, create it. This is especially
// important if we have multiple RAs, and the DLSCH has to reuse them, so we need to mark them
const int coresetid = coreset->controlResourceSetId;
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id-1][coresetid];
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id][coresetid];
if (!pdcch_pdu_rel15) {
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset(dl_tti_pdcch_pdu, 0, sizeof(nfapi_nr_dl_tti_request_pdu_t));
......@@ -1293,7 +1293,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
dl_req->nPDUs += 1;
pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
nr_configure_pdcch(pdcch_pdu_rel15, ss, coreset, scc, bwp);
nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id-1][coresetid] = pdcch_pdu_rel15;
nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id][coresetid] = pdcch_pdu_rel15;
}
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @ 4a6f8a7d
......@@ -60,7 +60,7 @@ void calculate_preferred_dl_tda(module_id_t module_id, const NR_BWP_Downlink_t *
{
gNB_MAC_INST *nrmac = RC.nrmac[module_id];
const int bwp_id = bwp->bwp_Id;
if (nrmac->preferred_dl_tda[bwp_id-1])
if (nrmac->preferred_dl_tda[bwp_id])
return;
/* there is a mixed slot only when in TDD */
......@@ -118,17 +118,17 @@ void calculate_preferred_dl_tda(module_id_t module_id, const NR_BWP_Downlink_t *
const uint8_t slots_per_frame[5] = {10, 20, 40, 80, 160};
const int n = slots_per_frame[*scc->ssbSubcarrierSpacing];
nrmac->preferred_dl_tda[bwp_id-1] = malloc(n * sizeof(*nrmac->preferred_dl_tda[bwp_id-1]));
nrmac->preferred_dl_tda[bwp_id] = malloc(n * sizeof(*nrmac->preferred_dl_tda[bwp_id]));
const int nr_mix_slots = tdd ? tdd->nrofDownlinkSymbols != 0 || tdd->nrofUplinkSymbols != 0 : 0;
const int nr_slots_period = tdd ? tdd->nrofDownlinkSlots + tdd->nrofUplinkSlots + nr_mix_slots : n;
for (int i = 0; i < n; ++i) {
nrmac->preferred_dl_tda[bwp_id-1][i] = -1;
nrmac->preferred_dl_tda[bwp_id][i] = -1;
if (!tdd || i % nr_slots_period < tdd->nrofDownlinkSlots)
nrmac->preferred_dl_tda[bwp_id-1][i] = 0;
nrmac->preferred_dl_tda[bwp_id][i] = 0;
else if (tdd && nr_mix_slots && i % nr_slots_period == tdd->nrofDownlinkSlots)
nrmac->preferred_dl_tda[bwp_id-1][i] = tdaMi;
LOG_I(MAC, "slot %d preferred_dl_tda %d\n", i, nrmac->preferred_dl_tda[bwp_id-1][i]);
nrmac->preferred_dl_tda[bwp_id][i] = tdaMi;
LOG_I(MAC, "slot %d preferred_dl_tda %d\n", i, nrmac->preferred_dl_tda[bwp_id][i]);
}
}
......@@ -429,7 +429,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
const uint8_t num_dmrs_cdm_grps_no_data = 1;
int rbSize = 0;
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id-1][slot];
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot];
if (tda == retInfo->time_domain_allocation) {
/* Check that there are enough resources for retransmission */
while (rbSize < retInfo->rbSize) {
......@@ -503,7 +503,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
slot);
int cid = sched_ctrl->coreset->controlResourceSetId;
UE_info->num_pdcch_cand[UE_id][cid]--;
int *cce_list = RC.nrmac[module_id]->cce_list[sched_ctrl->active_bwp->bwp_Id-1][cid];
int *cce_list = RC.nrmac[module_id]->cce_list[sched_ctrl->active_bwp->bwp_Id][cid];
for (int i = 0; i < sched_ctrl->aggregation_level; i++)
cce_list[sched_ctrl->cce_index + i] = 0;
return false;
......@@ -628,7 +628,7 @@ void pf_dl(module_id_t module_id,
slot);
int cid = sched_ctrl->coreset->controlResourceSetId;
UE_info->num_pdcch_cand[UE_id][cid]--;
int *cce_list = RC.nrmac[module_id]->cce_list[sched_ctrl->active_bwp->bwp_Id-1][cid];
int *cce_list = RC.nrmac[module_id]->cce_list[sched_ctrl->active_bwp->bwp_Id][cid];
for (int i = 0; i < sched_ctrl->aggregation_level; i++)
cce_list[sched_ctrl->cce_index + i] = 0;
return;
......@@ -642,7 +642,7 @@ void pf_dl(module_id_t module_id,
/* MCS has been set above */
const uint8_t num_dmrs_cdm_grps_no_data = 1;
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id-1][slot];
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot];
NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
if (ps->time_domain_allocation != tda || ps->numDmrsCdmGrpsNoData != num_dmrs_cdm_grps_no_data)
......@@ -688,7 +688,7 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
int UE_id = UE_info->list.head;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id-1][slot];
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot];
if (tda < 0)
return;
......@@ -844,7 +844,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
* exist, create it */
const int bwpid = sched_ctrl->active_bwp->bwp_Id;
const int coresetid = sched_ctrl->coreset->controlResourceSetId;
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = gNB_mac->pdcch_pdu_idx[CC_id][bwpid-1][coresetid];
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = gNB_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid];
if (!pdcch_pdu) {
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset(dl_tti_pdcch_pdu, 0, sizeof(nfapi_nr_dl_tti_request_pdu_t));
......@@ -853,7 +853,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
dl_req->nPDUs += 1;
pdcch_pdu = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
nr_configure_pdcch(pdcch_pdu, sched_ctrl->search_space, sched_ctrl->coreset, scc, bwp);
gNB_mac->pdcch_pdu_idx[CC_id][bwpid-1][coresetid] = pdcch_pdu;
gNB_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu;
}
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @ 4a6f8a7d
......@@ -282,6 +282,8 @@ void nr_preprocessor_phytest(module_id_t module_id,
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
/* find largest unallocated chunk */
const int bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
target_dl_bw = (bwpSize < target_dl_bw) ?bwpSize : target_dl_bw;
int rbStart = 0;
int rbSize = 0;
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
......@@ -295,7 +297,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize] && rbSize < target_dl_bw)
rbSize++;
/* found target_dl_bw? */
if (rbSize == target_dl_bw)
if (rbStart+ rbSize == target_dl_bw)
break;
/* at end and below target_dl_bw? */
if (rbStart + rbSize >= bwpSize)
......@@ -349,7 +351,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
frame,
slot);
UE_info->num_pdcch_cand[UE_id][cid]--;
int *cce_list = RC.nrmac[module_id]->cce_list[sched_ctrl->active_bwp->bwp_Id-1][cid];
int *cce_list = RC.nrmac[module_id]->cce_list[sched_ctrl->active_bwp->bwp_Id][cid];
for (int i = 0; i < sched_ctrl->aggregation_level; i++)
cce_list[sched_ctrl->cce_index + i] = 0;
return;
......@@ -364,7 +366,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
sched_pdsch->pucch_allocation = alloc;
sched_pdsch->rbStart = rbStart;
sched_pdsch->rbSize = rbSize;
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id-1][slot];
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot];
const uint8_t num_dmrs_cdm_grps_no_data = 1;
if (ps->time_domain_allocation != tda || ps->numDmrsCdmGrpsNoData != num_dmrs_cdm_grps_no_data)
nr_set_pdsch_semi_static(
......@@ -414,7 +416,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int tda = RC.nrmac[module_id]->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id-1][slot];
const int tda = RC.nrmac[module_id]->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot];
if (tda < 0)
return false;
const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList =
......@@ -445,7 +447,16 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
nr_set_pusch_semi_static(scc, sched_ctrl->active_ubwp, dci_format, tda, num_dmrs_cdm_grps_no_data, ps);
uint16_t rbStart = 0;
uint16_t rbSize = target_ul_bw;
uint16_t rbSize;
const int bw = NRRIV2BW(sched_ctrl->active_ubwp ?
sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth :
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
if (target_ul_bw>bw)
rbSize = bw;
else
rbSize = target_ul_bw;
uint16_t *vrb_map_UL =
&RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[sched_slot * MAX_BWP_SIZE];
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ 4a6f8a7d
......@@ -177,9 +177,9 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
int *cce_list;
if( bwp==NULL || bwp->bwp_Id == 0 ) {
cce_list = nr_mac->cce_list[0][0];
cce_list = nr_mac->cce_list[1][0];
} else {
cce_list = nr_mac->cce_list[bwp->bwp_Id-1][coreset_id];
cce_list = nr_mac->cce_list[bwp->bwp_Id][coreset_id];
}
int n_rb=0;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @ 4a6f8a7d
......@@ -65,7 +65,7 @@ void calculate_preferred_ul_tda(module_id_t module_id, const NR_BWP_Uplink_t *ub
{
gNB_MAC_INST *nrmac = RC.nrmac[module_id];
const int bwp_id = ubwp->bwp_Id;
if (nrmac->preferred_ul_tda[bwp_id-1])
if (nrmac->preferred_ul_tda[bwp_id])
return;
/* there is a mixed slot only when in TDD */
......@@ -151,18 +151,18 @@ void calculate_preferred_ul_tda(module_id_t module_id, const NR_BWP_Uplink_t *ub
const uint8_t slots_per_frame[5] = {10, 20, 40, 80, 160};
const int n = slots_per_frame[*scc->ssbSubcarrierSpacing];
nrmac->preferred_ul_tda[bwp_id-1] = malloc(n * sizeof(*nrmac->preferred_ul_tda[bwp_id-1]));
nrmac->preferred_ul_tda[bwp_id] = malloc(n * sizeof(*nrmac->preferred_ul_tda[bwp_id]));
const int nr_mix_slots = tdd ? tdd->nrofDownlinkSymbols != 0 || tdd->nrofUplinkSymbols != 0 : 0;
const int nr_slots_period = tdd ? tdd->nrofDownlinkSlots + tdd->nrofUplinkSlots + nr_mix_slots : n;
for (int slot = 0; slot < n; ++slot) {
const int sched_slot = (slot + k2) % n;
nrmac->preferred_ul_tda[bwp_id-1][slot] = -1;
nrmac->preferred_ul_tda[bwp_id][slot] = -1;
if (!tdd || sched_slot % nr_slots_period >= tdd->nrofDownlinkSlots + nr_mix_slots)
nrmac->preferred_ul_tda[bwp_id-1][slot] = 0;
nrmac->preferred_ul_tda[bwp_id][slot] = 0;
else if (tdd && nr_mix_slots && sched_slot % nr_slots_period == tdd->nrofDownlinkSlots)
nrmac->preferred_ul_tda[bwp_id-1][slot] = tdaMi;
LOG_I(MAC, "DL slot %d UL slot %d preferred_ul_tda %d\n", slot, sched_slot, nrmac->preferred_ul_tda[bwp_id-1][slot]);
nrmac->preferred_ul_tda[bwp_id][slot] = tdaMi;
LOG_I(MAC, "DL slot %d UL slot %d preferred_ul_tda %d\n", slot, sched_slot, nrmac->preferred_ul_tda[bwp_id][slot]);
}
if (k2 < tdd->nrofUplinkSlots)
......@@ -799,7 +799,7 @@ bool allocate_ul_retransmission(module_id_t module_id,
NRRIV2BW(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
const uint8_t num_dmrs_cdm_grps_no_data = 1;
const int tda = RC.nrmac[module_id]->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id-1][slot];
const int tda = RC.nrmac[module_id]->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot];
if (tda == retInfo->time_domain_allocation) {
/* Check the resource is enough for retransmission */
while (rbStart < bwpSize && !rballoc_mask[rbStart])
......@@ -986,7 +986,7 @@ void pf_ul(module_id_t module_id,
* num_dmrs_cdm_grps_no_data has changed and only then recompute */
const long f = sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats;
const int dci_format = f ? NR_UL_DCI_FORMAT_0_1 : NR_UL_DCI_FORMAT_0_0;
const int tda = nrmac->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id-1][slot];
const int tda = nrmac->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot];
if (ps->time_domain_allocation != tda
|| ps->dci_format != dci_format
|| ps->num_dmrs_cdm_grps_no_data != num_dmrs_cdm_grps_no_data)
......@@ -1076,7 +1076,7 @@ void pf_ul(module_id_t module_id,
* num_dmrs_cdm_grps_no_data has changed and only then recompute */
const long f = sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats;
const int dci_format = f ? NR_UL_DCI_FORMAT_0_1 : NR_UL_DCI_FORMAT_0_0;
const int tda = nrmac->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id-1][slot];
const int tda = nrmac->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot];
if (ps->time_domain_allocation != tda
|| ps->dci_format != dci_format
|| ps->num_dmrs_cdm_grps_no_data != num_dmrs_cdm_grps_no_data)
......@@ -1126,7 +1126,7 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
* schedule now (slot + k2 is not UL slot) */
int UE_id = UE_info->list.head;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int tda = nr_mac->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id-1][slot];
const int tda = nr_mac->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot];
if (tda < 0)
return false;
int K2 = get_K2(sched_ctrl->active_ubwp, tda, mu);
......@@ -1461,7 +1461,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
* create it */
const int bwpid = sched_ctrl->active_bwp->bwp_Id;
const int coresetid = sched_ctrl->coreset->controlResourceSetId;
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = pdcch_pdu_bwp_coreset[bwpid-1][coresetid];
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = pdcch_pdu_bwp_coreset[bwpid][coresetid];
if (!pdcch_pdu) {
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &ul_dci_req->ul_dci_pdu_list[ul_dci_req->numPdus];
memset(ul_dci_request_pdu, 0, sizeof(nfapi_nr_ul_dci_request_pdus_t));
......@@ -1470,7 +1470,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
pdcch_pdu = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
ul_dci_req->numPdus += 1;
nr_configure_pdcch(pdcch_pdu, sched_ctrl->search_space, sched_ctrl->coreset, scc, sched_ctrl->active_bwp);
pdcch_pdu_bwp_coreset[bwpid-1][coresetid] = pdcch_pdu;
pdcch_pdu_bwp_coreset[bwpid][coresetid] = pdcch_pdu;
}
LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frame,slot);
......
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @ 4a6f8a7d
......@@ -72,7 +72,7 @@
/* Defs */
#define MAX_NUM_BWP 4
#define MAX_NUM_BWP 5
#define MAX_NUM_CORESET 2
#define MAX_NUM_CCE 90
#define MAX_HARQ_ROUNDS 4
......
targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.SCD.conf
View file @ 4a6f8a7d
......@@ -43,7 +43,7 @@ gNBs =
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
dl_carrierBandwidth = 106; //when changing BWPs, change this also to the same RBs
#initialDownlinkBWP
#genericParameters
# this is RBstart=33 (Start RB of SSB block),L=24 (275*(L-1))+RBstart
......@@ -72,7 +72,7 @@ gNBs =
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
ul_carrierBandwidth = 106; //when changing BWPs, change this also to the same RBs
pMax = 20;
#initialUplinkBWP
#genericParameters
......@@ -187,13 +187,13 @@ gNBs =
bwp1_subcarrierSpacing = 1 ;
# BWP 2 Configuration
bwp-Id_2 = 2;
bwp2_locationAndBandwidth = 28908; // RBstart=33,L=106
bwp2_locationAndBandwidth = 6325; // RBstart=0,L=24 ( 10 MHz BW)
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
bwp2_subcarrierSpacing = 1 ;
# BWP 3 Configuration
bwp-Id_3 = 3;
bwp3_locationAndBandwidth = 28908; // RBstart=33,L=106
bwp3_locationAndBandwidth = 13750; // RBstart=0,L=51 ( 20 MHz BW)
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
bwp3_subcarrierSpacing = 1 ;
......
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