Commit 64a65a87 authored by Robert Schmidt's avatar Robert Schmidt

Merge remote-tracking branch 'origin/NR_mixed_slot_fixes' into integration_2022_wk51

parents d66bc221 88192f13
...@@ -227,7 +227,8 @@ void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset) { ...@@ -227,7 +227,8 @@ void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset) {
*n_rb = 6*count; *n_rb = 6*count;
} }
int get_nb_periods_per_frame(uint8_t tdd_period) { int get_nb_periods_per_frame(uint8_t tdd_period)
{
int nb_periods_per_frame; int nb_periods_per_frame;
switch(tdd_period) { switch(tdd_period) {
...@@ -270,7 +271,13 @@ int get_nb_periods_per_frame(uint8_t tdd_period) { ...@@ -270,7 +271,13 @@ int get_nb_periods_per_frame(uint8_t tdd_period) {
} }
int get_dmrs_port(int nl, uint16_t dmrs_ports) { int get_first_ul_slot(int nrofDownlinkSlots, int nrofDownlinkSymbols, int nrofUplinkSymbols)
{
return (nrofDownlinkSlots + (nrofDownlinkSymbols != 0 && nrofUplinkSymbols == 0));
}
int get_dmrs_port(int nl, uint16_t dmrs_ports)
{
if (dmrs_ports == 0) return 0; // dci 1_0 if (dmrs_ports == 0) return 0; // dci 1_0
int p = -1; int p = -1;
......
...@@ -63,6 +63,7 @@ static inline int get_num_dmrs(uint16_t dmrs_mask ) { ...@@ -63,6 +63,7 @@ static inline int get_num_dmrs(uint16_t dmrs_mask ) {
return(num_dmrs); return(num_dmrs);
} }
int get_first_ul_slot(int nrofDownlinkSlots, int nrofDownlinkSymbols, int nrofUplinkSymbols);
int cce_to_reg_interleaving(const int R, int k, int n_shift, const int C, int L, const int N_regs); int cce_to_reg_interleaving(const int R, int k, int n_shift, const int C, int L, const int N_regs);
int get_SLIV(uint8_t S, uint8_t L); int get_SLIV(uint8_t S, uint8_t L);
void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset); void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset);
......
...@@ -513,7 +513,7 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP, ...@@ -513,7 +513,7 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
int nr_ulstart_slot = 0; int nr_ulstart_slot = 0;
if (tdd) { if (tdd) {
nr_dl_slots = tdd->nrofDownlinkSlots + (tdd->nrofDownlinkSymbols != 0); nr_dl_slots = tdd->nrofDownlinkSlots + (tdd->nrofDownlinkSymbols != 0);
nr_ulstart_slot = tdd->nrofDownlinkSlots; nr_ulstart_slot = get_first_ul_slot(tdd->nrofDownlinkSlots, tdd->nrofDownlinkSymbols, tdd->nrofUplinkSymbols);
nr_slots_period /= get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity); nr_slots_period /= get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity);
} }
else else
......
...@@ -893,7 +893,7 @@ void nr_get_Msg3alloc(module_id_t module_id, ...@@ -893,7 +893,7 @@ void nr_get_Msg3alloc(module_id_t module_id,
const int n_slots_frame = nr_slots_per_frame[mu]; const int n_slots_frame = nr_slots_per_frame[mu];
uint8_t k2 = 0; uint8_t k2 = 0;
if (frame_type == TDD) { if (frame_type == TDD) {
int msg3_slot = tdd->nrofDownlinkSlots; // first uplink slot int msg3_slot = get_first_ul_slot(tdd->nrofDownlinkSlots, tdd->nrofDownlinkSymbols, tdd->nrofUplinkSymbols);
if (tdd->nrofUplinkSymbols < 3) if (tdd->nrofUplinkSymbols < 3)
msg3_slot++; // we can't trasmit msg3 in mixed slot if there are less than 3 symbols msg3_slot++; // we can't trasmit msg3 in mixed slot if there are less than 3 symbols
else { else {
......
...@@ -64,7 +64,7 @@ const int get_dl_tda(const gNB_MAC_INST *nrmac, const NR_ServingCellConfigCommon ...@@ -64,7 +64,7 @@ const int get_dl_tda(const gNB_MAC_INST *nrmac, const NR_ServingCellConfigCommon
if (tdd && tdd->nrofDownlinkSymbols > 1) { // if there is a mixed slot where we can transmit DL if (tdd && tdd->nrofDownlinkSymbols > 1) { // if there is a mixed slot where we can transmit DL
const int nr_slots_period = tdd->nrofDownlinkSlots + tdd->nrofUplinkSlots + 1; const int nr_slots_period = tdd->nrofDownlinkSlots + tdd->nrofUplinkSlots + 1;
if ((slot%nr_slots_period) == tdd->nrofDownlinkSlots) if ((slot % nr_slots_period) == tdd->nrofDownlinkSlots)
return 2; return 2;
} }
return 0; // if FDD or not mixed slot in TDD, for now use default TDA return 0; // if FDD or not mixed slot in TDD, for now use default TDA
......
...@@ -135,7 +135,7 @@ int get_pucch_index(int frame, int slot, int n_slots_frame, const NR_TDD_UL_DL_P ...@@ -135,7 +135,7 @@ int get_pucch_index(int frame, int slot, int n_slots_frame, const NR_TDD_UL_DL_P
{ {
// PUCCH structures are indexed by slot in the PUCCH period determined by sched_pucch_size number of UL slots // PUCCH structures are indexed by slot in the PUCCH period determined by sched_pucch_size number of UL slots
// this functions return the index to the structure for slot passed to the function // this functions return the index to the structure for slot passed to the function
const int first_ul_slot_period = tdd ? tdd->nrofDownlinkSlots : 0; const int first_ul_slot_period = tdd ? get_first_ul_slot(tdd->nrofDownlinkSlots, tdd->nrofDownlinkSymbols, tdd->nrofUplinkSymbols) : 0;
const int n_ul_slots_period = tdd ? tdd->nrofUplinkSlots + (tdd->nrofUplinkSymbols > 0 ? 1 : 0) : n_slots_frame; const int n_ul_slots_period = tdd ? tdd->nrofUplinkSlots + (tdd->nrofUplinkSymbols > 0 ? 1 : 0) : n_slots_frame;
const int nr_slots_period = tdd ? n_slots_frame / get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity) : n_slots_frame; const int nr_slots_period = tdd ? n_slots_frame / get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity) : n_slots_frame;
const int n_ul_slots_frame = n_slots_frame / nr_slots_period * n_ul_slots_period; const int n_ul_slots_frame = n_slots_frame / nr_slots_period * n_ul_slots_period;
...@@ -1099,7 +1099,7 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac, ...@@ -1099,7 +1099,7 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac,
const NR_TDD_UL_DL_Pattern_t *tdd = scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL; const NR_TDD_UL_DL_Pattern_t *tdd = scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
AssertFatal(tdd || mac->common_channels[CC_id].frame_type == FDD, "Dynamic TDD not handled yet\n"); AssertFatal(tdd || mac->common_channels[CC_id].frame_type == FDD, "Dynamic TDD not handled yet\n");
const int nr_slots_period = tdd ? n_slots_frame / get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity) : n_slots_frame; const int nr_slots_period = tdd ? n_slots_frame / get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity) : n_slots_frame;
const int first_ul_slot_period = tdd ? tdd->nrofDownlinkSlots : 0; const int first_ul_slot_period = tdd ? get_first_ul_slot(tdd->nrofDownlinkSlots, tdd->nrofDownlinkSymbols, tdd->nrofUplinkSymbols) : 0;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_PUCCH_Config_t *pucch_Config = ul_bwp->pucch_Config; NR_PUCCH_Config_t *pucch_Config = ul_bwp->pucch_Config;
......
...@@ -47,7 +47,7 @@ const int get_ul_tda(gNB_MAC_INST *nrmac, const NR_ServingCellConfigCommon_t *sc ...@@ -47,7 +47,7 @@ const int get_ul_tda(gNB_MAC_INST *nrmac, const NR_ServingCellConfigCommon_t *sc
if (tdd && tdd->nrofUplinkSymbols > 1) { // if there is uplink symbols in mixed slot if (tdd && tdd->nrofUplinkSymbols > 1) { // if there is uplink symbols in mixed slot
const int nr_slots_period = tdd->nrofDownlinkSlots + tdd->nrofUplinkSlots + 1; const int nr_slots_period = tdd->nrofDownlinkSlots + tdd->nrofUplinkSlots + 1;
if ((slot%nr_slots_period) == tdd->nrofDownlinkSlots) if ((slot % nr_slots_period) == tdd->nrofDownlinkSlots)
return 2; return 2;
} }
...@@ -1305,8 +1305,7 @@ long get_K2(NR_PUSCH_TimeDomainResourceAllocationList_t *tdaList, ...@@ -1305,8 +1305,7 @@ long get_K2(NR_PUSCH_TimeDomainResourceAllocationList_t *tdaList,
return 3; return 3;
} }
static bool nr_UE_is_to_be_scheduled(const NR_ServingCellConfigCommon_t *scc, static bool nr_UE_is_to_be_scheduled(const NR_ServingCellConfigCommon_t *scc, int CC_id, NR_UE_info_t* UE, frame_t frame, sub_frame_t slot, uint32_t ulsch_max_frame_inactivity)
int CC_id, NR_UE_info_t* UE, frame_t frame, sub_frame_t slot, uint32_t ulsch_max_frame_inactivity)
{ {
const int n = nr_slots_per_frame[*scc->ssbSubcarrierSpacing]; const int n = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
const int now = frame * n + slot; const int now = frame * n + slot;
...@@ -1317,10 +1316,9 @@ static bool nr_UE_is_to_be_scheduled(const NR_ServingCellConfigCommon_t *scc, ...@@ -1317,10 +1316,9 @@ static bool nr_UE_is_to_be_scheduled(const NR_ServingCellConfigCommon_t *scc,
scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL; scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
int num_slots_per_period; int num_slots_per_period;
int last_ul_slot; int last_ul_slot;
int tdd_period_len[8] = {500,625,1000,1250,2000,2500,5000,10000};
if (tdd) { // Force the default transmission in a full slot as early as possible in the UL portion of TDD period (last_ul_slot) if (tdd) { // Force the default transmission in a full slot as early as possible in the UL portion of TDD period (last_ul_slot)
num_slots_per_period = n*tdd_period_len[tdd->dl_UL_TransmissionPeriodicity]/10000; num_slots_per_period = n / get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity);
last_ul_slot=1+tdd->nrofDownlinkSlots; last_ul_slot = 1 + tdd->nrofDownlinkSlots;
} else { } else {
num_slots_per_period = n; num_slots_per_period = n;
last_ul_slot = sched_ctrl->last_ul_slot; last_ul_slot = sched_ctrl->last_ul_slot;
......
...@@ -886,7 +886,7 @@ static void set_SR_periodandoffset(NR_SchedulingRequestResourceConfig_t *schedul ...@@ -886,7 +886,7 @@ static void set_SR_periodandoffset(NR_SchedulingRequestResourceConfig_t *schedul
const NR_TDD_UL_DL_Pattern_t *tdd = scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL; const NR_TDD_UL_DL_Pattern_t *tdd = scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
int sr_slot = 1; // in FDD SR in slot 1 int sr_slot = 1; // in FDD SR in slot 1
if(tdd) if(tdd)
sr_slot = tdd->nrofDownlinkSlots; // SR in the first uplink slot sr_slot = get_first_ul_slot(tdd->nrofDownlinkSlots, tdd->nrofDownlinkSymbols, tdd->nrofUplinkSymbols);
schedulingRequestResourceConfig->periodicityAndOffset = calloc(1,sizeof(*schedulingRequestResourceConfig->periodicityAndOffset)); schedulingRequestResourceConfig->periodicityAndOffset = calloc(1,sizeof(*schedulingRequestResourceConfig->periodicityAndOffset));
...@@ -1286,7 +1286,7 @@ void set_csi_meas_periodicity(const NR_ServingCellConfigCommon_t *scc, NR_CSI_Re ...@@ -1286,7 +1286,7 @@ void set_csi_meas_periodicity(const NR_ServingCellConfigCommon_t *scc, NR_CSI_Re
const int n_slots_period = tdd ? n_slots_frame / get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity) : n_slots_frame; const int n_slots_period = tdd ? n_slots_frame / get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity) : n_slots_frame;
const int ideal_period = MAX_MOBILES_PER_GNB * 2 * n_slots_period / n_ul_slots_period; // 2 reports per UE const int ideal_period = MAX_MOBILES_PER_GNB * 2 * n_slots_period / n_ul_slots_period; // 2 reports per UE
AssertFatal(ideal_period < 320, "Not enough UL slots to accomodate all possible UEs. Need to rework the implementation\n"); AssertFatal(ideal_period < 320, "Not enough UL slots to accomodate all possible UEs. Need to rework the implementation\n");
const int first_ul_slot_period = tdd ? tdd->nrofDownlinkSlots : 0; const int first_ul_slot_period = tdd ? get_first_ul_slot(tdd->nrofDownlinkSlots, tdd->nrofDownlinkSymbols, tdd->nrofUplinkSymbols) : 0;
const int idx = (uid << 1) + is_rsrp; const int idx = (uid << 1) + is_rsrp;
const int offset = first_ul_slot_period + idx % n_ul_slots_period + (idx / n_ul_slots_period) * n_slots_period; const int offset = first_ul_slot_period + idx % n_ul_slots_period + (idx / n_ul_slots_period) * n_slots_period;
......
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