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Commit e2ee13e9 authored by Raymond Knopp's avatar Raymond Knopp
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modifications for DCI size of format 1_0 for RAR and filling of FAPI for RAR... 

modifications for DCI size of format 1_0 for RAR and filling of FAPI for RAR according to special RAR-related configuration
parent edeb9ea7
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Showing with 114 additions and 88 deletions
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @ e2ee13e9
......@@ -394,7 +394,7 @@ int configure_fapi_dl_pdu(int Mod_idP,
rnti_types[0] = NR_RNTI_C;
pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,pdcch_pdu_rel15->BWPSize);
LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
......@@ -846,6 +846,6 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,pdcch_pdu_rel15->BWPSize);
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ e2ee13e9
......@@ -534,10 +534,11 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats,
int *rnti_types
int *rnti_types,
int N_RB
) {
uint16_t N_RB = pdcch_pdu_rel15->BWPSize;
uint8_t fsize=0, pos=0;
for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
......@@ -546,7 +547,9 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
AssertFatal(pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported");
int dci_size = pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d];
*dci_pdu=0;
/// Payload generation
switch(dci_formats[d]) {
case NR_DL_DCI_FORMAT_1_0:
......@@ -563,7 +566,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
pos+=4;
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos));
#ifdef DEBUG_FILL_DCI
LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu);
LOG_D(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu);
#endif
// VRB to PRB mapping
......
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @ e2ee13e9
......@@ -176,7 +176,8 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats,
int *rnti_types);
int *rnti_types,
int N_RB);
int get_spf(nfapi_nr_config_request_scf_t *cfg);
......
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @ e2ee13e9
......@@ -85,56 +85,60 @@ typedef enum {
/*! \brief gNB template for the Random access information */
typedef struct {
/// Flag to indicate this process is active
RA_state_t state;
/// Slot where preamble was received
uint8_t preamble_slot;
/// Subframe where Msg2 is to be sent
uint8_t Msg2_slot;
/// Frame where Msg2 is to be sent
frame_t Msg2_frame;
/// Subframe where Msg3 is to be sent
sub_frame_t Msg3_slot;
/// Frame where Msg3 is to be sent
frame_t Msg3_frame;
/// Subframe where Msg4 is to be sent
sub_frame_t Msg4_slot;
/// Frame where Msg4 is to be sent
frame_t Msg4_frame;
/// harq_pid used for Msg4 transmission
uint8_t harq_pid;
/// UE RNTI allocated during RAR
rnti_t rnti;
/// RA RNTI allocated from received PRACH
uint16_t RA_rnti;
/// Received preamble_index
uint8_t preamble_index;
/// Received UE Contention Resolution Identifier
uint8_t cont_res_id[6];
/// Timing offset indicated by PHY
int16_t timing_offset;
/// Timeout for RRC connection
int16_t RRC_timer;
/// Msg3 first RB
uint8_t msg3_first_rb;
/// Msg3 number of RB
uint8_t msg3_nb_rb;
/// Msg3 MCS
uint8_t msg3_mcs;
/// Msg3 TPC command
uint8_t msg3_TPC;
/// Msg3 ULdelay command
uint8_t msg3_ULdelay;
/// Msg3 cqireq command
uint8_t msg3_cqireq;
/// Round of Msg3 HARQ
uint8_t msg3_round;
/// TBS used for Msg4
int msg4_TBsize;
/// MCS used for Msg4
int msg4_mcs;
/// RA search space
NR_SearchSpace_t *ra_ss;
/// Flag to indicate this process is active
RA_state_t state;
/// BWP id of RA process
int bwp_id;
/// CORESET0 configured flag
int coreset0_configured;
/// Slot where preamble was received
uint8_t preamble_slot;
/// Subframe where Msg2 is to be sent
uint8_t Msg2_slot;
/// Frame where Msg2 is to be sent
frame_t Msg2_frame;
/// Subframe where Msg3 is to be sent
sub_frame_t Msg3_slot;
/// Frame where Msg3 is to be sent
frame_t Msg3_frame;
/// Subframe where Msg4 is to be sent
sub_frame_t Msg4_slot;
/// Frame where Msg4 is to be sent
frame_t Msg4_frame;
/// harq_pid used for Msg4 transmission
uint8_t harq_pid;
/// UE RNTI allocated during RAR
rnti_t rnti;
/// RA RNTI allocated from received PRACH
uint16_t RA_rnti;
/// Received preamble_index
uint8_t preamble_index;
/// Received UE Contention Resolution Identifier
uint8_t cont_res_id[6];
/// Timing offset indicated by PHY
int16_t timing_offset;
/// Timeout for RRC connection
int16_t RRC_timer;
/// Msg3 first RB
uint8_t msg3_first_rb;
/// Msg3 number of RB
uint8_t msg3_nb_rb;
/// Msg3 MCS
uint8_t msg3_mcs;
/// Msg3 TPC command
uint8_t msg3_TPC;
/// Msg3 ULdelay command
uint8_t msg3_ULdelay;
/// Msg3 cqireq command
uint8_t msg3_cqireq;
/// Round of Msg3 HARQ
uint8_t msg3_round;
/// TBS used for Msg4
int msg4_TBsize;
/// MCS used for Msg4
int msg4_mcs;
/// RA search space
NR_SearchSpace_t *ra_ss;
} NR_RA_t;
/*! \brief gNB common channels */
......
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