also added a log message for DCI generation in MAC

changed uint8_t to void as return is not used in the calling function

this shouldn't affect the testing with cots ue

Created two dci_pdu's to hold dci configuration for UL and DL DCI.
This wasn't a problem before as only one DCI was scheduled.

Integration 2020 wk40 comprises the following udpates:

MR893 ULSCH decode mthread: 
- Enabled parallelization of ULSCH segments decoding, deinterleaving and rx rate matching.
  
MR896 Nsa remove band hardcodings:
- A missing commit from wk39, just a log change   

MR901 NR UE DCI improvements:
- Handling of DCI formats 0_0 and 0_1, including removing hard-coding and scheduling PUSCH with DCI parameters
- Blind decoding of DCIs based on size and format indicator
- Fix for segmentation fault during ULSCH encoding

MR895 support of RA procedure by implementing Msg3 on UE

MR908 NR DL scheduler improvements:
Preliminary work on the DL scheduler
- cleanup of DL scheduler, add interface preprocessor-postprocessor (`NR_UE_sched_ctrl_t`)
- postprocessor can handle multiple UEs. Preprocessor will follow soon (proportional fair scheduler)
- No MAC UE Context creation before end of RA (Msg 3)
These updates do not change anything performance wise (no additional scheduled slots, etc). 
This MR also reduces gNB log.

Conflicts:
	openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c
	openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
	openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c

MR 896 : Nsa remove band hardcodings  
Removes hardcodings of EUTRA and NR bands in UE_Capability_Enquiry and NR_UE Capability_Enquiry messages, providing them from the eNB config file and gNB over X2 respectively. Moreover, the SSB Absolute frequency of the gNB is now provided by the eNB configuration file (instead of being hardcoded at rrc_eNB.c)  

MR903 : pusch ta update  
Update of PUSCH Timing advance  

MR 900 : improve x2/rrc for ENDC  
This MR introduces several enhancements in X2AP and RRC to deal with ENDC. 
The main goal is to deal with UE's on/off and with various errors.
Includes :
- DC prep and DC overall X2 timers
- X2 messages for UE release and DC timers' timeout

because round 0 could be skipped if no pusch signal detected