Commit 23005bd4 authored by matzakos's avatar matzakos

After new merge of sidelink with develop, UE attachment and ping work fine....

After new merge of sidelink with develop, UE attachment and ping work fine. Low PHR value monitored at the eNB side. Need to find the reason
parents da86b8a8 f885cc74
......@@ -1559,8 +1559,8 @@ void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB
}
}
if ( LOG_DEBUGFLAG(DEBUG_UE_PHYPROC)) {
LOG_D(PHY,
if ( LOG_DEBUGFLAG(DEBUG_UE_PHYPROC)) { //LOG_DEBUGFLAG(DEBUG_UE_PHYPROC)) {
LOG_I(PHY,
"[UE %d][PUSCH %d] AbsSubframe %d.%d Generating PUSCH : first_rb %d, nb_rb %d, round %d, mcs %d, rv %d, "
"cyclic_shift %d (cyclic_shift_common %d,n_DMRS2 %d,n_PRS %d), ACK (%d,%d), O_ACK %d, ack_status_cw0 %d ack_status_cw1 %d bundling %d, Nbundled %d, CQI %d, RI %d\n",
Mod_id,harq_pid,frame_tx%1024,subframe_tx,
......
......@@ -77,6 +77,9 @@ static const eutra_band_t eutra_bands[] = {
{42, 3400 * MHz, 3600 * MHz, 3400 * MHz, 3600 * MHz, TDD},
{43, 3600 * MHz, 3800 * MHz, 3600 * MHz, 3800 * MHz, TDD},
{44, 703 * MHz, 803 * MHz, 703 * MHz, 803 * MHz, TDD},
// this area is reserved for non-3GPP bands
{99, 900 * MHz, 910 * MHz, 920 * MHz, 930 * MHz, FDD}
};
......
......@@ -2345,7 +2345,7 @@ ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP,
phr_p->R = 0;
LOG_D(MAC,
LOG_I(MAC,
"[UE %d] Frame %d report PHR with mapping (%d->%d) for LCID %d\n",
module_idP, frameP, get_PHR(module_idP, CC_id, eNB_index),
phr_p->PH, POWER_HEADROOM);
......
......@@ -107,7 +107,7 @@ mac_rrc_data_req(
RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB23);
if (LOG_DEBUGFLAG(DEBUG_RRC)) {
LOG_T(RRC,"[eNB %d] Frame %d BCCH request => SIB 2-3\n",Mod_idP,frameP);
LOG_T(RRC,"[eNB %d] Frame %d BCCH request => SIB 2-3 \n \n",Mod_idP,frameP);
for (int i=0; i<RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB23; i++) {
LOG_T(RRC,"%x.",buffer_pP[i]);
......@@ -117,7 +117,26 @@ mac_rrc_data_req(
} /* LOG_DEBUGFLAG(DEBUG_RRC) */
return(RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB23);
} else {
}
else if ((frameP%8) == 3) {
memcpy(&buffer_pP[0],
RC.rrc[Mod_idP]->carrier[CC_id].SIB181921,
RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB181921);
if (LOG_DEBUGFLAG(DEBUG_RRC)) {
LOG_T(RRC,"[eNB %d] Frame %d BCCH request => SIB 18,19,21, size:%d \n \n",Mod_idP,frameP, RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB181921);
for (int i=0; i<RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB181921; i++) {
LOG_T(RRC,"%x.",buffer_pP[i]);
}
LOG_T(RRC,"\n");
} /* LOG_DEBUGFLAG(DEBUG_RRC) */
return(RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB181921);
}
else {
return(0);
}
}
......@@ -209,6 +228,7 @@ mac_rrc_data_req(
}
if ((Srb_id & RAB_OFFSET) == BCCH_SI_BR) { // First SI message with SIB2/3
memcpy(&buffer_pP[0],
RC.rrc[Mod_idP]->carrier[CC_id].SIB23_BR,
RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB23_BR);
......
This diff is collapsed.
......@@ -109,6 +109,13 @@ uint8_t do_SIB23(uint8_t Mod_id,
#endif
);
uint8_t do_SIB_SL(uint8_t Mod_id,
int CC_id
#if defined(ENABLE_ITTI)
, RrcConfigurationReq *configuration
#endif
);
/**
\brief Generate an RRCConnectionRequest UL-CCCH-Message (UE) based on random string or S-TMSI. This
routine only generates an mo-data establishment cause.
......
......@@ -2452,7 +2452,7 @@ rrc_ue_decode_dcch(
const char siWindowLength[8][5] = {"1ms","2ms","5ms","10ms","15ms","20ms","40ms","ERR"};
const char siWindowLength_int[7] = {1,2,5,10,15,20,40};
const char SIBType[12][6] = {"SIB3","SIB4","SIB5","SIB6","SIB7","SIB8","SIB9","SIB10","SIB11","SIB12","SIB13","Spare"};
const char SIBType[13][6] = {"SIB3","SIB4","SIB5","SIB6","SIB7","SIB8","SIB9","SIB10","SIB11","SIB12","SIB13","SIB19","Spare"};
const char SIBPeriod[8][6]= {"rf8","rf16","rf32","rf64","rf128","rf256","rf512","ERR"};
int siPeriod_int[7] = {80,160,320,640,1280,2560,5120};
......@@ -4067,7 +4067,7 @@ void ue_measurement_report_triggering(protocol_ctxt_t *const ctxt_pP, const uint
ctxt_pP,
eNB_index);
UE_rrc_inst[ctxt_pP->module_id].HandoverInfoUe.measFlag = 1;
LOG_I(RRC,"[UE %d] Frame %d: A3 event detected, state: %d \n",
LOG_D(RRC,"[UE %d] Frame %d: A3 event detected, state: %d \n",
ctxt_pP->module_id, ctxt_pP->frame, UE_rrc_inst[ctxt_pP->module_id].Info[0].State);
} else {
if(UE_rrc_inst[ctxt_pP->module_id].measReportList[i][j] != NULL) {
......@@ -4121,7 +4121,7 @@ uint8_t check_trigger_meas_event(
uint8_t eNB_offset;
// uint8_t currentCellIndex = frame_parms->Nid_cell;
uint8_t tmp_offset;
LOG_I(RRC,"[UE %d] ofn(%ld) ocn(%ld) hys(%ld) ofs(%ld) ocs(%ld) a3_offset(%ld) ttt(%ld) rssi %3.1f\n",
LOG_D(RRC,"[UE %d] ofn(%ld) ocn(%ld) hys(%ld) ofs(%ld) ocs(%ld) a3_offset(%ld) ttt(%ld) rssi %3.1f\n",
ue_mod_idP,
ofn,ocn,hys,ofs,ocs,a3_offset,ttt,
10*log10(get_RSSI(ue_mod_idP,0))-get_rx_total_gain_dB(ue_mod_idP,0));
......
......@@ -662,6 +662,8 @@ typedef struct {
uint8_t sizeof_SIB1;
uint8_t *SIB23;
uint8_t sizeof_SIB23;
uint8_t *SIB181921;
uint8_t sizeof_SIB181921;
#if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0))
uint8_t *SIB1_BR;
uint8_t sizeof_SIB1_BR;
......
......@@ -226,6 +226,23 @@ init_SI(
, configuration
);
//Call sidelink SI creation routine
#if (LTE_RRC_VERSION >= MAKE_VERSION(10, 0, 0))
RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB181921 = 0;
RC.rrc[ctxt_pP->module_id]->carrier[CC_id].SIB181921 = (uint8_t *) malloc16(128);
AssertFatal(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].SIB181921!=NULL,"cannot allocate memory for SIB");
RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB181921 = do_SIB_SL(
ctxt_pP->module_id,
CC_id
#if defined(ENABLE_ITTI)
, configuration
#endif
);
AssertFatal(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB181921 != 255,"FATAL, RC.rrc[mod].carrier[CC_id].sizeof_SIB181921 == 255");
#endif
LOG_I(RRC, "Size of SIB1: %d, size of SIB23: %d, size of SIB181921: %d \n \n", RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB1, RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB23, RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB181921);
AssertFatal(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB23 != 255,"FATAL, RC.rrc[mod].carrier[CC_id].sizeof_SIB23 == 255");
#if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0))
......
......@@ -171,6 +171,7 @@ static const eutra_band_t eutra_bands[] = {
{42, 3400 * MHz, 3600 * MHz, 3400 * MHz, 3600 * MHz, TDD},
{43, 3600 * MHz, 3800 * MHz, 3600 * MHz, 3800 * MHz, TDD},
{44, 703 * MHz, 803 * MHz, 703 * MHz, 803 * MHz, TDD},
{99, 900 * MHz, 910 * MHz, 920 * MHz, 930 * MHz, FDD}
};
......@@ -989,55 +990,55 @@ static void *UE_thread_rxn_txnp4(void *arg) {
// Process Rx data for one sub-frame
lte_subframe_t sf_type = subframe_select( &UE->frame_parms, proc->subframe_rx);
if (UE->SLonly == 0) {
if ((sf_type == SF_DL) ||
(UE->frame_parms.frame_type == FDD) ||
(sf_type == SF_S)) {
if (UE->frame_parms.frame_type == TDD) {
LOG_D(PHY, "%s,TDD%d,%s: calling UE_RX\n",
threadname,
UE->frame_parms.tdd_config,
(sf_type==SF_DL? "SF_DL" :
(sf_type==SF_UL? "SF_UL" :
(sf_type==SF_S ? "SF_S" : "UNKNOWN_SF_TYPE"))));
} else {
LOG_D(PHY, "%s,%s,%s: calling UE_RX\n",
threadname,
(UE->frame_parms.frame_type==FDD? "FDD":
(UE->frame_parms.frame_type==TDD? "TDD":"UNKNOWN_DUPLEX_MODE")),
(sf_type==SF_DL? "SF_DL" :
(sf_type==SF_UL? "SF_UL" :
(sf_type==SF_S ? "SF_S" : "UNKNOWN_SF_TYPE"))));
}
#ifdef UE_SLOT_PARALLELISATION
phy_procedures_slot_parallelization_UE_RX( UE, proc, 0, 0, 1, UE->mode);
#else
phy_procedures_UE_RX( UE, proc, 0, 0, 1, UE->mode);
#endif
}
#if UE_TIMING_TRACE
start_meas(&UE->generic_stat);
#endif
if (UE->mac_enabled==1) {
ret = ue_scheduler(UE->Mod_id,
proc->frame_rx,
proc->subframe_rx,
proc->frame_tx,
proc->subframe_tx,
subframe_select(&UE->frame_parms,proc->subframe_tx),
0,
0/*FIXME CC_id*/);
if ( ret != CONNECTION_OK) {
LOG_E( PHY, "[UE %"PRIu8"] Frame %"PRIu32", subframe %u %s\n",
UE->Mod_id, proc->frame_rx, proc->subframe_tx,get_connectionloss_errstr(ret) );
}
}
#if UE_TIMING_TRACE
stop_meas(&UE->generic_stat);
#endif
if (UE->SLonly == 0) {
if ((sf_type == SF_DL) ||
(UE->frame_parms.frame_type == FDD) ||
(sf_type == SF_S)) {
if (UE->frame_parms.frame_type == TDD) {
LOG_D(PHY, "%s,TDD%d,%s: calling UE_RX\n",
threadname,
UE->frame_parms.tdd_config,
(sf_type==SF_DL? "SF_DL" :
(sf_type==SF_UL? "SF_UL" :
(sf_type==SF_S ? "SF_S" : "UNKNOWN_SF_TYPE"))));
} else {
LOG_D(PHY, "%s,%s,%s: calling UE_RX\n",
threadname,
(UE->frame_parms.frame_type==FDD? "FDD":
(UE->frame_parms.frame_type==TDD? "TDD":"UNKNOWN_DUPLEX_MODE")),
(sf_type==SF_DL? "SF_DL" :
(sf_type==SF_UL? "SF_UL" :
(sf_type==SF_S ? "SF_S" : "UNKNOWN_SF_TYPE"))));
}
#ifdef UE_SLOT_PARALLELISATION
phy_procedures_slot_parallelization_UE_RX( UE, proc, 0, 0, 1, UE->mode);
#else
phy_procedures_UE_RX( UE, proc, 0, 0, 1, UE->mode);
#endif
}
#if UE_TIMING_TRACE
start_meas(&UE->generic_stat);
#endif
if (UE->mac_enabled==1) {
ret = ue_scheduler(UE->Mod_id,
proc->frame_rx,
proc->subframe_rx,
proc->frame_tx,
proc->subframe_tx,
subframe_select(&UE->frame_parms,proc->subframe_tx),
0,
0/*FIXME CC_id*/);
if ( ret != CONNECTION_OK) {
LOG_E( PHY, "[UE %"PRIu8"] Frame %"PRIu32", subframe %u %s\n",
UE->Mod_id, proc->frame_rx, proc->subframe_tx,get_connectionloss_errstr(ret) );
}
}
#if UE_TIMING_TRACE
stop_meas(&UE->generic_stat);
#endif
// Prepare the future Tx data
......@@ -1046,7 +1047,7 @@ static void *UE_thread_rxn_txnp4(void *arg) {
(UE->frame_parms.frame_type == FDD) )
if (UE->mode != loop_through_memory)
//phy_procedures_UE_TX(UE,proc,0,0,UE->mode,no_relay);
phy_procedures_UE_TX(UE,proc,0,0,UE->mode);
phy_procedures_UE_TX(UE,proc,0,0,UE->mode);
......@@ -1056,7 +1057,7 @@ static void *UE_thread_rxn_txnp4(void *arg) {
phy_procedures_UE_S_TX(UE,0,0);
updateTimes(current, &t3, 10000, "Delay to process sub-frame (case 3)");
}
// This is for Sidelink
......
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