Commit 40cd42f0 authored by Valentin's avatar Valentin

feat(ldpc-offload-xdma): original commit with ldpc-offload-xdma, library omitted

parent e9344661
......@@ -2018,7 +2018,7 @@ set (SIMUSRC
${OPENAIR1_DIR}/SIMULATION/RF/adc.c
)
add_library(SIMU STATIC ${SIMUSRC} )
target_link_libraries(SIMU PRIVATE cblas)
target_link_libraries(SIMU PRIVATE blas)
target_include_directories(SIMU PUBLIC ${OPENAIR1_DIR}/SIMULATION/TOOLS ${OPENAIR1_DIR}/SIMULATION/RF)
# Qt-based scope
......@@ -2241,6 +2241,9 @@ target_link_libraries(lte-uesoftmodem PRIVATE
# nr-softmodem
###################################################
include_directories(${OPENAIR_DIR}/cmake_targets/xdma_driver) #Include header path
link_directories(${OPENAIR_DIR}/cmake_targets/xdma_driver) #Link STATIC Library path
add_executable(nr-softmodem
${rrc_h}
${nr_rrc_h}
......@@ -2277,7 +2280,7 @@ target_link_libraries(nr-softmodem PRIVATE
ITTI ${NAS_UE_LIB} lte_rrc nr_rrc
ngap s1ap L2_LTE_NR L2_NR MAC_NR_COMMON NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB SIMU SIMU_ETH
x2ap f1ap m2ap m3ap e1ap
-Wl,--end-group z dl)
-Wl,--end-group z dl fpga_ldpc)
target_link_libraries(nr-softmodem PRIVATE pthread m CONFIG_LIB rt crypt ${CRYPTO_LIBRARIES} ${OPENSSL_LIBRARIES} sctp ${ATLAS_LIBRARIES})
target_link_libraries(nr-softmodem PRIVATE ${T_LIB})
......@@ -2441,7 +2444,7 @@ add_executable(nr_dlschsim
)
target_link_libraries(nr_dlschsim PRIVATE
-Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI dl
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI dl fpga_ldpc
)
target_link_libraries(nr_dlschsim PRIVATE asn1_nr_rrc_hdrs)
......@@ -2459,7 +2462,7 @@ add_executable(nr_pbchsim
)
target_link_libraries(nr_pbchsim PRIVATE
-Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI dl
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI dl fpga_ldpc
)
target_link_libraries(nr_pbchsim PRIVATE asn1_nr_rrc_hdrs asn1_lte_rrc_hdrs)
......@@ -2479,7 +2482,7 @@ add_executable(nr_pucchsim
)
target_link_libraries(nr_pucchsim PRIVATE
-Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI dl
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI dl fpga_ldpc
)
target_link_libraries(nr_pucchsim PRIVATE asn1_nr_rrc_hdrs asn1_lte_rrc_hdrs)
......@@ -2504,7 +2507,7 @@ add_executable(nr_dlsim
)
target_link_libraries(nr_dlsim PRIVATE
-Wl,--start-group UTIL SIMU SIMU_ETH PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON nr_rrc CONFIG_LIB L2_NR HASHTABLE x2ap SECU_CN ngap -lz -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI ${OPENSSL_LIBRARIES} dl
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI ${OPENSSL_LIBRARIES} dl fpga_ldpc
)
target_link_libraries(nr_dlsim PRIVATE asn1_nr_rrc_hdrs asn1_lte_rrc_hdrs)
......@@ -2522,7 +2525,7 @@ add_executable(nr_prachsim
${SHLIB_LOADER_SOURCES})
target_link_libraries(nr_prachsim PRIVATE
-Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_RU PHY_NR_UE MAC_NR_COMMON SCHED_NR_LIB CONFIG_LIB -lz -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI ${OPENSSL_LIBRARIES} dl)
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI ${OPENSSL_LIBRARIES} dl fpga_ldpc)
target_link_libraries(nr_prachsim PRIVATE asn1_nr_rrc_hdrs asn1_lte_rrc_hdrs)
add_executable(nr_ulschsim
......@@ -2542,7 +2545,7 @@ add_executable(nr_ulschsim
)
target_link_libraries(nr_ulschsim PRIVATE
-Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI dl
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI dl fpga_ldpc
)
target_link_libraries(nr_ulschsim PRIVATE asn1_nr_rrc_hdrs asn1_lte_rrc_hdrs)
......@@ -2572,7 +2575,7 @@ endif()
target_link_libraries(nr_ulsim PRIVATE
-Wl,--start-group UTIL SIMU SIMU_ETH PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON nr_rrc CONFIG_LIB L2_NR HASHTABLE x2ap SECU_CN ngap -lz -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI ${OPENSSL_LIBRARIES} dl
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ITTI ${OPENSSL_LIBRARIES} dl fpga_ldpc
)
target_link_libraries(nr_ulsim PRIVATE asn1_nr_rrc_hdrs asn1_lte_rrc_hdrs)
......
......@@ -685,6 +685,7 @@ typedef struct PHY_VARS_gNB_s {
uint32_t ofdm_offset_divisor;
int ldpc_offload_flag;
int ldpc_fpga_flag; // Xilinx 8038 FPGA Hardware(by VT)
int max_ldpc_iterations;
/// indicate the channel estimation technique in time domain
......@@ -750,6 +751,7 @@ typedef struct PHY_VARS_gNB_s {
time_stats_t ulsch_rbs_extraction_stats;
time_stats_t ulsch_mrc_stats;
time_stats_t ulsch_llr_stats;
time_stats_t ulsch_ldpc_fpga_time_stats;
time_stats_t rx_srs_stats;
time_stats_t generate_srs_stats;
time_stats_t get_srs_signal_stats;
......
......@@ -209,6 +209,7 @@ int main(int argc, char *argv[])
double effTP;
float eff_tp_check = 100;
int ldpc_offload_flag = 0;
int fpga_optional = 0; // FPGA 8038
uint8_t max_rounds = 4;
int chest_type[2] = {0};
int enable_ptrs = 0;
......@@ -361,8 +362,12 @@ int main(int argc, char *argv[])
n_trials = atoi(optarg);
break;
// case 'o':
// ldpc_offload_flag = 1;
// break;
case 'o':
ldpc_offload_flag = 1;
fpga_optional = 1;
break;
case 'p':
......@@ -688,6 +693,7 @@ int main(int argc, char *argv[])
// nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,0,0x01);
gNB->ldpc_offload_flag = ldpc_offload_flag;
gNB->ldpc_fpga_flag = fpga_optional; // FPGA Xilinx 8038
gNB->chest_freq = chest_type[0];
gNB->chest_time = chest_type[1];
......@@ -880,7 +886,8 @@ int main(int argc, char *argv[])
ulsch_input_buffer[0] = 0x31;
for (i = 1; i < TBS/8; i++) {
ulsch_input_buffer[i] = (unsigned char) rand();
//ulsch_input_buffer[i] = (unsigned char) rand();
ulsch_input_buffer[i] = i & 0xff;
}
uint8_t ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, Imcs, mcs_table);
......
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