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lizhongxiao
OpenXG-RAN
Commits
42e4dce7
Commit
42e4dce7
authored
May 17, 2018
by
Raymond Knopp
Browse files
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Plain Diff
testing and modifications with external 10 MHz clock reference
parent
427eabb8
Changes
5
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Showing
5 changed files
with
82 additions
and
24 deletions
+82
-24
openair1/PHY/LTE_ESTIMATION/lte_sync_time.c
openair1/PHY/LTE_ESTIMATION/lte_sync_time.c
+4
-3
openair1/PHY/LTE_TRANSPORT/slbch.c
openair1/PHY/LTE_TRANSPORT/slbch.c
+4
-0
openair1/PHY/LTE_TRANSPORT/slsss.c
openair1/PHY/LTE_TRANSPORT/slsss.c
+20
-16
targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
+0
-1
targets/RT/USER/lte-ue.c
targets/RT/USER/lte-ue.c
+54
-4
No files found.
openair1/PHY/LTE_ESTIMATION/lte_sync_time.c
View file @
42e4dce7
...
...
@@ -54,7 +54,7 @@ int lte_sync_time_init(LTE_DL_FRAME_PARMS *frame_parms ) // LTE_UE_COMMON *com
int
i
,
k
;
sync_corr_ue0
=
(
int32_t
*
)
malloc16
(
LTE_NUMBER_OF_SUBFRAMES_PER_FRAME
*
sizeof
(
int32_t
)
*
frame_parms
->
samples_per_tti
);
sync_corr_ue1
=
(
int32_t
*
)
malloc16
(
LTE_NUMBER_OF_SUBFRAMES_PER_FRAME
*
sizeof
(
int32_t
)
*
frame_parms
->
samples_per_tti
);
sync_corr_ue1
=
(
int32_t
*
)
malloc16
(
4
*
LTE_NUMBER_OF_SUBFRAMES_PER_FRAME
*
sizeof
(
int32_t
)
*
frame_parms
->
samples_per_tti
);
sync_corr_ue2
=
(
int32_t
*
)
malloc16
(
LTE_NUMBER_OF_SUBFRAMES_PER_FRAME
*
sizeof
(
int32_t
)
*
frame_parms
->
samples_per_tti
);
if
(
sync_corr_ue0
)
{
...
...
@@ -708,14 +708,15 @@ int lte_sync_timeSL(PHY_VARS_UE *ue,
}
sync_corr0
[
nprime
]
=
magtmp0
;
sync_corr1
[
nprime
]
=
magtmp1
;
if
(
n
<
FRAME_LENGTH_COMPLEX_SAMPLES
)
sync_corr_ue1
[
n
]
=
magtmp1
;
if
(
n
<
4
*
FRAME_LENGTH_COMPLEX_SAMPLES
)
sync_corr_ue1
[
n
]
=
magtmp1
;
}
avg0
/=
(
length
/
4
);
avg1
/=
(
length
/
4
);
// PSS in symbol 1
int
pssoffset
=
frame_parms
->
ofdm_symbol_size
+
frame_parms
->
nb_prefix_samples0
;
printf
(
"maxpos1 = %d, pssoffset = %d
\n
"
,
maxpos1
,
pssoffset
);
if
(
maxlev0
>
maxlev1
)
{
if
((
int64_t
)
maxlev0
>
(
5
*
avg0
))
{
*
lev
=
maxlev0
;
*
ind
=
0
;
*
avg
=
avg0
;
return
((
length
+
maxpos0
-
pssoffset
)
%
length
);};
}
...
...
openair1/PHY/LTE_TRANSPORT/slbch.c
View file @
42e4dce7
...
...
@@ -42,6 +42,8 @@
#define PSBCH_A 40
#define PSBCH_E 1008 //12REs/PRB*6PRBs*7symbols*2 bits/RB
#define PSBCH_DEBUG 1
...
...
@@ -150,6 +152,8 @@ int rx_psbch(PHY_VARS_UE *ue) {
ru_tmp
.
common
.
rxdata_7_5kHz
[
aa
]
=
(
int32_t
*
)
&
ue
->
common_vars
.
rxdata_syncSL
[
aa
][
ue
->
rx_offsetSL
*
2
];
ru_tmp
.
common
.
rxdataF
=
(
int32_t
**
)
rxdataF
;
ru_tmp
.
nb_rx
=
ue
->
frame_parms
.
nb_antennas_rx
;
LOG_I
(
PHY
,
"Running PBCH detection with Nid_SL %d
\n
"
,
ue
->
frame_parms
.
Nid_SL
);
for
(
int
l
=
0
;
l
<
11
;
l
++
)
{
slot_fep_ul
(
&
ru_tmp
,
l
%
7
,(
l
>
6
)
?
1
:
0
,
0
);
...
...
openair1/PHY/LTE_TRANSPORT/slsss.c
View file @
42e4dce7
...
...
@@ -100,7 +100,7 @@ int slpss_ch_est(PHY_VARS_UE *ue,
{
int16_t
*
pss
;
int16_t
*
pss0_ext2
,
*
sss0_ext2
,
*
sss0_ext3
,
*
sss1_ext3
,
tmp
_re
,
tmp
_im
,
tmp0_re2
,
tmp0_im2
,
tmp1_re2
,
tmp1_im2
;
int16_t
*
pss0_ext2
,
*
sss0_ext2
,
*
sss0_ext3
,
*
sss1_ext3
,
tmp
0_re
,
tmp0_im
,
tmp1_re
,
tmp1
_im
,
tmp0_re2
,
tmp0_im2
,
tmp1_re2
,
tmp1_im2
;
int16_t
*
pss1_ext2
,
*
sss1_ext2
;
uint8_t
aarx
,
i
;
...
...
@@ -134,19 +134,22 @@ int slpss_ch_est(PHY_VARS_UE *ue,
for
(
i
=
0
;
i
<
62
;
i
++
)
{
// This is H*(PSS) = R* \cdot PSS
tmp_re
=
(
int16_t
)((((
pss0_ext2
[
i
<<
1
]
+
pss1_ext2
[
i
<<
1
])
*
(
int32_t
)
pss
[
i
<<
1
])
>>
15
)
+
(((
pss0_ext2
[
1
+
(
i
<<
1
)]
+
pss1_ext2
[
1
+
(
i
<<
1
)])
*
(
int32_t
)
pss
[
1
+
(
i
<<
1
)])
>>
15
));
tmp_im
=
(
int16_t
)((((
pss0_ext2
[
i
<<
1
]
+
pss1_ext2
[
i
<<
1
])
*
(
int32_t
)
pss
[
1
+
(
i
<<
1
)])
>>
15
)
-
(((
pss0_ext2
[
1
+
(
i
<<
1
)]
+
pss1_ext2
[
1
+
(
i
<<
1
)])
*
(
int32_t
)
pss
[(
i
<<
1
)])
>>
15
));
tmp0_re
=
(
int16_t
)((((
pss0_ext2
[
i
<<
1
])
*
(
int32_t
)
pss
[
i
<<
1
])
>>
15
)
+
(((
pss0_ext2
[
1
+
(
i
<<
1
)])
*
(
int32_t
)
pss
[
1
+
(
i
<<
1
)])
>>
15
));
tmp0_im
=
(
int16_t
)((((
pss0_ext2
[
i
<<
1
])
*
(
int32_t
)
pss
[
1
+
(
i
<<
1
)])
>>
15
)
-
(((
pss0_ext2
[
1
+
(
i
<<
1
)])
*
(
int32_t
)
pss
[(
i
<<
1
)])
>>
15
));
tmp1_re
=
(
int16_t
)((((
pss1_ext2
[
i
<<
1
])
*
(
int32_t
)
pss
[
i
<<
1
])
>>
15
)
+
(((
pss1_ext2
[
1
+
(
i
<<
1
)])
*
(
int32_t
)
pss
[
1
+
(
i
<<
1
)])
>>
15
));
tmp1_im
=
(
int16_t
)((((
pss1_ext2
[
i
<<
1
])
*
(
int32_t
)
pss
[
1
+
(
i
<<
1
)])
>>
15
)
-
(((
pss1_ext2
[
1
+
(
i
<<
1
)])
*
(
int32_t
)
pss
[(
i
<<
1
)])
>>
15
));
// printf("H*(%d,%d) : (%d,%d)\n",aarx,i,tmp_re,tmp_im);
// This is R(SSS0) \cdot H*(PSS)
tmp0_re2
=
(
int16_t
)(((
tmp
_re
*
(
int32_t
)
sss0_ext2
[
i
<<
1
])
>>
15
)
-
((
tmp
_im
*
(
int32_t
)
sss0_ext2
[
1
+
(
i
<<
1
)])
>>
15
));
tmp0_im2
=
(
int16_t
)(((
tmp
_re
*
(
int32_t
)
sss0_ext2
[
1
+
(
i
<<
1
)])
>>
15
)
+
((
tmp
_im
*
(
int32_t
)
sss0_ext2
[(
i
<<
1
)])
>>
15
));
tmp0_re2
=
(
int16_t
)(((
tmp
0_re
*
(
int32_t
)
sss0_ext2
[
i
<<
1
])
>>
12
)
-
((
tmp
0_im
*
(
int32_t
)
sss0_ext2
[
1
+
(
i
<<
1
)])
>>
12
));
tmp0_im2
=
(
int16_t
)(((
tmp
0_re
*
(
int32_t
)
sss0_ext2
[
1
+
(
i
<<
1
)])
>>
12
)
+
((
tmp
0_im
*
(
int32_t
)
sss0_ext2
[(
i
<<
1
)])
>>
12
));
// This is R(SSS1) \cdot H*(PSS)
tmp1_re2
=
(
int16_t
)(((
tmp
_re
*
(
int32_t
)
sss1_ext2
[
i
<<
1
])
>>
15
)
-
((
tmp
_im
*
(
int32_t
)
sss1_ext2
[
1
+
(
i
<<
1
)])
>>
15
));
tmp1_im2
=
(
int16_t
)(((
tmp
_re
*
(
int32_t
)
sss1_ext2
[
1
+
(
i
<<
1
)])
>>
15
)
+
((
tmp
_im
*
(
int32_t
)
sss1_ext2
[(
i
<<
1
)])
>>
15
));
tmp1_re2
=
(
int16_t
)(((
tmp
1_re
*
(
int32_t
)
sss1_ext2
[
i
<<
1
])
>>
12
)
-
((
tmp
1_im
*
(
int32_t
)
sss1_ext2
[
1
+
(
i
<<
1
)])
>>
12
));
tmp1_im2
=
(
int16_t
)(((
tmp
1_re
*
(
int32_t
)
sss1_ext2
[
1
+
(
i
<<
1
)])
>>
12
)
+
((
tmp
1_im
*
(
int32_t
)
sss1_ext2
[(
i
<<
1
)])
>>
12
));
// printf("SSSi(%d,%d) : (%d,%d)\n",aarx,i,sss_ext2[i<<1],sss_ext2[1+(i<<1)]);
// printf("SSSo(%d,%d) : (%d,%d)\n",aarx,i,tmp_re2,tmp_im2);
...
...
@@ -342,8 +345,8 @@ int rx_slsss(PHY_VARS_UE *ue,int32_t *tot_metric,uint8_t *phase_max,int Nid2)
0
);
// write_output("rxdataF0.m","rxF0",&rxdataF[0][0],2*14*ue->frame_parms.ofdm_symbol_size,1,1);
//
write_output("pss0_ext.m","pss0ext",pss0_ext,72,1,1);
//
write_output("sss0_ext.m","sss0ext",sss0_ext,72,1,1);
write_output
(
"pss0_ext.m"
,
"pss0ext"
,
pss0_ext
,
72
,
1
,
1
);
write_output
(
"sss0_ext.m"
,
"sss0ext"
,
sss0_ext
,
72
,
1
,
1
);
// exit(-1);
...
...
@@ -357,7 +360,8 @@ int rx_slsss(PHY_VARS_UE *ue,int32_t *tot_metric,uint8_t *phase_max,int Nid2)
sss1_ext
,
Nid2
);
// write_output("sss0_comp0.m","sss0comp0",sss0_ext,72,1,1);
write_output
(
"sss0_comp0.m"
,
"sss0comp0"
,
sss0_ext
,
72
,
1
,
1
);
write_output
(
"sss1_comp0.m"
,
"sss1comp0"
,
sss1_ext
,
72
,
1
,
1
);
// exit(-1);
// now do the SSS detection based on the precomputed sequences in PHY/LTE_TRANSPORT/sss.h
...
...
@@ -377,8 +381,8 @@ int rx_slsss(PHY_VARS_UE *ue,int32_t *tot_metric,uint8_t *phase_max,int Nid2)
// This is the inner product using one particular value of each unknown parameter
for
(
i
=
0
;
i
<
62
;
i
++
)
{
metric
+=
(
int16_t
)(((
d0
[
i
]
*
((((
phaseSL_re
[
phase
]
*
(
int32_t
)
sss0
[
i
<<
1
])
>>
1
9
)
-
((
phaseSL_im
[
phase
]
*
(
int32_t
)
sss0
[
1
+
(
i
<<
1
)])
>>
19
))))))
+
(
int16_t
)(((
d5
[
i
]
*
((((
phaseSL_re
[
phase
]
*
(
int32_t
)
sss1
[
i
<<
1
])
>>
1
9
)
-
((
phaseSL_im
[
phase
]
*
(
int32_t
)
sss1
[
1
+
(
i
<<
1
)])
>>
19
))))));
(
int16_t
)(((
d0
[
i
]
*
((((
phaseSL_re
[
phase
]
*
(
int32_t
)
sss0
[
i
<<
1
])
>>
1
5
)
-
((
phaseSL_im
[
phase
]
*
(
int32_t
)
sss0
[
1
+
(
i
<<
1
)])
>>
15
))))))
+
(
int16_t
)(((
d5
[
i
]
*
((((
phaseSL_re
[
phase
]
*
(
int32_t
)
sss1
[
i
<<
1
])
>>
1
5
)
-
((
phaseSL_im
[
phase
]
*
(
int32_t
)
sss1
[
1
+
(
i
<<
1
)])
>>
15
))))));
}
// if the current metric is better than the last save it
...
...
targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
View file @
42e4dce7
...
...
@@ -1066,7 +1066,6 @@ extern "C" {
}
else
{
s
->
usrp
->
set_clock_source
(
"external"
);
s
->
usrp
->
set_time_source
(
"external"
);
}
device
->
type
=
USRP_B200_DEV
;
...
...
targets/RT/USER/lte-ue.c
View file @
42e4dce7
...
...
@@ -635,6 +635,8 @@ static void *UE_thread_synch(void *arg)
return
&
UE_thread_synch_retval
;
}
extern
int32_t
*
sync_corr_ue1
;
static
void
*
UE_thread_synchSL
(
void
*
arg
)
{
static
int
UE_thread_synch_retval
;
...
...
@@ -702,14 +704,62 @@ static void *UE_thread_synchSL(void *arg)
// the thread waits here most of the time
pthread_cond_wait
(
&
UE
->
proc
.
cond_synchSL
,
&
UE
->
proc
.
mutex_synchSL
);
AssertFatal
(
0
==
pthread_mutex_unlock
(
&
UE
->
proc
.
mutex_synchSL
),
""
);
LOG_I
(
PHY
,
"Running initial synch with carrier offset %d, ue_scan_carrier %d
\n
"
,
freq_offset
,
UE
->
UE_scan_carrier
);
// Do initial synch here
if
(
initial_syncSL
(
UE
)
>=
0
)
LOG_I
(
PHY
,
"Found SynchRef UE
\n
"
);
if
(
initial_syncSL
(
UE
)
>=
0
)
{
LOG_I
(
PHY
,
"Found SynchRef UE
\n
"
);
// rerun with new cell parameters and frequency-offset
for
(
i
=
0
;
i
<
openair0_cfg
[
UE
->
rf_map
.
card
].
rx_num_channels
;
i
++
)
{
openair0_cfg
[
UE
->
rf_map
.
card
].
rx_gain
[
UE
->
rf_map
.
chain
+
i
]
=
UE
->
rx_total_gain_dB
;
//-USRP_GAIN_OFFSET;
if
(
UE
->
UE_scan_carrier
==
1
)
{
if
(
freq_offset
>=
0
)
openair0_cfg
[
UE
->
rf_map
.
card
].
rx_freq
[
UE
->
rf_map
.
chain
+
i
]
+=
abs
(
UE
->
common_vars
.
freq_offset
);
else
openair0_cfg
[
UE
->
rf_map
.
card
].
rx_freq
[
UE
->
rf_map
.
chain
+
i
]
-=
abs
(
UE
->
common_vars
.
freq_offset
);
freq_offset
=
0
;
}
}
UE
->
rfdevice
.
trx_set_freq_func
(
&
UE
->
rfdevice
,
&
openair0_cfg
[
0
],
0
);
//UE->rfdevice.trx_set_gains_func(&openair0,&openair0_cfg[0]);
//UE->rfdevice.trx_stop_func(&UE->rfdevice);
sleep
(
1
);
if
(
UE
->
UE_scan_carrier
==
1
)
{
UE
->
UE_scan_carrier
=
0
;
}
else
{
AssertFatal
(
0
==
pthread_mutex_lock
(
&
UE
->
proc
.
mutex_synch
),
""
);
UE
->
is_synchronizedSL
=
1
;
AssertFatal
(
0
==
pthread_mutex_unlock
(
&
UE
->
proc
.
mutex_synch
),
""
);
}
}
else
{
LOG_I
(
PHY
,
"No SynchRefUE found
\n
"
);
LOG_I
(
PHY
,
"No SynchRefUE found
\n
"
);
/*
write_output("rxsig0.m","rxs0",&UE->common_vars.rxdata_syncSL[0][0],40*UE->frame_parms.samples_per_tti,1,1);
write_output("corr.m","corr1",sync_corr_ue1,40*UE->frame_parms.samples_per_tti,1,2);
exit(-1);
}
*/
if
(
UE
->
UE_scan_carrier
==
1
)
{
if
(
freq_offset
>=
0
)
freq_offset
+=
100
;
freq_offset
*=-
1
;
if
(
abs
(
freq_offset
)
>
7500
)
AssertFatal
(
1
==
0
,
"[initial_sync] No cell synchronization found, abandoning
\n
"
);
}
for
(
i
=
0
;
i
<
openair0_cfg
[
UE
->
rf_map
.
card
].
rx_num_channels
;
i
++
)
{
openair0_cfg
[
UE
->
rf_map
.
card
].
rx_freq
[
UE
->
rf_map
.
chain
+
i
]
=
(
double
)
UE
->
frame_parms
.
ul_CarrierFreq
+
freq_offset
;
openair0_cfg
[
UE
->
rf_map
.
card
].
tx_freq
[
UE
->
rf_map
.
chain
+
i
]
=
(
double
)
UE
->
frame_parms
.
ul_CarrierFreq
+
freq_offset
;
openair0_cfg
[
UE
->
rf_map
.
card
].
rx_gain
[
UE
->
rf_map
.
chain
+
i
]
=
UE
->
rx_total_gain_dB
;
//-USRP_GAIN_OFFSET;
if
(
UE
->
UE_scan_carrier
==
1
)
openair0_cfg
[
UE
->
rf_map
.
card
].
autocal
[
UE
->
rf_map
.
chain
+
i
]
=
1
;
}
LOG_I
(
PHY
,
"Setting USRP freq to %f
\n
"
,
openair0_cfg
[
UE
->
rf_map
.
card
].
rx_freq
[
0
]);
UE
->
rfdevice
.
trx_set_freq_func
(
&
UE
->
rfdevice
,
&
openair0_cfg
[
0
],
0
);
}
AssertFatal
(
0
==
pthread_mutex_lock
(
&
UE
->
proc
.
mutex_synchSL
),
""
);
UE
->
proc
.
instance_cnt_synchSL
--
;
UE
->
is_synchronizedSL
=
0
;
...
...
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