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Commit 6f290e71 authored by root's avatar root Committed by Florian Kaltenberger
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UE add RF board ZC706+AD9371 

Conflicts:
	cmake_targets/build_oai
	openair1/PHY/LTE_TRANSPORT/prach.c
	openair1/SCHED/phy_procedures_lte_ue.c
	targets/ARCH/COMMON/common_lib.h
	targets/RT/USER/lte-softmodem.c
parent c4fd4dca
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Showing with 3582 additions and 30 deletions
cmake_targets/CMakeLists.txt
View file @ 6f290e71
...@@ -484,7 +484,7 @@ include_directories ("${X2AP_DIR}") ...@@ -484,7 +484,7 @@ include_directories ("${X2AP_DIR}")
add_list1_option(NB_ANTENNAS_RX "2" "Number of antennas in reception" "1" "2" "4") add_list1_option(NB_ANTENNAS_RX "2" "Number of antennas in reception" "1" "2" "4")
add_list1_option(NB_ANTENNAS_TX "4" "Number of antennas in transmission" "1" "2" "4") add_list1_option(NB_ANTENNAS_TX "4" "Number of antennas in transmission" "1" "2" "4")
add_list2_option(RF_BOARD "EXMIMO" "RF head type" "None" "EXMIMO" "OAI_USRP" "OAI_BLADERF" "CPRIGW" "OAI_LMSSDR") add_list2_option(RF_BOARD "EXMIMO" "RF head type" "None" "EXMIMO" "OAI_USRP" "OAI_BLADERF" "CPRIGW" "OAI_LMSSDR" "OAI_ADRV9371_ZC706")
add_list2_option(TRANSP_PRO "None" "Transport protocol type" "None" "ETHERNET") add_list2_option(TRANSP_PRO "None" "Transport protocol type" "None" "ETHERNET")
#NOKIA config enhancement #NOKIA config enhancement
...@@ -507,6 +507,11 @@ set (SHLIB_LOADER_SOURCES ...@@ -507,6 +507,11 @@ set (SHLIB_LOADER_SOURCES
) )
# include RF devices / transport protocols library modules # include RF devices / transport protocols library modules
###################################################################### ######################################################################
if (HWLAT)
add_definitions(-DHWLAT )
endif()
include_directories("${OPENAIR_TARGETS}/ARCH/EXMIMO/USERSPACE/LIB/") include_directories("${OPENAIR_TARGETS}/ARCH/EXMIMO/USERSPACE/LIB/")
include_directories ("${OPENAIR_TARGETS}/ARCH/EXMIMO/DEFS/") include_directories ("${OPENAIR_TARGETS}/ARCH/EXMIMO/DEFS/")
...@@ -761,6 +766,9 @@ include_directories("${OPENAIR3_DIR}/UDP") ...@@ -761,6 +766,9 @@ include_directories("${OPENAIR3_DIR}/UDP")
include_directories("${OPENAIR3_DIR}/GTPV1-U") include_directories("${OPENAIR3_DIR}/GTPV1-U")
include_directories("${OPENAIR_DIR}/targets/COMMON") include_directories("${OPENAIR_DIR}/targets/COMMON")
include_directories("${OPENAIR_DIR}/targets/ARCH/COMMON") include_directories("${OPENAIR_DIR}/targets/ARCH/COMMON")
include_directories("${OPENAIR_DIR}/targets/ARCH/ADRV9371_ZC706/USERSPACE/LIB/")
include_directories("${OPENAIR_DIR}/targets/ARCH/ADRV9371_ZC706/USERSPACE/libini/")
include_directories("${OPENAIR_DIR}/targets/ARCH/ADRV9371_ZC706/DEFS/")
include_directories("${OPENAIR_DIR}/targets/ARCH/EXMIMO/USERSPACE/LIB/") include_directories("${OPENAIR_DIR}/targets/ARCH/EXMIMO/USERSPACE/LIB/")
include_directories("${OPENAIR_DIR}/targets/ARCH/EXMIMO/DEFS") include_directories("${OPENAIR_DIR}/targets/ARCH/EXMIMO/DEFS")
include_directories("${OPENAIR2_DIR}/ENB_APP") include_directories("${OPENAIR2_DIR}/ENB_APP")
...@@ -2063,6 +2071,38 @@ target_link_libraries (lte-softmodem-nos1 pthread m ${CONFIG_LIBRARIES} rt crypt ...@@ -2063,6 +2071,38 @@ target_link_libraries (lte-softmodem-nos1 pthread m ${CONFIG_LIBRARIES} rt crypt
target_link_libraries (lte-softmodem-nos1 ${LIB_LMS_LIBRARIES}) target_link_libraries (lte-softmodem-nos1 ${LIB_LMS_LIBRARIES})
target_link_libraries (lte-softmodem-nos1 ${T_LIB}) target_link_libraries (lte-softmodem-nos1 ${T_LIB})
# lte-hwlat
###################################################
add_executable(lte-hwlat
${HW_SOURCE}
${OPENAIR_TARGETS}/RT/USER/lte-hwlat.c
${OPENAIR_TARGETS}/ARCH/COMMON/common_lib.c
)
target_link_libraries (lte-hwlat
-Wl,--start-group
-Wl,--end-group )
target_link_libraries (lte-hwlat rt pthread m )
target_link_libraries (lte-hwlat ${CMAKE_DL_LIBS} )
target_link_libraries (lte-hwlat ${OPENAIR_TARGETS}/ARCH/ADRV9371_ZC706/slib/libadrv9371_zc706.so )
# lte-hwlat-test
###################################################
add_executable(lte-hwlat-test
${HW_SOURCE}
${OPENAIR1_DIR}/PHY/TOOLS/time_meas.c
${OPENAIR_TARGETS}/RT/USER/lte-hwlat2.c
${OPENAIR_TARGETS}/ARCH/COMMON/common_lib.c
)
target_link_libraries (lte-hwlat-test
-Wl,--start-group
-Wl,--end-group )
target_link_libraries (lte-hwlat-test rt pthread m )
target_link_libraries (lte-hwlat-test ${CMAKE_DL_LIBS} )
# lte-uesoftmodem is UE implementation # lte-uesoftmodem is UE implementation
####################################### #######################################
...@@ -2379,10 +2419,10 @@ if (${T_TRACER}) ...@@ -2379,10 +2419,10 @@ if (${T_TRACER})
#all "add_executable" definitions (except tests, rb_tool, updatefw) #all "add_executable" definitions (except tests, rb_tool, updatefw)
lte-softmodem lte-softmodem-nos1 oaisim oaisim_nos1 lte-softmodem lte-softmodem-nos1 oaisim oaisim_nos1
dlsim_tm4 dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim dlsim_tm4 dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim
pdcchsim pucchsim prachsim syncsim pdcchsim pucchsim prachsim syncsim lte-hwlat
#all "add_library" definitions #all "add_library" definitions
ITTI RRC_LIB S1AP_LIB S1AP_ENB X2AP_LIB ITTI RRC_LIB S1AP_LIB S1AP_ENB X2AP_LIB
oai_exmimodevif oai_usrpdevif oai_bladerfdevif oai_lmssdrdevif oai_adrv9371_zc706devif oai_exmimodevif oai_usrpdevif oai_bladerfdevif oai_lmssdrdevif
oai_eth_transpro oai_eth_transpro
FLPT_MSG ASYNC_IF FLEXRAN_AGENT HASHTABLE MSC UTIL OMG_SUMO SECU_OSA FLPT_MSG ASYNC_IF FLEXRAN_AGENT HASHTABLE MSC UTIL OMG_SUMO SECU_OSA
SECU_CN SCHED_LIB PHY L2 default_sched remote_sched RAL CN_UTILS SECU_CN SCHED_LIB PHY L2 default_sched remote_sched RAL CN_UTILS
......
cmake_targets/build_oai
View file @ 6f290e71
...@@ -51,6 +51,7 @@ REL="Rel14" ...@@ -51,6 +51,7 @@ REL="Rel14"
HW="None" HW="None"
TP="None" TP="None"
NOS1=0 NOS1=0
HW_LATENCY=0
EPC=0 EPC=0
VERBOSE_COMPILE=0 VERBOSE_COMPILE=0
CFLAGS_PROCESSOR_USER="" CFLAGS_PROCESSOR_USER=""
...@@ -104,12 +105,14 @@ Options ...@@ -104,12 +105,14 @@ Options
Specify conf_nvram_path (default \"$conf_nvram_path\") Specify conf_nvram_path (default \"$conf_nvram_path\")
--UE-gen-nvram [output path] --UE-gen-nvram [output path]
Specify gen_nvram_path (default \"$gen_nvram_path\") Specify gen_nvram_path (default \"$gen_nvram_path\")
--HWLAT
Makes test program for haw latency tests
-r | --3gpp-release -r | --3gpp-release
default is Rel14, default is Rel14,
Rel8 limits the implementation to 3GPP Release 8 version Rel8 limits the implementation to 3GPP Release 8 version
Rel10 limits the implementation to 3GPP Release 10 version Rel10 limits the implementation to 3GPP Release 10 version
-w | --hardware -w | --hardware
EXMIMO, USRP, BLADERF, ETHERNET, LMSSDR, None (Default) EXMIMO, USRP, BLADERF, ETHERNET, LMSSDR, ADRV9371_ZC706, None (Default)
Adds this RF board support (in external packages installation and in compilation) Adds this RF board support (in external packages installation and in compilation)
-t | --transport protocol -t | --transport protocol
ETHERNET , None ETHERNET , None
...@@ -234,13 +237,16 @@ function main() { ...@@ -234,13 +237,16 @@ function main() {
shift 2;; shift 2;;
-w | --hardware) -w | --hardware)
HW="$2" #"${i#*=}" HW="$2" #"${i#*=}"
# Use OAI_USRP as the key word USRP is used inside UHD driver # Use OAI_USRP as the key word USRP is used inside UHD driver
if [ "$HW" != "BLADERF" -a "$HW" != "USRP" -a "$HW" != "LMSSDR" -a "$HW" != "None" -a "$HW" != "EXMIMO" ] ; then if [ "$HW" != "BLADERF" -a "$HW" != "USRP" -a "$HW" != "LMSSDR" -a "$HW" != "None" -a "$HW" != "EXMIMO" -a "$HW" != "ADRV9371_ZC706" ] ; then
echo_fatal "Unknown HW type $HW will exit..." echo_fatal "Unknown HW type $HW will exit..."
else else
if [ "$HW" == "USRP" ] ; then if [ "$HW" == "USRP" ] ; then
HW="OAI_USRP" HW="OAI_USRP"
fi fi
if [ "$HW" == "ADRV9371_ZC706" ] ; then
HW="OAI_ADRV9371_ZC706"
fi
if [ "$HW" == "BLADERF" ] ; then if [ "$HW" == "BLADERF" ] ; then
HW="OAI_BLADERF" HW="OAI_BLADERF"
fi fi
...@@ -297,6 +303,14 @@ function main() { ...@@ -297,6 +303,14 @@ function main() {
NOS1=1 NOS1=1
echo_info "Will compile without S1 interface" echo_info "Will compile without S1 interface"
shift;; shift;;
--HWLAT)
HWLAT=1
echo_info "Will compile hw latency test program"
shift;;
--HWLAT_TEST)
HWLAT_TEST=1
echo_info "Will compile hw latency test program"
shift;;
--verbose-compile) --verbose-compile)
VERBOSE_COMPILE=1 VERBOSE_COMPILE=1
echo_info "Will compile with verbose instructions" echo_info "Will compile with verbose instructions"
...@@ -397,6 +411,12 @@ function main() { ...@@ -397,6 +411,12 @@ function main() {
fi fi
fi fi
if [ "$HWLAT" = "1" ] ; then
if [ "$HW" = "None" ] ; then
echo_info "No radio head has been selected (HW set to $HW)"
fi
fi
echo_info "RF HW set to $HW" echo_info "RF HW set to $HW"
#Now we set flags to enable deadline scheduler settings #Now we set flags to enable deadline scheduler settings
#By default: USRP: disable, #By default: USRP: disable,
...@@ -409,6 +429,8 @@ function main() { ...@@ -409,6 +429,8 @@ function main() {
DEADLINE_SCHEDULER_FLAG_USER="False" DEADLINE_SCHEDULER_FLAG_USER="False"
elif [ "$HW" = "OAI_USRP" ] ; then elif [ "$HW" = "OAI_USRP" ] ; then
DEADLINE_SCHEDULER_FLAG_USER="False" DEADLINE_SCHEDULER_FLAG_USER="False"
elif [ "$HW" = "OAI_ADRV9371_ZC706" ] ; then
DEADLINE_SCHEDULER_FLAG_USER="False"
elif [ "$HW" = "OAI_BLADERF" ] ; then elif [ "$HW" = "OAI_BLADERF" ] ; then
DEADLINE_SCHEDULER_FLAG_USER="False" DEADLINE_SCHEDULER_FLAG_USER="False"
elif [ "$HW" = "OAI_LMSSDR" ] ; then elif [ "$HW" = "OAI_LMSSDR" ] ; then
...@@ -474,6 +496,10 @@ function main() { ...@@ -474,6 +496,10 @@ function main() {
install_usrp_uhd_driver $UHD_IMAGES_DIR install_usrp_uhd_driver $UHD_IMAGES_DIR
fi fi
fi fi
if [ "$HW" == "OAI_ADRV9371_ZC706" ] ; then
echo_info "\nInstalling packages for ADRV9371_ZC706 support"
check_install_libiio_driver
fi
if [ "$HW" == "OAI_BLADERF" ] ; then if [ "$HW" == "OAI_BLADERF" ] ; then
echo_info "installing packages for BLADERF support" echo_info "installing packages for BLADERF support"
check_install_bladerf_driver check_install_bladerf_driver
...@@ -811,9 +837,65 @@ function main() { ...@@ -811,9 +837,65 @@ function main() {
libtelnetsrv.so $dbin/libtelnetsrv.so libtelnetsrv.so $dbin/libtelnetsrv.so
fi fi
# HWLAT compilation
#####################
if [ "$HWLAT" = "1" ] ; then
hwlat_exec=lte-hwlat
hwlat_build_dir=lte-hwlat
echo_info "Compiling $hwlat_exec ..."
[ "$CLEAN" = "1" ] && rm -rf $DIR/lte-hwlat/build
mkdir -p $DIR/$hwlat_build_dir/build
cmake_file=$DIR/$hwlat_build_dir/CMakeLists.txt
echo "cmake_minimum_required(VERSION 2.8)" > $cmake_file
echo "set ( CMAKE_BUILD_TYPE $CMAKE_BUILD_TYPE )" >> $cmake_file
echo "set ( RF_BOARD \"${HW}\")" >> $cmake_file
echo 'set ( PACKAGE_NAME "\"lte-hwlat\"")' >> $cmake_file
echo "set ( DEADLINE_SCHEDULER \"${DEADLINE_SCHEDULER_FLAG_USER}\" )" >>$cmake_file
echo "set ( CPU_AFFINITY \"${CPU_AFFINITY_FLAG_USER}\" )" >>$cmake_file
echo "set ( HWLAT \"${HWLAT}\" )" >>$cmake_file
echo 'include(${CMAKE_CURRENT_SOURCE_DIR}/../CMakeLists.txt)' >> $cmake_file
cd $DIR/$hwlat_build_dir/build
cmake ..
compilations \
lte-hwlat lte-hwlat \
lte-hwlat $dbin/lte-hwlat
fi
# HWLAT_TEST compilation
#####################
if [ "$HWLAT_TEST" = "1" ] ; then
hwlat_test_exec=lte-hwlat-test
hwlat_test_build_dir=lte-hwlat-test
echo_info "Compiling $hwlat_test_exec ..."
[ "$CLEAN" = "1" ] && rm -rf $DIR/lte-hwlat-test/build
mkdir -p $DIR/$hwlat_test_build_dir/build
cmake_file=$DIR/$hwlat_test_build_dir/CMakeLists.txt
echo "cmake_minimum_required(VERSION 2.8)" > $cmake_file
echo "set ( CMAKE_BUILD_TYPE $CMAKE_BUILD_TYPE )" >> $cmake_file
echo "set ( RF_BOARD \"${HW}\")" >> $cmake_file
echo 'set ( PACKAGE_NAME "\"lte-hwlat-test\"")' >> $cmake_file
echo "set ( DEADLINE_SCHEDULER \"${DEADLINE_SCHEDULER_FLAG_USER}\" )" >>$cmake_file
echo "set ( CPU_AFFINITY \"${CPU_AFFINITY_FLAG_USER}\" )" >>$cmake_file
echo "set ( HWLAT \"${HWLAT}\" )" >>$cmake_file
echo 'include(${CMAKE_CURRENT_SOURCE_DIR}/../CMakeLists.txt)' >> $cmake_file
cd $DIR/$hwlat_test_build_dir/build
cmake ..
compilations \
lte-hwlat-test lte-hwlat-test \
lte-hwlat-test $dbin/lte-hwlat-test
fi
# build RF device and transport protocol libraries # build RF device and transport protocol libraries
##################################### #####################################
if [ "$eNB" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" ] ; then if [ "$eNB" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" - o "$HWLAT" = "1" ] ; then
build_dir=$build_dir build_dir=$build_dir
...@@ -831,6 +913,11 @@ function main() { ...@@ -831,6 +913,11 @@ function main() {
ln -sf liboai_exmimodevif.so liboai_device.so ln -sf liboai_exmimodevif.so liboai_device.so
ln -sf $dbin/liboai_exmimodevif.so.$REL $dbin/liboai_device.so ln -sf $dbin/liboai_exmimodevif.so.$REL $dbin/liboai_device.so
echo_info "liboai_device.so is linked to EXMIMO device library" echo_info "liboai_device.so is linked to EXMIMO device library"
elif [ "$HW" == "OAI_ADRV9371_ZC706" ] ; then
ln -sf $OPENAIR_DIR/targets/ARCH/ADRV9371_ZC706/slib/libadrv9371_zc706.so liboai_device.so
echo_info "liboai_device.so is linked to ADRV9371_ZC706 device library"
elif [ "$HW" == "OAI_USRP" ] ; then elif [ "$HW" == "OAI_USRP" ] ; then
compilations \ compilations \
$build_dir oai_usrpdevif \ $build_dir oai_usrpdevif \
......
cmake_targets/tools/build_helper
View file @ 6f290e71
...@@ -242,6 +242,36 @@ install_protobuf_c_from_source(){ ...@@ -242,6 +242,36 @@ install_protobuf_c_from_source(){
) >& $protobuf_c_install_log ) >& $protobuf_c_install_log
} }
install_libiio_driver_from_source(){
libiio_install_log=$OPENAIR_DIR/cmake_targets/log/libiio_install_log.txt
echo_info "\nInstalling LibIIO driver from sources. The log file for LibIIO driver installation is here: $libiio_install_log "
(
cd /tmp
echo "Downloading LibIIO driver"
rm -rf /tmp/libiio
git clone https://github.com/analogdevicesinc/libiio.git
cd libiio
git checkout 2016_R2
cmake ./
make all
$SUDO make install
) >& $libiio_install_log
}
check_install_libiio_driver(){
if [[ "$OS_DISTRO" == "ubuntu" ]]; then
$SUDO apt-get install -y --allow-unauthenticated libxml2
$SUDO apt-get install -y --allow-unauthenticated libxml2-dev
$SUDO apt-get install -y --allow-unauthenticated bison
$SUDO apt-get install -y --allow-unauthenticated flex
$SUDO apt-get install -y --allow-unauthenticated libcdk5-dev
$SUDO apt-get install -y --allow-unauthenticated cmake
$SUDO apt-get install -y --allow-unauthenticated libaio-dev
$SUDO apt-get install -y --allow-unauthenticated libavahi-client-dev
install_libiio_driver_from_source
fi
}
install_usrp_uhd_driver_from_source(){ install_usrp_uhd_driver_from_source(){
uhd_install_log=$OPENAIR_DIR/cmake_targets/log/uhd_install_log.txt uhd_install_log=$OPENAIR_DIR/cmake_targets/log/uhd_install_log.txt
echo_info "\nInstalling UHD driver from sources. The log file for UHD driver installation is here: $uhd_install_log " echo_info "\nInstalling UHD driver from sources. The log file for UHD driver installation is here: $uhd_install_log "
......
oaienv
View file @ 6f290e71
...@@ -17,3 +17,6 @@ alias oait='cd $OPENAIR_TARGETS' ...@@ -17,3 +17,6 @@ alias oait='cd $OPENAIR_TARGETS'
alias oailte='cd $OPENAIR_TARGETS/RT/USER' alias oailte='cd $OPENAIR_TARGETS/RT/USER'
alias oais='cd $OPENAIR_TARGETS/SIMU/USER' alias oais='cd $OPENAIR_TARGETS/SIMU/USER'
alias oaiex='cd $OPENAIR_TARGETS/SIMU/EXAMPLES' alias oaiex='cd $OPENAIR_TARGETS/SIMU/EXAMPLES'
export IIOD_REMOTE=192.168.121.32
openair1/PHY/LTE_TRANSPORT/dci_tools.c
View file @ 6f290e71
...@@ -8118,6 +8118,9 @@ int generate_ue_ulsch_params_from_dci(void *dci_pdu, ...@@ -8118,6 +8118,9 @@ int generate_ue_ulsch_params_from_dci(void *dci_pdu,
// ulsch->n_DMRS2 = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cshift; // ulsch->n_DMRS2 = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
//printf("Format 0 DCI : ulsch (ue): AbsSubframe %d.%d nrb %d harq_pid %d round %d mcs %d\n",proc->frame_rx%1024,nr_tti_rx,ulsch->harq_processes[harq_pid]->nb_rb,
// harq_pid,ulsch->harq_processes[harq_pid]->round,ulsch->harq_processes[harq_pid]->mcs);
#ifdef UE_DEBUG_TRACE #ifdef UE_DEBUG_TRACE
LOG_D(PHY,"Format 0 DCI : ulsch (ue): AbsSubframe %d.%d\n",proc->frame_rx%1024,subframe); LOG_D(PHY,"Format 0 DCI : ulsch (ue): AbsSubframe %d.%d\n",proc->frame_rx%1024,subframe);
......
openair1/PHY/LTE_TRANSPORT/initial_sync.c
View file @ 6f290e71
...@@ -554,7 +554,7 @@ int initial_sync(PHY_VARS_UE *ue, runmode_t mode) ...@@ -554,7 +554,7 @@ int initial_sync(PHY_VARS_UE *ue, runmode_t mode)
ue->frame_parms.nb_antenna_ports_eNB); ue->frame_parms.nb_antenna_ports_eNB);
#endif #endif
#if defined(OAI_USRP) || defined(EXMIMO) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(OAI_USRP) || defined(EXMIMO) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
# if DISABLE_LOG_X # if DISABLE_LOG_X
printf("[UE %d] Frame %d Measured Carrier Frequency %.0f Hz (offset %d Hz)\n", printf("[UE %d] Frame %d Measured Carrier Frequency %.0f Hz (offset %d Hz)\n",
ue->Mod_id, ue->Mod_id,
...@@ -618,9 +618,11 @@ int initial_sync(PHY_VARS_UE *ue, runmode_t mode) ...@@ -618,9 +618,11 @@ int initial_sync(PHY_VARS_UE *ue, runmode_t mode)
#ifndef OAI_USRP #ifndef OAI_USRP
#ifndef OAI_BLADERF #ifndef OAI_BLADERF
#ifndef OAI_LMSSDR #ifndef OAI_LMSSDR
#ifndef OAI_ADRV9371_ZC706
phy_adjust_gain(ue,ue->measurements.rx_power_avg_dB[0],0); phy_adjust_gain(ue,ue->measurements.rx_power_avg_dB[0],0);
#endif #endif
#endif #endif
#endif
#endif #endif
} }
...@@ -629,9 +631,11 @@ int initial_sync(PHY_VARS_UE *ue, runmode_t mode) ...@@ -629,9 +631,11 @@ int initial_sync(PHY_VARS_UE *ue, runmode_t mode)
#ifndef OAI_USRP #ifndef OAI_USRP
#ifndef OAI_BLADERF #ifndef OAI_BLADERF
#ifndef OAI_LMSSDR #ifndef OAI_LMSSDR
#ifndef OAI_ADRV9371_ZC706
phy_adjust_gain(ue,dB_fixed(ue->measurements.rssi),0); phy_adjust_gain(ue,dB_fixed(ue->measurements.rssi),0);
#endif #endif
#endif #endif
#endif
#endif #endif
} }
......
openair1/PHY/LTE_TRANSPORT/prach.c
View file @ 6f290e71
...@@ -636,7 +636,7 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 ...@@ -636,7 +636,7 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1
int i, prach_len; int i, prach_len;
uint16_t first_nonzero_root_idx=0; uint16_t first_nonzero_root_idx=0;
#if defined(EXMIMO) || defined(OAI_USRP) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_ADRV9371_ZC706)
prach_start = (ue->rx_offset+subframe*ue->frame_parms.samples_per_tti-ue->hw_timing_advance-ue->N_TA_offset); prach_start = (ue->rx_offset+subframe*ue->frame_parms.samples_per_tti-ue->hw_timing_advance-ue->N_TA_offset);
#ifdef PRACH_DEBUG #ifdef PRACH_DEBUG
LOG_I(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id, LOG_I(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id,
...@@ -1042,7 +1042,7 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1 ...@@ -1042,7 +1042,7 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1
AssertFatal(prach_fmt<4, AssertFatal(prach_fmt<4,
"prach_fmt4 not fully implemented" ); "prach_fmt4 not fully implemented" );
#if defined(EXMIMO) || defined(OAI_USRP) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_ADRV9371_ZC706)
int j; int j;
int overflow = prach_start + prach_len - LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*ue->frame_parms.samples_per_tti; int overflow = prach_start + prach_len - LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*ue->frame_parms.samples_per_tti;
LOG_I( PHY, "prach_start=%d, overflow=%d\n", prach_start, overflow ); LOG_I( PHY, "prach_start=%d, overflow=%d\n", prach_start, overflow );
......
openair1/PHY/LTE_TRANSPORT/print_stats.c
View file @ 6f290e71
...@@ -42,7 +42,7 @@ ...@@ -42,7 +42,7 @@
#endif #endif
extern int mac_get_rrc_status(uint8_t Mod_id,uint8_t eNB_flag,uint8_t index); extern int mac_get_rrc_status(uint8_t Mod_id,uint8_t eNB_flag,uint8_t index);
#if defined(OAI_USRP) || defined(EXMIMO) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(OAI_USRP) || defined(EXMIMO) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
#include "common_lib.h" #include "common_lib.h"
extern openair0_config_t openair0_cfg[]; extern openair0_config_t openair0_cfg[];
#endif #endif
...@@ -90,10 +90,10 @@ int dump_ue_stats(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc,char* buffer, int length ...@@ -90,10 +90,10 @@ int dump_ue_stats(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc,char* buffer, int length
#ifdef EXMIMO #ifdef EXMIMO
len += sprintf(&buffer[len], "[UE PROC] RX Gain %d dB (LNA %d, vga %d dB)\n",ue->rx_total_gain_dB, openair0_cfg[0].rxg_mode[0],(int)openair0_cfg[0].rx_gain[0]); len += sprintf(&buffer[len], "[UE PROC] RX Gain %d dB (LNA %d, vga %d dB)\n",ue->rx_total_gain_dB, openair0_cfg[0].rxg_mode[0],(int)openair0_cfg[0].rx_gain[0]);
#endif #endif
#if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
len += sprintf(&buffer[len], "[UE PROC] RX Gain %d dB\n",ue->rx_total_gain_dB); len += sprintf(&buffer[len], "[UE PROC] RX Gain %d dB\n",ue->rx_total_gain_dB);
#endif #endif
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
len += sprintf(&buffer[len], "[UE_PROC] Frequency offset %d Hz, estimated carrier frequency %f Hz\n",ue->common_vars.freq_offset,openair0_cfg[0].rx_freq[0]-ue->common_vars.freq_offset); len += sprintf(&buffer[len], "[UE_PROC] Frequency offset %d Hz, estimated carrier frequency %f Hz\n",ue->common_vars.freq_offset,openair0_cfg[0].rx_freq[0]-ue->common_vars.freq_offset);
#endif #endif
len += sprintf(&buffer[len], "[UE PROC] UE mode = %s (%d)\n",mode_string[ue->UE_mode[0]],ue->UE_mode[0]); len += sprintf(&buffer[len], "[UE PROC] UE mode = %s (%d)\n",mode_string[ue->UE_mode[0]],ue->UE_mode[0]);
......
openair1/SCHED/phy_procedures_lte_ue.c
View file @ 6f290e71
...@@ -76,7 +76,7 @@ extern double cpuf; ...@@ -76,7 +76,7 @@ extern double cpuf;
void Msg1_transmitted(module_id_t module_idP,uint8_t CC_id,frame_t frameP, uint8_t eNB_id); void Msg1_transmitted(module_id_t module_idP,uint8_t CC_id,frame_t frameP, uint8_t eNB_id);
void Msg3_transmitted(module_id_t module_idP,uint8_t CC_id,frame_t frameP, uint8_t eNB_id); void Msg3_transmitted(module_id_t module_idP,uint8_t CC_id,frame_t frameP, uint8_t eNB_id);
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
extern uint32_t downlink_frequency[MAX_NUM_CCs][4]; extern uint32_t downlink_frequency[MAX_NUM_CCs][4];
#endif #endif
...@@ -158,7 +158,7 @@ void dump_dlsch_SI(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t s ...@@ -158,7 +158,7 @@ void dump_dlsch_SI(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t s
exit(-1); exit(-1);
} }
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
//unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162}; //unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162};
/* /*
unsigned int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL) unsigned int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL)
...@@ -1202,7 +1202,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt ...@@ -1202,7 +1202,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
int frame_tx = proc->frame_tx; int frame_tx = proc->frame_tx;
int ulsch_start; int ulsch_start;
int overflow=0; int overflow=0;
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
int k,l; int k,l;
int dummy_tx_buffer[frame_parms->samples_per_tti] __attribute__((aligned(16))); int dummy_tx_buffer[frame_parms->samples_per_tti] __attribute__((aligned(16)));
#endif #endif
...@@ -1213,7 +1213,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt ...@@ -1213,7 +1213,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
#endif #endif
nsymb = (frame_parms->Ncp == 0) ? 14 : 12; nsymb = (frame_parms->Ncp == 0) ? 14 : 12;
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)//this is the EXPRESS MIMO case #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)//this is the EXPRESS MIMO case
ulsch_start = (ue->rx_offset+subframe_tx*frame_parms->samples_per_tti- ulsch_start = (ue->rx_offset+subframe_tx*frame_parms->samples_per_tti-
ue->hw_timing_advance- ue->hw_timing_advance-
ue->timing_advance- ue->timing_advance-
...@@ -1231,7 +1231,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt ...@@ -1231,7 +1231,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
ulsch_start = (frame_parms->samples_per_tti*subframe_tx)-ue->N_TA_offset; //-ue->timing_advance; ulsch_start = (frame_parms->samples_per_tti*subframe_tx)-ue->N_TA_offset; //-ue->timing_advance;
#endif //else EXMIMO #endif //else EXMIMO
//#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) //#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
if (empty_subframe) if (empty_subframe)
{ {
//#if 1 //#if 1
...@@ -1279,7 +1279,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt ...@@ -1279,7 +1279,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) { for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
if (frame_parms->Ncp == 1) if (frame_parms->Ncp == 1)
PHY_ofdm_mod(&ue->common_vars.txdataF[aa][subframe_tx*nsymb*frame_parms->ofdm_symbol_size], PHY_ofdm_mod(&ue->common_vars.txdataF[aa][subframe_tx*nsymb*frame_parms->ofdm_symbol_size],
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
dummy_tx_buffer, dummy_tx_buffer,
#else #else
&ue->common_vars.txdata[aa][ulsch_start], &ue->common_vars.txdata[aa][ulsch_start],
...@@ -1290,7 +1290,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt ...@@ -1290,7 +1290,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
CYCLIC_PREFIX); CYCLIC_PREFIX);
else { else {
normal_prefix_mod(&ue->common_vars.txdataF[aa][subframe_tx*nsymb*frame_parms->ofdm_symbol_size], normal_prefix_mod(&ue->common_vars.txdataF[aa][subframe_tx*nsymb*frame_parms->ofdm_symbol_size],
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
dummy_tx_buffer, dummy_tx_buffer,
#else #else
&ue->common_vars.txdata[aa][ulsch_start], &ue->common_vars.txdata[aa][ulsch_start],
...@@ -1308,7 +1308,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt ...@@ -1308,7 +1308,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
&ue->frame_parms); &ue->frame_parms);
} }
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
apply_7_5_kHz(ue,dummy_tx_buffer,0); apply_7_5_kHz(ue,dummy_tx_buffer,0);
apply_7_5_kHz(ue,dummy_tx_buffer,1); apply_7_5_kHz(ue,dummy_tx_buffer,1);
#else #else
...@@ -1317,7 +1317,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt ...@@ -1317,7 +1317,7 @@ void ulsch_common_procedures(PHY_VARS_UE *ue, UE_rxtx_proc_t *proc, uint8_t empt
#endif #endif
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
overflow = ulsch_start - 9*frame_parms->samples_per_tti; overflow = ulsch_start - 9*frame_parms->samples_per_tti;
...@@ -1822,7 +1822,7 @@ void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB ...@@ -1822,7 +1822,7 @@ void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB
} }
ue->tx_total_RE[subframe_tx] = nb_rb*12; ue->tx_total_RE[subframe_tx] = nb_rb*12;
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
tx_amp = get_tx_amp(ue->tx_power_dBm[subframe_tx], tx_amp = get_tx_amp(ue->tx_power_dBm[subframe_tx],
ue->tx_power_max_dBm, ue->tx_power_max_dBm,
ue->frame_parms.N_RB_UL, ue->frame_parms.N_RB_UL,
...@@ -1899,7 +1899,7 @@ void ue_srs_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8 ...@@ -1899,7 +1899,7 @@ void ue_srs_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8
Po_SRS = ue->tx_power_max_dBm; Po_SRS = ue->tx_power_max_dBm;
} }
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
if (ue->mac_enabled==1) if (ue->mac_enabled==1)
{ {
tx_amp = get_tx_amp(Po_SRS, tx_amp = get_tx_amp(Po_SRS,
...@@ -2182,7 +2182,7 @@ void ue_pucch_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uin ...@@ -2182,7 +2182,7 @@ void ue_pucch_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uin
ue->tx_power_dBm[subframe_tx] = Po_PUCCH; ue->tx_power_dBm[subframe_tx] = Po_PUCCH;
ue->tx_total_RE[subframe_tx] = 12; ue->tx_total_RE[subframe_tx] = 12;
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
tx_amp = get_tx_amp(Po_PUCCH, tx_amp = get_tx_amp(Po_PUCCH,
ue->tx_power_max_dBm, ue->tx_power_max_dBm,
ue->frame_parms.N_RB_UL, ue->frame_parms.N_RB_UL,
...@@ -2277,7 +2277,7 @@ void ue_pucch_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uin ...@@ -2277,7 +2277,7 @@ void ue_pucch_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uin
ue->tx_power_dBm[subframe_tx] = Po_PUCCH; ue->tx_power_dBm[subframe_tx] = Po_PUCCH;
ue->tx_total_RE[subframe_tx] = 12; ue->tx_total_RE[subframe_tx] = 12;
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
tx_amp = get_tx_amp(Po_PUCCH, tx_amp = get_tx_amp(Po_PUCCH,
ue->tx_power_max_dBm, ue->tx_power_max_dBm,
ue->frame_parms.N_RB_UL, ue->frame_parms.N_RB_UL,
...@@ -2538,9 +2538,11 @@ void ue_measurement_procedures( ...@@ -2538,9 +2538,11 @@ void ue_measurement_procedures(
#ifndef OAI_USRP #ifndef OAI_USRP
#ifndef OAI_BLADERF #ifndef OAI_BLADERF
#ifndef OAI_LMSSDR #ifndef OAI_LMSSDR
#ifndef OAI_ADRV9371_ZC706
phy_adjust_gain (ue,dB_fixed(ue->measurements.rssi),0); phy_adjust_gain (ue,dB_fixed(ue->measurements.rssi),0);
#endif #endif
#endif #endif
#endif
#endif #endif
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GAIN_CONTROL, VCD_FUNCTION_OUT); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GAIN_CONTROL, VCD_FUNCTION_OUT);
......
openair2/RRC/LITE/rrc_UE.c
View file @ 6f290e71
...@@ -788,7 +788,7 @@ rrc_ue_establish_drb( ...@@ -788,7 +788,7 @@ rrc_ue_establish_drb(
RADIO_ACCESS_BEARER,Rlc_info_um); RADIO_ACCESS_BEARER,Rlc_info_um);
*/ */
#ifdef PDCP_USE_NETLINK #ifdef PDCP_USE_NETLINK
# if !defined(OAI_NW_DRIVER_TYPE_ETHERNET) && !defined(EXMIMO) && !defined(OAI_USRP) && !defined(OAI_BLADERF) && !defined(ETHERNET) && !defined(LINK_ENB_PDCP_TO_GTPV1U) # if !defined(OAI_NW_DRIVER_TYPE_ETHERNET) && !defined(EXMIMO) && !defined(OAI_USRP) && !defined(OAI_BLADERF) && !defined(ETHERNET) && !defined(LINK_ENB_PDCP_TO_GTPV1U) && !defined(OAI_ADRV9371_ZC706)
ip_addr_offset3 = 0; ip_addr_offset3 = 0;
ip_addr_offset4 = 1; ip_addr_offset4 = 1;
LOG_I(OIP,"[UE %d] trying to bring up the OAI interface oai%d, IP 10.0.%d.%d\n", ue_mod_idP, ip_addr_offset3+ue_mod_idP, LOG_I(OIP,"[UE %d] trying to bring up the OAI interface oai%d, IP 10.0.%d.%d\n", ue_mod_idP, ip_addr_offset3+ue_mod_idP,
......
openair2/RRC/LITE/rrc_eNB.c
View file @ 6f290e71
...@@ -5401,7 +5401,7 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete( ...@@ -5401,7 +5401,7 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete(
ctxt_pP->module_id, ctxt_pP->frame, (int)DRB_configList->list.array[i]->drb_Identity); ctxt_pP->module_id, ctxt_pP->frame, (int)DRB_configList->list.array[i]->drb_Identity);
#if defined(PDCP_USE_NETLINK) && !defined(LINK_ENB_PDCP_TO_GTPV1U) #if defined(PDCP_USE_NETLINK) && !defined(LINK_ENB_PDCP_TO_GTPV1U)
// can mean also IPV6 since ether -> ipv6 autoconf // can mean also IPV6 since ether -> ipv6 autoconf
# if !defined(OAI_NW_DRIVER_TYPE_ETHERNET) && !defined(EXMIMO) && !defined(OAI_USRP) && !defined(OAI_BLADERF) && !defined(ETHERNET) # if !defined(OAI_NW_DRIVER_TYPE_ETHERNET) && !defined(EXMIMO) && !defined(OAI_USRP) && !defined(OAI_BLADERF) && !defined(ETHERNET) && !defined(OAI_ADRV9371_ZC706)
LOG_I(OIP, "[eNB %d] trying to bring up the OAI interface oai%d\n", LOG_I(OIP, "[eNB %d] trying to bring up the OAI interface oai%d\n",
ctxt_pP->module_id, ctxt_pP->module_id,
ctxt_pP->module_id); ctxt_pP->module_id);
......
targets/ARCH/ADRV9371_ZC706/Makefile 0 → 100755
View file @ 6f290e71
# Creates shared library
CC= gcc
CFLAGS+= -DADRV9371_ZC706 -DHWLAT -O0 -g3 -Wall -fmessage-length=0 -fPIC
DROOT= ./USERSPACE
DIR= $(DROOT)/LIB
IFLAGS+= -I$(DIR)/ \
-I$(DROOT)/libini/ \
-I../COMMON/ \
-I/usr/include/
LDFLAGS+= -L/usr/lib/x86/64-linux-gnu/ \
-lm -liio -ldl -lriffa
OUTDIR= ./slib
TARGET= libadrv9371_zc706.so
SRC= $(DIR)/adrv9371_dump.c \
$(DIR)/adrv9371_helper.c \
$(DIR)/adrv9371_self_test.c \
$(DIR)/adrv9371_zc706_lib.c \
$(DIR)/adrv9371_zc706_riffa_lib.c \
$(DIR)/adrv9371_zc706_stats.c \
$(DIR)/hw_init.c \
$(DROOT)/libini/libini.c
OBJ= $(OUTDIR)/adrv9371_dump.o \
$(OUTDIR)/adrv9371_helper.o \
$(OUTDIR)/adrv9371_self_test.o \
$(OUTDIR)/adrv9371_zc706_lib.o \
$(OUTDIR)/adrv9371_zc706_riffa_lib.o \
$(OUTDIR)/adrv9371_zc706_stats.o \
$(OUTDIR)/hw_init.o \
$(OUTDIR)/libini.o
all: lib
dir:
mkdir -p $(OUTDIR)
env:
set PATH=/usr/lib/:${PATH}
obj: dir env
$(CC) -c $(CFLAGS) $(IFLAGS) $(SRC)
mv *.o $(OUTDIR)
lib: dir obj
$(CC) -shared $(OBJ) -o $(OUTDIR)/$(TARGET) $(LDFLAGS)
# exec: env
# $(CC) $(CFLAGS) $(IFLAGS) main.c $(SRC) -o lib.exe $(LDFLAGS) -lpthread
.PHONY: clean
clean:
rm -f $(OUTDIR)/*.o $(OUTDIR)/*~
rm: clean
rm -f $(OUTDIR)/$(TARGET)
rmdir $(OUTDIR)
\ No newline at end of file
targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ADRV9371-W_test.ini 0 → 100644
View file @ 6f290e71
[IIO Oscilloscope]
plugin.DMM.detached=0
plugin.Debug.detached=0
plugin.AD9371 Advanced.detached=0
plugin.AD9371.detached=0
startup_version_check=0
test=1
[IIO Oscilloscope - Capture Window1]
fru_connect = 1
test.message = Please ensure:\n • 30.72 MHz -> REF_CLK_IN (0dBm)\n • Rx1 <-> Tx1\n • Rx2 <-> Tx2
domain=fft
sample_count=400
fft_size=16384
fft_avg=8
fft_pwr_offset=0.000000
graph_type=Lines
show_grid=1
enable_auto_scale=1
x_axis_min=-67.583626
x_axis_max=67.576126
y_axis_min=-130
y_axis_max=3
show_capture_options = 1
axi-ad9371-rx-obs-hpc.expanded=1
axi-ad9371-rx-obs-hpc.active=0
axi-ad9371-rx-obs-hpc.trigger_enabled=0
axi-ad9371-rx-obs-hpc.voltage0_i.enabled=0
axi-ad9371-rx-obs-hpc.voltage0_q.enabled=0
axi-ad9371-rx-hpc.expanded=1
axi-ad9371-rx-hpc.active=1
axi-ad9371-rx-hpc.voltage0_i.enabled=1
axi-ad9371-rx-hpc.voltage0_q.enabled=1
axi-ad9371-rx-hpc.voltage1_i.enabled=0
axi-ad9371-rx-hpc.voltage1_q.enabled=0
marker_type = Single Tone Markers
marker.0 = 9525
marker.1 = 8192
marker.2 = 10859
marker.3 = 12193
marker.4 = 13526
marker.5 = 14859
capture_started=0
[DMM]
device_list = ad7291 0
device_list = ad9371-phy 0
device_list = xadc 0
running = No
# temp between 20C and 55C (in 0.25C units)
test.ad7291.in_temp0_raw.int = 80 220
# See the production testing wiki docs [1] for how these values are calculated.
# [1]: (https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/testing#voltage)
# scale = 0.610351562
# All nominal voltages +/- 2.5%
# 0 INPUT_VOLTAGE 12V - V(Drop Diode) 56/10
test.ad7291.in_voltage0_raw.int = 2710 2850
# 1 VOUT2_1V3_DIG 1
test.ad7291.in_voltage1_raw.int = 2077 2183
# 2 VDD_IF 10/10
test.ad7291.in_voltage2_raw.int = 1997 2099
# 3 VOUT3_3V3 10/10
test.ad7291.in_voltage3_raw.int = 2636 2770
# 5 VOUT4_1V8 1
test.ad7291.in_voltage5_raw.int = 2875 3023
# 7 VOUT1_1V3_ANLG 1
test.ad7291.in_voltage7_raw.int = 2077 2183
# Test AD9528 lock status - Requires 30.720 MHz reference clock!
test.ad9528-1.pll1_reference_clk_a_present.int = 1 1
test.ad9528-1.pll1_locked.int = 1 1
test.ad9528-1.pll2_locked.int = 1 1
[AD9371]
ad9371-phy.in_voltage2_rf_port_select = INTERNALCALS
ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
ad9371-phy.out_altvoltage1_TX_LO_frequency = 2500000000
ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2600000000
ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB
ad9371-phy.out_voltage1_lo_leakage_tracking_en = 1
ad9371-phy.out_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage0_gain_control_mode = automatic
ad9371-phy.in_voltage0_quadrature_tracking_en = 1
ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage1_gain_control_mode = automatic
ad9371-phy.out_altvoltage0_RX_LO_frequency = 2600000000
ad9371-phy.out_voltage0_lo_leakage_tracking_en = 1
ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB
ad9371-phy.out_voltage0_quadrature_tracking_en = 1
ad9371-phy.ensm_mode = radio_on
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 10001402
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1001265
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 10001402
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 10001402
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 40001860
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1001265
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 10001402
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 40001860
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
dds_mode_tx1 = 0
dds_mode_tx2 = 0
SYNC_RELOAD = 1
# test receiver at 1GHz to 5 GHz
# SEQ FIRST INCREMENT LAST
<SEQ> i 1000000000 5000000000 5000000000
[IIO Oscilloscope - Capture Window1]
# wait for device to settle
marker_type = Peak Markers
capture_started = 0
cycle = 1000
axi-ad9371-rx-hpc.voltage0_i.enabled=1
axi-ad9371-rx-hpc.voltage0_q.enabled=1
axi-ad9371-rx-hpc.voltage1_i.enabled=0
axi-ad9371-rx-hpc.voltage1_q.enabled=0
cycle = 1000
[AD9371]
ad9371-phy.out_altvoltage1_TX_LO_frequency = <i>
ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = {{<i>} + {100000000}}
ad9371-phy.out_altvoltage0_RX_LO_frequency = {{<i>} + {100000000}}
dds_mode_tx1 = 0
dds_mode_tx2 = 0
SYNC_RELOAD = 1
[IIO Oscilloscope - Capture Window1]
# wait for device to settle
capture_started = 1
cycle = 3000
[AD9371]
# channels should be off, so RSSI should be low
test.ad9371-phy.in_voltage0_rssi.int = 44 45
test.ad9371-phy.in_voltage1_rssi.int = 44 45
# and gain is high
test.ad9371-phy.in_voltage0_hardwaregain.double = 30.0 31.0
test.ad9371-phy.in_voltage0_hardwaregain.double = 30.0 31.0
# set Tx and Rx to be the same
ad9371-phy.out_altvoltage0_RX_LO_frequency = <i>
dds_mode_tx1 = 1
dds_mode_tx2 = 1
SYNC_RELOAD = 1
[IIO Oscilloscope - Capture Window1]
# wait for device to settle
marker_type = Single Tone Markers
cycle = 3000
[AD9371]
ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB
ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB
# channels should be on, so RSSI should be high
test.ad9371-phy.in_voltage0_rssi.int = 3 12
test.ad9371-phy.in_voltage1_rssi.int = 3 12
# and gain is low
test.ad9371-phy.in_voltage0_hardwaregain.double = 15.0 29.0
test.ad9371-phy.in_voltage0_hardwaregain.double = 15.0 29.0
[IIO Oscilloscope - Capture Window1]
cycle = 1000
capture_started = 1
cycle = 3000
save_png = ADRV9371_rx1_<i>.png
save_markers = markers.log
#look at the markers - Fundamental
test.marker.0 = -12.0 -4.0
# DC
test.marker.1 = -100.0 -60.0
# 2st Harmonic
test.marker.2 = -110.0 -75.0
# 3nd Harmonic
test.marker.3 = -110.0 -75.0
# 4th Harmonic
test.marker.4 = -110.0 -75.0
# 4th Harmonic
test.marker.5 = -110.0 -65.0
capture_started = 0
cycle = 1000
axi-ad9371-rx-hpc.voltage0_i.enabled=0
axi-ad9371-rx-hpc.voltage0_q.enabled=0
axi-ad9371-rx-hpc.voltage1_i.enabled=1
axi-ad9371-rx-hpc.voltage1_q.enabled=1
cycle = 1000
capture_started = 1
cycle = 3000
save_png = ADRV9371_rx2_<i>.png
save_markers = markers.log
#look at the markers - Fundamental
test.marker.0 = -12.0 -4.0
# DC
test.marker.1 = -100.0 -60.0
# 2st Harmonic
test.marker.2 = -110.0 -75.0
# 3nd Harmonic
test.marker.3 = -110.0 -75.0
# 4th Harmonic
test.marker.4 = -110.0 -75.0
# 4th Harmonic
test.marker.5 = -110.0 -65.0
</SEQ>
[IIO Oscilloscope - Capture Window1]
capture_started = 0
test.message = Please ensure:\n • ORX1 <-> Tx1\n • ORX22 <-> Tx2
axi-ad9371-rx-hpc.expanded=1
axi-ad9371-rx-hpc.active=0
axi-ad9371-rx-hpc.voltage0_i.enabled=0
axi-ad9371-rx-hpc.voltage0_q.enabled=0
axi-ad9371-rx-hpc.voltage1_i.enabled=0
axi-ad9371-rx-hpc.voltage1_q.enabled=0
axi-ad9371-rx-obs-hpc.expanded=1
axi-ad9371-rx-obs-hpc.active=1
axi-ad9371-rx-obs-hpc.voltage0_i.enabled=1
axi-ad9371-rx-obs-hpc.voltage0_q.enabled=1
cycle = 1000
# test observer path at 1GHz to 5 GHz
# SEQ FIRST INCREMENT LAST
<SEQ> i 1000000000 1000000000 5000000000
[AD9371]
# set Tx and Rx to be the same
ad9371-phy.out_altvoltage1_TX_LO_frequency = <i>
ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = {{<i>} + {1000000}}
ad9371-phy.out_altvoltage0_RX_LO_frequency = <i>
dds_mode_tx1 = 1
dds_mode_tx2 = 1
ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB
ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB
ad9371-phy.in_voltage2_rf_port_select = ORX1_TX_LO
ad9371-phy.in_voltage2_gain_control_mode = manual
ad9371-phy.in_voltage2_hardwaregain = 18.000000 dB
[IIO Oscilloscope - Capture Window1]
capture_started = 1
cycle = 3000
save_png = ADRV9371_ob1_<i>.png
save_markers = markers.log
#look at the markers - Fundamental
test.marker.0 = -15.0 -5.0
# DC
test.marker.1 = -100.0 -75.0
# 2st Harmonic
test.marker.2 = -110.0 -75.0
# 3nd Harmonic
test.marker.3 = -110.0 -75.0
# 4th Harmonic
test.marker.4 = -110.0 -75.0
# 4th Harmonic
test.marker.5 = -110.0 -65.0
[AD9371]
ad9371-phy.in_voltage2_rf_port_select = ORX2_TX_LO
[IIO Oscilloscope - Capture Window1]
cycle = 1000
capture_started = 1
cycle = 3000
save_png = ADRV9371_ob2_<i>.png
save_markers = markers.log
#look at the markers - Fundamental
test.marker.0 = -15.0 -4.0
# DC
test.marker.1 = -100.0 -75.0
# 2st Harmonic
test.marker.2 = -110.0 -75.0
# 3nd Harmonic
test.marker.3 = -110.0 -75.0
# 4th Harmonic
test.marker.4 = -110.0 -75.0
# 4th Harmonic
test.marker.5 = -110.0 -65.0
</SEQ>
[IIO Oscilloscope - Capture Window1]
test.message = All tests passed - Ship it
quit = 1
targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile1-osc.ini 0 → 100644
View file @ 6f290e71
[AD9371]
ad9371-phy.in_voltage2_rf_port_select = OFF
ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB
ad9371-phy.out_voltage0_quadrature_tracking_en = 1
ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB
ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage1_TX_LO_frequency = 2685000000
ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2565000000
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage0_gain_control_mode = automatic
ad9371-phy.in_voltage0_quadrature_tracking_en = 1
ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB
ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB
ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage1_gain_control_mode = automatic
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage0_RX_LO_frequency = 2565000000
ad9371-phy.calibrate_rx_qec_en = 0
ad9371-phy.calibrate_tx_lol_en = 0
ad9371-phy.calibrate_vswr_en = 0
ad9371-phy.calibrate_tx_qec_en = 0
ad9371-phy.calibrate_clgc_en = 0
ad9371-phy.ensm_mode = radio_on
ad9371-phy.calibrate_tx_lol_ext_en = 0
ad9371-phy.calibrate_dpd_en = 0
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt
dds_mode_tx1 = 1
dds_mode_tx2 = 1
dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
tx_channel_0 = 1
tx_channel_1 = 1
tx_channel_2 = 0
tx_channel_3 = 0
global_settings_show = 1
tx_show = 1
rx_show = 1
obs_show = 1
fpga_show = 1
[ADRV9371_ZC706]
debug_mode = 0
interpolation_decimation_factor = 2
targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt 0 → 100644
View file @ 6f290e71
<profile AD9371 version=0 name=Rx 20, IQrate 30.720>
<clocks>
<deviceClock_kHz=122880>
<clkPllVcoFreq_kHz=9830400>
<clkPllVcoDiv=2>
<clkPllHsDiv=4>
</clocks>
<rx>
<adcDiv=1>
<rxFirDecimation=4>
<rxDec5Decimation=5>
<enHighRejDec5=1>
<rhb1Decimation=2>
<iqRate_kHz=30720>
<rfBandwidth_Hz=20000000>
<rxBbf3dBCorner_kHz=20000>
<filter FIR gain=-6 num=72>
0
2
4
3
-4
-14
-21
-12
17
56
73
39
-53
-159
-198
-101
129
377
457
229
-274
-793
-951
-482
527
1564
1899
1011
-978
-3154
-4109
-2611
1669
7795
13807
17524
17524
13807
7795
1669
-2611
-4109
-3154
-978
1011
1899
1564
527
-482
-951
-793
-274
229
457
377
129
-101
-198
-159
-53
39
73
56
17
-12
-21
-14
-4
3
4
2
0
</filter>
<adc-profile num=16>
599
357
201
98
1280
112
1505
53
1331
21
820
40
48
40
23
191
</adc-profile>
</rx>
<obs>
<adcDiv=1>
<rxFirDecimation=2>
<rxDec5Decimation=5>
<enHighRejDec5=1>
<rhb1Decimation=2>
<iqRate_kHz=61440>
<rfBandwidth_Hz=50000000>
<rxBbf3dBCorner_kHz=25000>
<filter FIR gain=0 num=72>
0
-1
1
2
-2
-6
6
12
-13
-24
25
43
-45
-73
77
118
-124
-183
193
274
-289
-402
423
579
-607
-826
866
1187
-1244
-1759
1842
2818
-2970
-5815
4337
18436
18436
4337
-5815
-2970
2818
1842
-1759
-1244
1187
866
-826
-607
579
423
-402
-289
274
193
-183
-124
118
77
-73
-45
43
25
-24
-13
12
6
-6
-2
2
1
-1
0
</filter>
<adc-profile num=16>
596
358
201
98
1280
134
1509
64
1329
25
818
39
48
40
23
190
</adc-profile>
<lpbk-adc-profile num=16>
599
357
201
98
1280
112
1505
53
1331
21
820
40
48
40
23
191
</lpbk-adc-profile>
</obs>
<tx>
<dacDiv=2.5>
<txFirInterpolation=2>
<thb1Interpolation=2>
<thb2Interpolation=2>
<txInputHbInterpolation=1>
<iqRate_kHz=61440>
<primarySigBandwidth_Hz=20000000>
<rfBandwidth_Hz=50000000>
<txDac3dBCorner_kHz=92000>
<txBbf3dBCorner_kHz=25000>
<filter FIR gain=0 num=32>
-118
-122
242
240
-429
-499
730
900
-1154
-1615
1742
2957
-2322
-5354
3885
17211
17211
3885
-5354
-2322
2957
1742
-1615
-1154
900
730
-499
-429
240
242
-122
-118
</filter>
</tx>
</profile>
targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706.ini 0 → 100644
View file @ 6f290e71
[AD9371]
ad9371-phy.in_voltage2_rf_port_select = OFF
ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB
ad9371-phy.out_voltage0_quadrature_tracking_en = 1
ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB
ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage1_TX_LO_frequency = 2560000000
ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2680000000
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage0_gain_control_mode = manual
ad9371-phy.in_voltage0_quadrature_tracking_en = 1
ad9371-phy.in_voltage0_hardwaregain = 25.000000 dB
ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage1_hardwaregain = 25.000000 dB
ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage1_gain_control_mode = manual
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage0_RX_LO_frequency = 2680000000
ad9371-phy.calibrate_rx_qec_en = 0
ad9371-phy.calibrate_tx_lol_en = 0
ad9371-phy.calibrate_vswr_en = 0
ad9371-phy.calibrate_tx_qec_en = 0
ad9371-phy.calibrate_clgc_en = 0
ad9371-phy.ensm_mode = radio_on
ad9371-phy.calibrate_tx_lol_ext_en = 0
ad9371-phy.calibrate_dpd_en = 0
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt
dds_mode_tx1 = 1
dds_mode_tx2 = 1
dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
tx_channel_0 = 1
tx_channel_1 = 1
tx_channel_2 = 0
tx_channel_3 = 0
global_settings_show = 1
tx_show = 1
rx_show = 1
obs_show = 1
fpga_show = 1
[ADRV9371_ZC706]
# NO_DEBUG=0; DEBUG=1
debug_mode = 0
# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4
interpolation_decimation_factor = 1
# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual"
rx_gain_offset = 69
targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini 0 → 100644
View file @ 6f290e71
[AD9371]
ad9371-phy.in_voltage2_rf_port_select = OFF
ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB
ad9371-phy.out_voltage0_quadrature_tracking_en = 1
ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB
ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage1_TX_LO_frequency = 2560000000
ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2680000000
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage0_gain_control_mode = manual
ad9371-phy.in_voltage0_quadrature_tracking_en = 1
ad9371-phy.in_voltage0_hardwaregain = 15.000000 dB
ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage1_hardwaregain = 15.000000 dB
ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage1_gain_control_mode = manual
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage0_RX_LO_frequency = 2680000000
ad9371-phy.calibrate_rx_qec_en = 0
ad9371-phy.calibrate_tx_lol_en = 0
ad9371-phy.calibrate_vswr_en = 0
ad9371-phy.calibrate_tx_qec_en = 0
ad9371-phy.calibrate_clgc_en = 0
ad9371-phy.ensm_mode = radio_on
ad9371-phy.calibrate_tx_lol_ext_en = 0
ad9371-phy.calibrate_dpd_en = 0
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile20MHz.txt
dds_mode_tx1 = 1
dds_mode_tx2 = 1
dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
tx_channel_0 = 1
tx_channel_1 = 1
tx_channel_2 = 0
tx_channel_3 = 0
global_settings_show = 1
tx_show = 1
rx_show = 1
obs_show = 1
fpga_show = 1
[ADRV9371_ZC706]
# NO_DEBUG=0; DEBUG=1
debug_mode = 0
# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4
interpolation_decimation_factor = 1
# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual"
rx_gain_offset = 30
targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB25.adrv9371-zc706.ini 0 → 100644
View file @ 6f290e71
[AD9371]
ad9371-phy.in_voltage2_rf_port_select = OFF
ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB
ad9371-phy.out_voltage0_quadrature_tracking_en = 1
ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB
ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage1_TX_LO_frequency = 2535000000
ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2655000000
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage0_gain_control_mode = automatic
ad9371-phy.in_voltage0_quadrature_tracking_en = 1
ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB
ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB
ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage1_gain_control_mode = automatic
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage0_RX_LO_frequency = 2655000000
ad9371-phy.calibrate_rx_qec_en = 0
ad9371-phy.calibrate_tx_lol_en = 0
ad9371-phy.calibrate_vswr_en = 0
ad9371-phy.calibrate_tx_qec_en = 0
ad9371-phy.calibrate_clgc_en = 0
ad9371-phy.ensm_mode = radio_on
ad9371-phy.calibrate_tx_lol_ext_en = 0
ad9371-phy.calibrate_dpd_en = 0
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt
dds_mode_tx1 = 1
dds_mode_tx2 = 1
dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
tx_channel_0 = 1
tx_channel_1 = 1
tx_channel_2 = 0
tx_channel_3 = 0
global_settings_show = 1
tx_show = 1
rx_show = 1
obs_show = 1
fpga_show = 1
[ADRV9371_ZC706]
debug_mode = 0
interpolation_decimation_factor = 4
targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB50.adrv9371-zc706.ini 0 → 100644
View file @ 6f290e71
[AD9371]
ad9371-phy.in_voltage2_rf_port_select = OFF
ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage0_hardwaregain = -10.000000 dB
ad9371-phy.out_voltage0_quadrature_tracking_en = 1
ad9371-phy.out_voltage1_hardwaregain = -10.000000 dB
ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage1_TX_LO_frequency = 2535000000
ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2655000000
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage0_gain_control_mode = automatic
ad9371-phy.in_voltage0_quadrature_tracking_en = 1
ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB
ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB
ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage1_gain_control_mode = automatic
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage0_RX_LO_frequency = 2655000000
ad9371-phy.calibrate_rx_qec_en = 0
ad9371-phy.calibrate_tx_lol_en = 0
ad9371-phy.calibrate_vswr_en = 0
ad9371-phy.calibrate_tx_qec_en = 0
ad9371-phy.calibrate_clgc_en = 0
ad9371-phy.ensm_mode = radio_on
ad9371-phy.calibrate_tx_lol_ext_en = 0
ad9371-phy.calibrate_dpd_en = 0
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profile_rx30_Tx60_syr.txt
dds_mode_tx1 = 1
dds_mode_tx2 = 1
dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
tx_channel_0 = 1
tx_channel_1 = 1
tx_channel_2 = 0
tx_channel_3 = 0
global_settings_show = 1
tx_show = 1
rx_show = 1
obs_show = 1
fpga_show = 1
[ADRV9371_ZC706]
debug_mode = 0
interpolation_decimation_factor = 2
targets/ARCH/ADRV9371_ZC706/readme.txt 0 → 100644
View file @ 6f290e71
Common command line:
--------------------
cd /openairinterface5g/
source oaienv
HWLAT application:
------------------
./cmake_targets/build_oai -c -C -w ADRV9371_ZC706 --HWLAT
./cmake_targets/lte-hwlat/build/lte-hwlat
LTE-SOFTMODEM application:
--------------------------
./cmake_targets/build_oai -c --eNB --UE --noS1 -w ADRV9371_ZC706
sudo su
source oaienv
source ./targets/bin/init_nas_nos1 UE
./cmake_targets/lte_noS1_build_oai/build/lte-softmodem-nos1 -U -C 2680000000 -r100 --ue-scan-carrier --ue-txgain 0 --ue-rxgain 5 -S -A 6 --ue-max-power -25 --phy-test -g 7 --rf-config-file ./targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.adrv9371-zc706_HWgain15dB.ini
targets/ARCH/COMMON/common_lib.c
View file @ 6f290e71
...@@ -60,6 +60,12 @@ case USRP_X300_DEV: ...@@ -60,6 +60,12 @@ case USRP_X300_DEV:
case NONE_DEV: case NONE_DEV:
printf("[%s] has not loaded a HW device.\n",((device->host_type == RAU_HOST) ? "RAU": "RRU")); printf("[%s] has not loaded a HW device.\n",((device->host_type == RAU_HOST) ? "RAU": "RRU"));
break; break;
case ADRV9371_ZC706_DEV:
printf("[%s] has loaded ADRV9371_ZC706 device.\n",((device->host_type == RAU_HOST) ? "RAU": "RRU"));
break;
case UEDv2_DEV:
printf("[%s] has loaded UEDv2 device.\n",((device->host_type == RAU_HOST) ? "RAU": "RRU"));
break;
default: default:
printf("[%s] invalid HW device.\n",((device->host_type == RAU_HOST) ? "RAU": "RRU")); printf("[%s] invalid HW device.\n",((device->host_type == RAU_HOST) ? "RAU": "RRU"));
return -1; return -1;
......
targets/ARCH/COMMON/common_lib.h
View file @ 6f290e71
...@@ -97,6 +97,10 @@ typedef enum { ...@@ -97,6 +97,10 @@ typedef enum {
LMSSDR_DEV, LMSSDR_DEV,
/*!\brief device is NONE*/ /*!\brief device is NONE*/
NONE_DEV, NONE_DEV,
/*!\brief device is ADRV9371_ZC706 */
ADRV9371_ZC706_DEV,
/*!\brief device is UEDv2 */
UEDv2_DEV,
MAX_RF_DEV_TYPE MAX_RF_DEV_TYPE
} dev_type_t; } dev_type_t;
...@@ -216,6 +220,14 @@ typedef struct { ...@@ -216,6 +220,14 @@ typedef struct {
unsigned int sf_write_delay; // write delay in replay mode unsigned int sf_write_delay; // write delay in replay mode
unsigned int eth_mtu; // ethernet MTU unsigned int eth_mtu; // ethernet MTU
#endif #endif
//! number of samples per tti
unsigned int samples_per_tti;
//! the sample rate for receive.
double rx_sample_rate;
//! the sample rate for transmit.
double tx_sample_rate;
} openair0_config_t; } openair0_config_t;
/*! \brief RF mapping */ /*! \brief RF mapping */
......
targets/COMMON/openairinterface5g_limits.h
View file @ 6f290e71
#ifndef OPENAIRINTERFACE5G_LIMITS_H_ #ifndef OPENAIRINTERFACE5G_LIMITS_H_
#define OPENAIRINTERFACE5G_LIMITS_H_ #define OPENAIRINTERFACE5G_LIMITS_H_
#if defined(CBMIMO1) || defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_LMSSDR) #if defined(CBMIMO1) || defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
# define NUMBER_OF_eNB_MAX 1 # define NUMBER_OF_eNB_MAX 1
# define NUMBER_OF_RU_MAX 2 # define NUMBER_OF_RU_MAX 2
# define NUMBER_OF_UE_MAX 16 # define NUMBER_OF_UE_MAX 16
......
targets/RT/USER/lte-hwlat.c 0 → 100755
View file @ 6f290e71
This diff is collapsed.
targets/RT/USER/lte-hwlat2.c 0 → 100644
View file @ 6f290e71
This diff is collapsed.
targets/SIMU/USER/oaisim_functions.c
View file @ 6f290e71
...@@ -1704,7 +1704,7 @@ void update_otg_eNB(module_id_t enb_module_idP, unsigned int ctime) ...@@ -1704,7 +1704,7 @@ void update_otg_eNB(module_id_t enb_module_idP, unsigned int ctime)
} }
#else #else
#if 0 // defined(EXMIMO) || defined(OAI_USRP) #if 0 // defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_ADRV9371_ZC706)
if (otg_enabled==1) { if (otg_enabled==1) {
ctime = frame * 100; ctime = frame * 100;
......
targets/build_oai.bash
View file @ 6f290e71
...@@ -344,6 +344,10 @@ build_enb(){ ...@@ -344,6 +344,10 @@ build_enb(){
SOFTMODEM_DIRECTIVES="$SOFTMODEM_DIRECTIVES USRP=1 " SOFTMODEM_DIRECTIVES="$SOFTMODEM_DIRECTIVES USRP=1 "
fi fi
if [ $HW = "ADRV9371_ZC706" ]; then
SOFTMODEM_DIRECTIVES="$SOFTMODEM_DIRECTIVES ADRV9371_ZC706=1 "
fi
if [ $HW = "EXMIMO" ]; then if [ $HW = "EXMIMO" ]; then
SOFTMODEM_DIRECTIVES="$SOFTMODEM_DIRECTIVES EXMIMO=1 " SOFTMODEM_DIRECTIVES="$SOFTMODEM_DIRECTIVES EXMIMO=1 "
fi fi
......
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