Commit 73244eae authored by francescomani's avatar francescomani

storing TBS and R at MAC instead of PHY

parent a62bdf36
......@@ -101,27 +101,23 @@ static bool nr_ue_postDecode(PHY_VARS_NR_UE *phy_vars_ue,
LOG_D(PHY, "DLSCH %d in error\n", rdata->dlsch_id);
}
uint32_t tbs;
if (dlsch->dlsch_config.targetCodeRate > 0)
tbs = dlsch->dlsch_config.TBS;
else
tbs = harq_process->tb_size;
// if all segments are done
if (last) {
kpiStructure.nb_total++;
kpiStructure.blockSize = tbs;
kpiStructure.blockSize = dlsch->dlsch_config.TBS;
kpiStructure.dl_mcs = dlsch->dlsch_config.mcs;
kpiStructure.nofRBs = dlsch->dlsch_config.number_rbs;
if (*num_seg_ok == harq_process->C) {
if (harq_process->C > 1) {
int A = dlsch->dlsch_config.TBS;
/* check global CRC */
// we have regrouped the transport block, so it is "1" segment
if (!check_crc(b, lenWithCrc(1, tbs), crcType(1, tbs))) {
if (!check_crc(b, lenWithCrc(1, A), crcType(1, A))) {
harq_process->ack = 0;
dlsch->last_iteration_cnt = dlsch->max_ldpc_iterations + 1;
LOG_E(PHY, " Frame %d.%d LDPC global CRC fails, but individual LDPC CRC succeeded. %d segs\n", proc->frame_rx, proc->nr_slot_rx, harq_process->C);
LOG_E(PHY, " Frame %d.%d LDPC global CRC fails, but individual LDPC CRC succeeded. %d segs\n",
proc->frame_rx, proc->nr_slot_rx, harq_process->C);
LOG_D(PHY, "DLSCH received nok \n");
return true; //stop
}
......@@ -343,13 +339,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
}
*/
nb_rb = dlsch->dlsch_config.number_rbs;
uint32_t A;
if (dlsch->dlsch_config.targetCodeRate > 0) {
A = dlsch->dlsch_config.TBS;
harq_process->tb_size = A;
}
else
A = harq_process->tb_size;
uint32_t A = dlsch->dlsch_config.TBS;
ret = dlsch->max_ldpc_iterations + 1;
dlsch->last_iteration_cnt = ret;
harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, dmrs_length, dlsch->dlsch_config.qamModOrder,dlsch->Nl);
......
......@@ -91,8 +91,6 @@ typedef struct {
uint8_t BG;
// LDPC lifting size
uint32_t Z;
// TB size
uint32_t tb_size;
} NR_UL_UE_HARQ_t;
typedef struct {
......@@ -115,6 +113,8 @@ typedef struct {
uint8_t Ndi;
/// DLSCH status flag indicating
SCH_status_t status;
/// Transport block size
uint32_t TBS;
/// Pointers to transport block segments
uint8_t **c;
/// soft bits for each received segment ("d"-sequence)(for definition see 36-212 V8.6 2009-03, p.15)
......@@ -140,8 +140,6 @@ typedef struct {
/// Used for computing LDPC decoder R
int llrLen;
decode_abort_t abort_decode;
// TB size
uint32_t tb_size;
} NR_DL_UE_HARQ_t;
typedef struct {
......
......@@ -131,16 +131,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
NR_UL_UE_HARQ_t *harq_process_ul_ue = &UE->ul_harq_processes[harq_pid];
const nfapi_nr_ue_pusch_pdu_t *pusch_pdu = &ulsch_ue->pusch_pdu;
uint32_t tb_size;
// MCS > limit -> retransmission
// Take TB size from previois transmission
if (pusch_pdu->target_code_rate == 0)
tb_size = harq_process_ul_ue->tb_size;
else {
tb_size = pusch_pdu->pusch_data.tb_size;
harq_process_ul_ue->tb_size = tb_size;
}
uint32_t tb_size = pusch_pdu->pusch_data.tb_size;
int start_symbol = pusch_pdu->start_symbol_index;
uint16_t ul_dmrs_symb_pos = pusch_pdu->ul_dmrs_symb_pos;
uint8_t number_of_symbols = pusch_pdu->nr_of_symbols;
......
......@@ -132,7 +132,7 @@ void nr_fill_rx_indication(fapi_nr_rx_indication_t *rx_ind,
dl_harq0 = &ue->dl_harq_processes[0][dlsch0->dlsch_config.harq_process_nbr];
trace_NRpdu(DIRECTION_DOWNLINK,
b,
dl_harq0->tb_size / 8,
dlsch0->dlsch_config.TBS / 8,
t,
dlsch0->rnti,
proc->frame_rx,
......@@ -148,7 +148,7 @@ void nr_fill_rx_indication(fapi_nr_rx_indication_t *rx_ind,
rx_ind->rx_indication_body[n_pdus - 1].pdsch_pdu.harq_pid = dlsch0->dlsch_config.harq_process_nbr;
rx_ind->rx_indication_body[n_pdus - 1].pdsch_pdu.ack_nack = dl_harq0->ack;
rx_ind->rx_indication_body[n_pdus - 1].pdsch_pdu.pdu = b;
rx_ind->rx_indication_body[n_pdus - 1].pdsch_pdu.pdu_length = dl_harq0->tb_size / 8;
rx_ind->rx_indication_body[n_pdus - 1].pdsch_pdu.pdu_length = dlsch0->dlsch_config.TBS / 8;
}
if(dlsch1) {
AssertFatal(1==0,"Second codeword currently not supported\n");
......@@ -764,7 +764,7 @@ bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
nr_fill_dl_indication(&dl_indication, NULL, &rx_ind, proc, ue, NULL);
nr_fill_rx_indication(&rx_ind, ind_type, ue, &dlsch[0], NULL, number_pdus, proc, NULL, p_b);
LOG_D(PHY, "DL PDU length in bits: %d, in bytes: %d \n", dl_harq0->tb_size, dl_harq0->tb_size / 8);
LOG_D(PHY, "DL PDU length in bits: %d, in bytes: %d \n", dlsch[0].dlsch_config.TBS, dlsch[0].dlsch_config.TBS / 8);
stop_meas(&ue->dlsch_decoding_stats);
if (cpumeas(CPUMEAS_GETSTATE)) {
......@@ -814,7 +814,7 @@ bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
LOG_D(PHY, "AbsSubframe %d.%d --> ldpc Decoding for CW1 %5.3f\n",
frame_rx%1024, nr_slot_rx,(ue->dlsch_decoding_stats.p_time)/(cpuf*1000.0));
}
LOG_D(PHY, "harq_pid: %d, TBS expected dlsch1: %d \n", harq_pid, dl_harq1->tb_size);
LOG_D(PHY, "harq_pid: %d, TBS expected dlsch1: %d \n", harq_pid, dlsch[1].dlsch_config.TBS);
}
// send to mac
......
......@@ -340,8 +340,15 @@ typedef struct {
int N_CCE;
int j_dai;
int8_t delta_pucch;
uint32_t R;
uint32_t TBS;
} NR_UE_HARQ_STATUS_t;
typedef struct {
uint32_t R;
uint32_t TBS;
} NR_UL_HARQ_INFO_t;
typedef struct {
uint8_t freq_hopping;
uint8_t mcs;
......@@ -525,6 +532,7 @@ typedef struct {
// Defined for abstracted mode
nr_downlink_indication_t dl_info;
NR_UE_HARQ_STATUS_t dl_harq_info[NR_MAX_HARQ_PROCESSES];
NR_UL_HARQ_INFO_t ul_harq_info[NR_MAX_HARQ_PROCESSES];
nr_emulated_l1_t nr_ue_emul_l1;
......
......@@ -712,12 +712,12 @@ static int nr_ue_process_dci_dl_10(module_id_t module_id,
return -1;
}
NR_UE_HARQ_STATUS_t *current_harq = &mac->dl_harq_info[dci->harq_pid];
int R = nr_get_code_rate_dl(dlsch_pdu->mcs, dlsch_pdu->mcs_table);
dlsch_pdu->targetCodeRate = R;
int nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
int nb_re_dmrs = ((dlsch_pdu->dmrsConfigType == NFAPI_NR_DMRS_TYPE1) ? 6 : 4) * dlsch_pdu->n_dmrs_cdm_groups;
if (R > 0)
if (R > 0) {
dlsch_pdu->targetCodeRate = R;
int nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
int nb_re_dmrs = ((dlsch_pdu->dmrsConfigType == NFAPI_NR_DMRS_TYPE1) ? 6 : 4) * dlsch_pdu->n_dmrs_cdm_groups;
dlsch_pdu->TBS = nr_compute_tbs(dlsch_pdu->qamModOrder,
R,
dlsch_pdu->number_rbs,
......@@ -726,6 +726,14 @@ static int nr_ue_process_dci_dl_10(module_id_t module_id,
nb_rb_oh,
0,
1);
// storing for possible retransmissions
current_harq->R = dlsch_pdu->targetCodeRate;
current_harq->TBS = dlsch_pdu->TBS;
}
else {
dlsch_pdu->targetCodeRate = current_harq->R;
dlsch_pdu->TBS = current_harq->TBS;
}
int bw_tbslbrm;
if (current_DL_BWP->initial_BWPSize > 0)
......@@ -1126,8 +1134,6 @@ static int nr_ue_process_dci_dl_11(module_id_t module_id,
/* TODO same calculation for MCS table as done in UL */
dlsch_pdu->mcs_table = (pdsch_Config->mcs_Table) ? (*pdsch_Config->mcs_Table + 1) : 0;
dlsch_pdu->qamModOrder = nr_get_Qm_dl(dlsch_pdu->mcs, dlsch_pdu->mcs_table);
int R = nr_get_code_rate_dl(dlsch_pdu->mcs, dlsch_pdu->mcs_table);
dlsch_pdu->targetCodeRate = R;
if (dlsch_pdu->qamModOrder == 0) {
LOG_W(MAC, "Invalid code rate or Mod order, likely due to unexpected DL DCI.\n");
return -1;
......@@ -1139,7 +1145,11 @@ static int nr_ue_process_dci_dl_11(module_id_t module_id,
}
int nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
int nb_re_dmrs = ((dmrs_type == NULL) ? 6 : 4) * dlsch_pdu->n_dmrs_cdm_groups;
if (R > 0)
NR_UE_HARQ_STATUS_t *current_harq = &mac->dl_harq_info[dci->harq_pid];
int R = nr_get_code_rate_dl(dlsch_pdu->mcs, dlsch_pdu->mcs_table);
if (R > 0) {
dlsch_pdu->targetCodeRate = R;
dlsch_pdu->TBS = nr_compute_tbs(dlsch_pdu->qamModOrder,
R,
dlsch_pdu->number_rbs,
......@@ -1148,6 +1158,14 @@ static int nr_ue_process_dci_dl_11(module_id_t module_id,
nb_rb_oh,
0,
Nl);
// storing for possible retransmissions
current_harq->R = dlsch_pdu->targetCodeRate;
current_harq->TBS = dlsch_pdu->TBS;
}
else {
dlsch_pdu->targetCodeRate = current_harq->R;
dlsch_pdu->TBS = current_harq->TBS;
}
// TBS_LBRM according to section 5.4.2.1 of 38.212
long *maxMIMO_Layers = current_DL_BWP->pdsch_servingcellconfig->ext1->maxMIMO_Layers;
......@@ -1247,8 +1265,8 @@ void set_harq_status(NR_UE_MAC_INST_t *mac,
int n_CCE,
int N_CCE,
frame_t frame,
int slot) {
int slot)
{
NR_UE_HARQ_STATUS_t *current_harq = &mac->dl_harq_info[harq_id];
current_harq->active = true;
......
......@@ -424,14 +424,8 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
uint16_t rnti,
const nr_dci_format_t dci_format)
{
int f_alloc;
int mask;
uint8_t nb_dmrs_re_per_rb;
uint16_t l_prime_mask = 0;
uint16_t number_dmrs_symbols = 0;
int N_PRB_oh = 0;
uint16_t l_prime_mask = 0;
int N_PRB_oh = 0;
int rnti_type = get_rnti_type(mac, rnti);
NR_UE_UL_BWP_t *current_UL_BWP = &mac->current_UL_BWP;
......@@ -467,12 +461,13 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
//// Resource assignment from RAR
// Frequency domain allocation according to 8.3 of TS 38.213
int mask;
if (ibwp_size < 180)
mask = (1 << ((int) ceil(log2((ibwp_size*(ibwp_size+1))>>1)))) - 1;
else
mask = (1 << (28 - (int)(ceil(log2((ibwp_size*(ibwp_size+1))>>1))))) - 1;
f_alloc = rar_grant->Msg3_f_alloc & mask;
int f_alloc = rar_grant->Msg3_f_alloc & mask;
if (nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu, NULL, ibwp_size, 0, f_alloc) < 0)
return -1;
......@@ -702,19 +697,15 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
}
}
LOG_D(NR_MAC, "In %s: received UL grant (rb_start %d, rb_size %d, start_symbol_index %d, nr_of_symbols %d) for RNTI type %s \n",
__FUNCTION__,
pusch_config_pdu->rb_start,
pusch_config_pdu->rb_size,
pusch_config_pdu->start_symbol_index,
pusch_config_pdu->nr_of_symbols,
rnti_types[rnti_type]);
LOG_D(NR_MAC, "Received UL grant (rb_start %d, rb_size %d, start_symbol_index %d, nr_of_symbols %d) for RNTI type %s \n",
pusch_config_pdu->rb_start,
pusch_config_pdu->rb_size,
pusch_config_pdu->start_symbol_index,
pusch_config_pdu->nr_of_symbols,
rnti_types[rnti_type]);
pusch_config_pdu->ul_dmrs_symb_pos = l_prime_mask;
uint16_t R = nr_get_code_rate_ul(pusch_config_pdu->mcs_index, pusch_config_pdu->mcs_table);
pusch_config_pdu->target_code_rate = R;
pusch_config_pdu->qam_mod_order = nr_get_Qm_ul(pusch_config_pdu->mcs_index, pusch_config_pdu->mcs_table);
if (pusch_config_pdu->qam_mod_order == 0) {
LOG_W(NR_MAC, "Invalid Mod order, likely due to unexpected UL DCI. Ignoring DCI! \n");
return -1;
......@@ -722,25 +713,35 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
int start_symbol = pusch_config_pdu->start_symbol_index;
int number_of_symbols = pusch_config_pdu->nr_of_symbols;
int number_dmrs_symbols = 0;
for (int i = start_symbol; i < start_symbol + number_of_symbols; i++) {
if((pusch_config_pdu->ul_dmrs_symb_pos >> i) & 0x01)
number_dmrs_symbols += 1;
}
nb_dmrs_re_per_rb = ((pusch_config_pdu->dmrs_config_type == pusch_dmrs_type1) ? 6:4)*pusch_config_pdu->num_dmrs_cdm_grps_no_data;
int nb_dmrs_re_per_rb = ((pusch_config_pdu->dmrs_config_type == pusch_dmrs_type1) ? 6 : 4) * pusch_config_pdu->num_dmrs_cdm_grps_no_data;
// Compute TBS
if (R > 0)
uint16_t R = nr_get_code_rate_ul(pusch_config_pdu->mcs_index, pusch_config_pdu->mcs_table);
int pid = pusch_config_pdu->pusch_data.harq_process_id;
if (R > 0) {
pusch_config_pdu->target_code_rate = R;
pusch_config_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_config_pdu->qam_mod_order,
R,
pusch_config_pdu->rb_size,
pusch_config_pdu->nr_of_symbols,
nb_dmrs_re_per_rb*number_dmrs_symbols,
nb_dmrs_re_per_rb * number_dmrs_symbols,
N_PRB_oh,
0, // TBR to verify tb scaling
pusch_config_pdu->nrOfLayers)>>3;
pusch_config_pdu->nrOfLayers) >> 3;
mac->ul_harq_info[pid].TBS = pusch_config_pdu->pusch_data.tb_size;
mac->ul_harq_info[pid].R = R;
}
else {
pusch_config_pdu->target_code_rate = mac->ul_harq_info[pid].R;
pusch_config_pdu->pusch_data.tb_size = mac->ul_harq_info[pid].TBS;
}
return 0;
}
void configure_srs_pdu(NR_UE_MAC_INST_t *mac,
......
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