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Commit 7e83f75d authored by Ejaz Ahmed's avatar Ejaz Ahmed
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Added functionality to take PSFCH Preconfigurations from conf file

parent c4706eda
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Showing with 141 additions and 504 deletions
executables/nr-ue.c
View file @ 7e83f75d
......@@ -624,12 +624,7 @@ void processSlotTX(void *arg) {
if (proc->tx_slot_type == NR_SIDELINK_SLOT && UE->sl_mode == 2) {
// wait for rx slots to send indication (if any) that SLSCH decoding is finished
// for(int i=0; i < rxtxD->tx_wait_for_slsch; i++) {
// LOG_D(NR_PHY, "tx frame:slot %d:%d, rxtxD->tx_wait_for_slsch: %d pullNotifiedFIFO\n", proc->frame_tx, proc->nr_slot_tx, rxtxD->tx_wait_for_slsch);
// notifiedFIFO_elt_t *res = pullNotifiedFIFO(UE->tx_resume_ind_fifo[proc->nr_slot_tx]);
// delNotifiedFIFO_elt(res);
// }
// trigger L2 to run ue_scheduler thru IF module
if(UE->if_inst != NULL && UE->if_inst->sl_indication != NULL) {
start_meas(&UE->ue_ul_indication_stats);
......@@ -646,7 +641,7 @@ void processSlotTX(void *arg) {
sl_indication.phy_data = &phy_data;
sl_indication.slot_type = SIDELINK_SLOT_TYPE_TX;
LOG_D(NR_PHY,"Sending SL indication RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
LOG_D(NR_PHY,"Sending SL indication RX %d.%d TX %d.%d\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx);
UE->if_inst->sl_indication(&sl_indication);
stop_meas(&UE->ue_ul_indication_stats);
......@@ -724,24 +719,10 @@ nr_phy_data_t UE_dl_preprocessing(PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc)
if(UE->if_inst != NULL && UE->if_inst->sl_indication != NULL) {
nr_sidelink_indication_t sl_indication;
nr_fill_sl_indication(&sl_indication, NULL, NULL, proc, UE, &phy_data);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
UE->if_inst->sl_indication(&sl_indication);
}
uint64_t a=rdtsc_oai();
psbch_pscch_pssch_processing(UE, proc, &phy_data);
// if (phy_data.sl_active) {
// LOG_I(NR_PHY, "%s sl_active: %d\n", __FUNCTION__, phy_data.sl_active);
// // indicate to tx thread to wait for DLSCH decoding
// sl_nr_phy_config_request_t *sl_cfg = NULL;
// sl_cfg = &UE->SL_UE_PHY_PARAMS.sl_config;
// uint8_t psfch_period = sl_cfg->psfch_period;
// uint8_t psfch_min_time_gap = sl_cfg->time_gap;
// int delta_slots = (proc->nr_slot_rx + psfch_min_time_gap) % psfch_period ? psfch_period - (proc->nr_slot_rx + psfch_min_time_gap) % psfch_period: 0;
// uint8_t feedback_slot = proc->nr_slot_rx + psfch_min_time_gap + delta_slots;
// feedback_slot %= NR_MAX_SLOTS_PER_FRAME;
// UE->tx_wait_for_slsch[feedback_slot]++;
// phy_data.sl_active = false;
// }
LOG_D(PHY, "In %s: slot %d:%d, time %llu\n", __FUNCTION__, proc->frame_rx, proc->nr_slot_rx, (rdtsc_oai()-a)/3500);
}
} else {
......@@ -936,7 +917,6 @@ void *UE_thread(void *arg)
int num_ind_fifo = nb_slot_frame;
for(int i=0; i < num_ind_fifo; i++) {
UE->tx_wait_for_dlsch[num_ind_fifo] = 0;
// UE->tx_wait_for_slsch[num_ind_fifo] = 0;
UE->tx_resume_ind_fifo[i] = malloc(sizeof(*UE->tx_resume_ind_fifo[i]));
initNotifiedFIFO(UE->tx_resume_ind_fifo[i]);
}
......@@ -1105,13 +1085,8 @@ void *UE_thread(void *arg)
curMsgTx->writeBlockSize = writeBlockSize;
curMsgTx->proc.timestamp_tx = writeTimestamp;
curMsgTx->UE = UE;
// if (UE->tx_wait_for_slsch[curMsgTx->proc.nr_slot_tx] > 0) {
// curMsgTx->tx_wait_for_slsch = UE->tx_wait_for_slsch[curMsgTx->proc.nr_slot_tx];
// UE->tx_wait_for_slsch[curMsgTx->proc.nr_slot_tx] = 0;
// } else {
curMsgTx->tx_wait_for_dlsch = UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx];
UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx] = 0;
//}
pushTpool(&(get_nrUE_params()->Tpool), newElt);
// RX slot processing. We launch and forget.
......
nfapi/open-nFAPI/nfapi/public_inc/sidelink_nr_ue_interface.h
View file @ 7e83f75d
......@@ -30,7 +30,6 @@ typedef enum sl_nr_rx_config_type_enum {
SL_NR_CONFIG_TYPE_RX_PSCCH,
SL_NR_CONFIG_TYPE_RX_PSSCH_SCI,
SL_NR_CONFIG_TYPE_RX_PSSCH_SLSCH,
SL_NR_CONFIG_TYPE_RX_PSFCH,
SL_NR_CONFIG_TYPE_RX_MAXIMUM
} sl_nr_rx_config_type_enum_t;
......@@ -293,42 +292,20 @@ typedef struct sl_nr_tx_config_psbch_pdu {
typedef struct sl_nr_tx_config_psfch_pdu {
// These fields map directly to the same fields in nfapi_nr_ul_config_pucch_pdu
uint8_t freq_hop_flag;
uint8_t group_hop_flag;
uint8_t sequence_hop_flag;
uint16_t second_hop_prb;
uint8_t nr_of_symbols;
uint8_t start_symbol_index;
uint8_t hopping_id;
uint8_t prb;
uint16_t initial_cyclic_shift;
uint8_t mcs;
uint8_t bit_len_harq;
uint8_t psfch_payload;
} sl_nr_tx_config_psfch_pdu_t;
typedef struct sl_nr_rx_config_psfch_pdu {
// These fields map directly to the same fields in nfapi_nr_ul_config_pucch_pdu
uint8_t freq_hop_flag;
uint8_t group_hop_flag;
uint8_t sequence_hop_flag;
uint16_t second_hop_prb;
uint8_t nr_of_symbols;
uint8_t start_symbol_index;
uint8_t hopping_id;
uint8_t prb;
uint16_t initial_cyclic_shift;
uint8_t mcs;
uint8_t psfch_payload;
} sl_nr_rx_config_psfch_pdu_t;
// MAC commands PHY to perform an action on TX RESOURCE POOL or TX PSBCH using this TX CONFIG
typedef struct {
sl_nr_tx_config_type_enum_t pdu_type; // indicates the type of TX config request
union {
sl_nr_tx_config_psbch_pdu_t tx_psbch_config_pdu;
sl_nr_tx_config_pscch_pssch_pdu_t tx_pscch_pssch_config_pdu;
sl_nr_tx_config_psfch_pdu_t tx_psfch_config_pdu;
};
} sl_nr_tx_config_request_pdu_t;
......@@ -407,7 +384,6 @@ typedef struct
} sl_nr_carrier_config_t;
typedef struct {
// Mask indicating which of the below configs are changed
// Bit0 - carrier_config, Bit1 - syncsource cfg
......@@ -423,10 +399,6 @@ typedef struct {
sl_nr_bwp_config_t sl_bwp_config;
uint32_t sl_DMRS_ScrambleId;
// PSFCH related configuration to find feedback slot
uint8_t time_gap;
uint8_t psfch_period;
} sl_nr_phy_config_request_t;
......
openair1/PHY/NR_TRANSPORT/nr_uci_tools_common.c
View file @ 7e83f75d
......@@ -31,7 +31,6 @@
*/
#include "nr_dci.h"
# include "executables/softmodem-common.h"
void nr_group_sequence_hopping (pucch_GroupHopping_t PUCCH_GroupHopping,
uint32_t n_id,
......@@ -64,11 +63,7 @@ void nr_group_sequence_hopping (pucch_GroupHopping_t PUCCH_GroupHopping,
uint8_t f_ss=0,f_gh=0;
*u=0;
*v=0;
uint32_t c_init = 0;
if (get_softmodem_params()->sl_mode) {
*u = n_id % 30;
return;
}
uint32_t c_init = 0;
uint32_t x1,s; // TS 38.211 Subclause 5.2.1
int l = 32, minShift = ((2*nr_slot_tx+n_hop)<<3);
int tmpShift =0;
......@@ -140,14 +135,12 @@ double nr_cyclic_shift_hopping(uint32_t n_id,
* - lprime: lprime is the index of the OFDM symbol in the slot that corresponds to the first OFDM symbol of the PUCCH transmission in the slot given by [5, TS 38.213]
*/
// alpha_init initialized to 2*PI/12=0.5235987756
uint8_t is_sidelink = get_softmodem_params()->sl_mode ? 1 : 0;
double alpha = 0.5235987756;
uint32_t c_init = n_id; // we initialize c_init again to calculate n_cs
uint32_t x1,s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1
uint8_t n_cs=0;
int l = is_sidelink ? 0 : 32;
int minShift = (14*8*nr_slot_tx) + 8*(lnormal+lprime);
int l = 32, minShift = (14*8*nr_slot_tx )+ 8*(lnormal+lprime);
int tmpShift =0;
#ifdef DEBUG_NR_PUCCH_TX
printf("\t\t [nr_cyclic_shift_hopping] calculating alpha (cyclic shift) using c_init=%u -> \n",c_init);
......
openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c
View file @ 7e83f75d
......@@ -2260,7 +2260,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB,
pssch_pdu->sci2_len,
sci2_re);
// send SCI indication with SCI2 payload and get SLSCH information if CRC is OK
LOG_I(NR_PHY,"SCI indication (crc %x)\n",crc);
LOG_D(NR_PHY,"SCI indication (crc %x)\n",crc);
if (crc==0) ue->SL_UE_PHY_PARAMS.pssch.rx_sci2_ok++;
else ue->SL_UE_PHY_PARAMS.pssch.rx_sci2_errors++;
sl_nr_sci_indication_t sci_ind={0};
......@@ -2277,7 +2277,6 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB,
memcpy(sci_ind.sci_pdu[sci_ind.number_of_SCIs].sci_payloadBits,&sci_estimation,8);
sci_ind.number_of_SCIs++;
nr_sidelink_indication_t sl_indication;
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
nr_fill_sl_indication(&sl_indication, NULL, &sci_ind, proc, ue, phy_data);
ue->if_inst->sl_indication(&sl_indication);
LOG_D(NR_PHY,"Returning from SCI2 SL indication\n");
......
openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync_sl.c
View file @ 7e83f75d
......@@ -575,7 +575,7 @@ int sl_nr_slss_search(PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc, int num_frame
LOG_D(PHY,"Sidelink SLSS SEARCH PSBCH RX OK. Send SL-SSB TO MAC\n");
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
if (UE->if_inst && UE->if_inst->sl_indication)
UE->if_inst->sl_indication(&sl_indication);
......
openair1/PHY/NR_UE_TRANSPORT/nr_psfch_tx.c
View file @ 7e83f75d
......@@ -59,8 +59,6 @@ void nr_generate_psfch0(const PHY_VARS_NR_UE *ue,
pucch_pdu.prb_start = psfch_pdu->prb;
pucch_pdu.initial_cyclic_shift = psfch_pdu->initial_cyclic_shift;
pucch_pdu.mcs = psfch_pdu->mcs;
pucch_pdu.nr_of_symbols = psfch_pdu->nr_of_symbols;
pucch_pdu.payload = psfch_pdu->psfch_payload;
pucch_pdu.n_bit = psfch_pdu->bit_len_harq;
nr_generate_pucch0(ue,txdataF,frame_parms,amp,nr_slot_tx,&pucch_pdu);
}
nr_generate_pucch0(ue,txdataF,frame_parms,amp,nr_slot_tx,&pucch_pdu);
}
openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c
View file @ 7e83f75d
......@@ -40,7 +40,6 @@
#include <openair1/PHY/CODING/nrSmallBlock/nr_small_block_defs.h>
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
# include "executables/softmodem-common.h"
#include "T.h"
//#define NR_UNIT_TEST 1
......
openair1/PHY/defs_nr_UE.h
View file @ 7e83f75d
......@@ -222,7 +222,6 @@ typedef struct {
} NR_UE_PUCCH;
typedef struct {
int max_nb_pucch;
/// \brief Holds the transmit data in time domain.
/// For IFFT_FPGA this points to the same memory as PHY_vars->tx_vars[a].TX_DMA_BUFFER.
/// - first index: tx antenna [0..nb_antennas_tx[
......@@ -654,7 +653,6 @@ typedef struct PHY_VARS_NR_UE_s {
notifiedFIFO_t phy_config_ind;
notifiedFIFO_t *tx_resume_ind_fifo[NR_MAX_SLOTS_PER_FRAME];
int tx_wait_for_dlsch[NR_MAX_SLOTS_PER_FRAME];
// int tx_wait_for_slsch[NR_MAX_SLOTS_PER_FRAME];
//Sidelink parameters
sl_nr_sidelink_mode_t sl_mode;
......@@ -705,14 +703,12 @@ typedef struct nr_phy_data_tx_s {
typedef struct nr_phy_data_s {
NR_UE_PDCCH_CONFIG phy_pdcch_config;
NR_UE_DLSCH_t dlsch[2];
bool sl_active;
//Sidelink Rx action decided by MAC
sl_nr_rx_config_type_enum_t sl_rx_action;
sl_nr_rx_config_pscch_pdu_t nr_sl_pscch_pdu;
sl_nr_rx_config_pssch_sci_pdu_t nr_sl_pssch_sci_pdu;
sl_nr_rx_config_pssch_pdu_t nr_sl_pssch_pdu;
sl_nr_rx_config_psfch_pdu_t nr_sl_psfch_pdu;
} nr_phy_data_t;
/* this structure is used to pass both UE phy vars and
* proc to the function UE_thread_rxn_txnp4
......@@ -724,7 +720,6 @@ typedef struct nr_rxtx_thread_data_s {
notifiedFIFO_t txFifo;
nr_phy_data_t phy_data;
int tx_wait_for_dlsch;
// int tx_wait_for_slsch;
} nr_rxtx_thread_data_t;
typedef struct LDPCDecode_ue_s {
......
openair1/PHY/defs_nr_sl_UE.h
View file @ 7e83f75d
......@@ -183,12 +183,6 @@ typedef struct SL_NR_UE_PSBCH {
} SL_NR_UE_PSBCH_t;
typedef struct SL_NR_UE_PSFCH {
// STATS - transmissions of PSFCH by the UE
uint16_t num_psfch_tx;
} SL_NR_UE_PSFCH_t;
typedef struct sl_nr_ue_phy_params {
SL_NR_UE_INIT_PARAMS_t init_params;
......@@ -204,9 +198,6 @@ typedef struct sl_nr_ue_phy_params {
// sidelink phy parameters used for pssch reception/txn
SL_NR_UE_PSSCH_t pssch;
// sidelink phy parameters used for psfch reception/txn
SL_NR_UE_PSFCH_t psfch;
//Configuration parameters from MAC
sl_nr_phy_config_request_t sl_config;
......
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
View file @ 7e83f75d
......@@ -759,11 +759,6 @@ int8_t sl_handle_scheduled_response(nr_scheduled_response_t *scheduled_response)
phy_data_tx->nr_sl_pssch_pscch_pdu.mcs,
phy_data_tx->nr_sl_pssch_pscch_pdu.tbslbrm);
break;
case SL_NR_CONFIG_TYPE_TX_PSFCH:
LOG_I(NR_PHY, "Recvd CONFIG_TYPE_TX_PSFCH\n");
phy_data_tx->sl_tx_action = SL_NR_CONFIG_TYPE_TX_PSFCH;
phy_data_tx->nr_sl_psfch_pdu = sl_tx_config->tx_config_list[0].tx_psfch_config_pdu;
break;
default:
AssertFatal(0,"Incorrect sl_tx config req pdutype \n");
break;
......
openair1/SCHED_NR_UE/phy_frame_config_nr_ue.c
View file @ 7e83f75d
......@@ -150,7 +150,7 @@ int sl_nr_ue_slot_select(sl_nr_phy_config_request_t *cfg,
ul_sym++;
}
}
LOG_D(NR_MAC, "frame:slot %d:%d num of ul_sym %d, NR_NUMBER_OF_SYMBOLS_PER_SLOT %d\n", nr_frame, nr_slot, ul_sym, NR_NUMBER_OF_SYMBOLS_PER_SLOT);
if(ul_sym == NR_NUMBER_OF_SYMBOLS_PER_SLOT) {
slot_type = NR_SIDELINK_SLOT;
} else if (ul_sym){
......
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
View file @ 7e83f75d
......@@ -494,7 +494,6 @@ int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue,
sci_ind.number_of_SCIs = dci_cnt;
// fill sl_indication message
nr_fill_sl_indication(&sl_indication, NULL, &sci_ind, proc, ue, phy_data);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
// send to mac
ue->if_inst->sl_indication(&sl_indication);
}
......@@ -658,7 +657,6 @@ void send_slot_ind(notifiedFIFO_t *nf, int slot) {
notifiedFIFO_elt_t *newElt = newNotifiedFIFO_elt(sizeof(int), 0, NULL, NULL);
int *msgData = (int *) NotifiedFifoData(newElt);
*msgData = slot;
LOG_I(PHY, "Pushed slot %d in notified fifo\n", slot);
pushNotifiedFIFO(nf, newElt);
}
}
......
openair1/SCHED_NR_UE/phy_procedures_nr_ue_sl.c
View file @ 7e83f75d
......@@ -92,6 +92,7 @@ void nr_fill_sl_rx_indication(sl_nr_rx_indication_t *rx_ind,
rx_slsch_pdu->pdu_length = slsch_status->rdata->ulsch_harq->TBS;
rx_slsch_pdu->harq_pid = slsch_status->rdata->harq_pid;
rx_slsch_pdu->ack_nack = (slsch_status->rxok==true) ? 1 : 0;
if (slsch_status->rxok==true) ue->SL_UE_PHY_PARAMS.pssch.rx_ok++;
else ue->SL_UE_PHY_PARAMS.pssch.rx_errors[0]++;
}
......@@ -218,18 +219,6 @@ int nr_slsch_procedures(PHY_VARS_NR_UE *ue, int frame_rx, int slot_rx, int SLSCH
int nbDecode =
nr_ulsch_decoding(NULL, ue, SLSCH_id, ue->pssch_vars[SLSCH_id].llr, fp, &pusch_pdu, frame_rx, slot_rx, harq_pid, G,proc,phy_data);
// sl_nr_phy_config_request_t *sl_cfg = NULL;
// sl_cfg = &ue->SL_UE_PHY_PARAMS.sl_config;
// uint8_t psfch_period = sl_cfg->psfch_period;
// uint8_t psfch_min_time_gap = sl_cfg->time_gap;
// int delta_slots = (slot_rx + psfch_min_time_gap) % psfch_period ? psfch_period - (slot_rx + psfch_min_time_gap) % psfch_period: 0;
// uint8_t feedback_slot = slot_rx + psfch_min_time_gap + delta_slots;
// feedback_slot %= NR_MAX_SLOTS_PER_FRAME;
// phy_data->sl_active = true;
// send_slot_ind(ue->tx_resume_ind_fifo[feedback_slot], slot_rx);
// LOG_D(NR_PHY, "%s Sent slot indication: slot_rx %d feedback_slot %d, sl_active %d\n", __FUNCTION__, slot_rx, feedback_slot, phy_data->sl_active);
// LOG_I(NR_MAC, "harq pid: %d Sent slot indication psfch_period %d, slot_rx %d, delta_slots %d, feedback_slot %d, time_gap %d\n", harq_pid, psfch_period, slot_rx, delta_slots, feedback_slot, psfch_min_time_gap);
return nbDecode;
}
......@@ -300,12 +289,8 @@ void nr_postDecode_slsch(PHY_VARS_NR_UE *UE, notifiedFIFO_elt_t *req,UE_nr_rxtx_
// dumpsig=1;
}
slsch->last_iteration_cnt = rdata->decodeIterations;
// FIXME: There may be need to add condition for PSFCH
sl_rx_indication.sfn = proc->frame_rx;
sl_rx_indication.slot = proc->nr_slot_rx;
nr_fill_sl_rx_indication(&sl_rx_indication,SL_NR_RX_PDU_TYPE_SLSCH,UE,1,proc,(void*)&slsch_status,0);
nr_fill_sl_indication(&sl_indication,&sl_rx_indication,NULL,proc,UE,phy_data);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
if (UE->if_inst && UE->if_inst->sl_indication)
UE->if_inst->sl_indication(&sl_indication);
/*
......@@ -396,7 +381,7 @@ static int nr_ue_psbch_procedures(PHY_VARS_NR_UE *ue,
nr_fill_sl_indication(&sl_indication, &rx_ind, NULL, proc, ue, phy_data);
nr_fill_sl_rx_indication(&rx_ind, SL_NR_RX_PDU_TYPE_SSB, ue, number_pdus, proc, (void *)result, rx_slss_id);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
if (ue->if_inst && ue->if_inst->sl_indication)
ue->if_inst->sl_indication(&sl_indication);
......@@ -451,10 +436,6 @@ void psbch_pscch_pssch_processing(PHY_VARS_NR_UE *ue,
sl_phy_params->pssch.rx_errors[1],
sl_phy_params->pssch.rx_errors[2],
sl_phy_params->pssch.rx_errors[3]);
LOG_I(NR_PHY, "%s[UE%d] %d:%d PSFCH Stats: TX %d, RX \n",KGRN,
ue->Mod_id, frame_rx, nr_slot_rx,
sl_phy_params->psfch.num_psfch_tx
);
LOG_I(NR_PHY,"============================================\n");
}
......@@ -737,18 +718,10 @@ int phy_procedures_nrUE_SL_TX(PHY_VARS_NR_UE *ue,
tx_action = 1;
}
else if (phy_data->sl_tx_action == SL_NR_CONFIG_TYPE_TX_PSFCH) {
LOG_I(NR_PHY,"Generating PSFCH ( )\n");
nr_generate_psfch0(ue,
txdataF,
fp,
AMP,
slot_tx,
&phy_data->nr_sl_psfch_pdu);
sl_phy_params->psfch.num_psfch_tx ++;
tx_action = 1;
LOG_D(NR_PHY, "Sending SL data frame %d slot %d\n", frame_tx, slot_tx);
LOG_I(NR_PHY,"Generating PSFCH ( )\n");
}
if (tx_action) {
LOG_D(PHY, "Sending SL data \n");
nr_ue_pusch_common_procedures(ue,
proc->nr_slot_tx,
fp,
......
openair1/SCHED_NR_UE/pucch_uci_ue_nr.c
View file @ 7e83f75d
......@@ -230,7 +230,7 @@ void pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, n
tx_amp = AMP;
LOG_I(PHY,"Generation of PUCCH format %d at frame.slot %d.%d\n",pucch_pdu->format_type,proc->frame_tx,nr_slot_tx);
LOG_D(PHY,"Generation of PUCCH format %d at frame.slot %d.%d\n",pucch_pdu->format_type,proc->frame_tx,nr_slot_tx);
switch(pucch_pdu->format_type) {
case 0:
......
openair2/LAYER2/NR_MAC_UE/config_ue_sl.c
View file @ 7e83f75d
......@@ -457,13 +457,6 @@ int nr_rrc_mac_config_req_sl_preconfig(module_id_t module_id,
nr_sl_phy_config_t *sl_phy_cfg = &sl_mac->sl_phy_config;
sl_phy_cfg->Mod_id = module_id;
sl_phy_cfg->CC_id = 0;
const uint8_t psfch_periods[] = {0,1,2,4};
const uint8_t time_gaps[] = {2, 3};
NR_SL_PSFCH_Config_r16_t *psfch_config = mac->sl_tx_res_pool->sl_PSFCH_Config_r16->choice.setup;
uint8_t psfch_period_index = *psfch_config->sl_PSFCH_Period_r16;
uint8_t psfch_time_gap_indx = *psfch_config->sl_MinTimeGapPSFCH_r16;
sl_phy_cfg->sl_config_req.psfch_period = psfch_periods[psfch_period_index];
sl_phy_cfg->sl_config_req.time_gap = time_gaps[psfch_time_gap_indx];
sl_prepare_phy_config(module_id, &sl_phy_cfg->sl_config_req,
freqcfg, sync_source, sl_OffsetDFN, sl_mac->sl_TDD_config);
......
openair2/LAYER2/NR_MAC_UE/mac_defs.h
View file @ 7e83f75d
......@@ -449,12 +449,9 @@ typedef struct NR_sched_pssch {
typedef struct {
bool is_waiting;
bool is_active;
uint8_t ndi;
uint8_t round;
uint16_t feedback_slot;
uint16_t feedback_frame;
int8_t sl_harq_pid;
/// sched_pusch keeps information on MCS etc used for the initial transmission
NR_sched_pssch_t sched_pssch;
......@@ -603,7 +600,6 @@ typedef struct {
NR_SSB_meas_t ssb_measurements;
dci_pdu_rel15_t def_dci_pdu_rel15[NR_MAX_SLOTS_PER_FRAME][8];
sl_nr_tx_config_psfch_pdu_t *sl_tx_config_psfch_pdu[NR_MAX_HARQ_PROCESSES];
// Defined for abstracted mode
nr_downlink_indication_t dl_info;
......
openair2/LAYER2/NR_MAC_UE/mac_proto.h
View file @ 7e83f75d
......@@ -40,13 +40,6 @@
#define NR_DL_MAX_DAI (4) /* TS 38.213 table 9.1.3-1 Value of counter DAI for DCI format 1_0 and 1_1 */
#define NR_DL_MAX_NB_CW (2) /* number of downlink code word */
// 38.213 Table 16.3-1 set of cyclic shift pairs
static const int16_t table_16_3_1[4][6] = {
{0},
{0, 3},
{0, 2, 4},
{0, 1, 2, 3, 4, 5}
};
/**\brief initialize the field in nr_mac instance
\param module_id module id */
void nr_ue_init_mac(module_id_t module_idP);
......@@ -448,8 +441,6 @@ int nr_rrc_mac_config_req_sl_preconfig(module_id_t module_id,
uint8_t sync_source,
int srcid);
uint8_t count_PSFCH_PRBs_bits(uint8_t* buf, size_t size);
void nr_rrc_mac_transmit_slss_req(module_id_t module_id,
uint8_t *sl_mib_payload,
uint16_t tx_slss_id,
......@@ -499,11 +490,6 @@ bool nr_schedule_slsch(NR_UE_MAC_INST_t *mac, int frameP, int slotP, nr_sci_pdu_
nr_sci_format_t format2,
uint16_t *slsch_pdu_length);
void config_psfch_pdu_rx(NR_UE_MAC_INST_t *mac,
sl_nr_rx_config_psfch_pdu_t *nr_sl_psfch_pdu,
const NR_SL_BWP_Generic_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool);
void config_pscch_pdu_rx(sl_nr_rx_config_pscch_pdu_t *nr_sl_pscch_pdu,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool);
......
openair2/LAYER2/NR_MAC_UE/nr_slsch_scheduler.c
View file @ 7e83f75d
......@@ -64,13 +64,13 @@ bool nr_schedule_slsch(NR_UE_MAC_INST_t *mac, int frameP,int slotP, nr_sci_pdu_t
sci_pdu->beta_offset_indicator = 0;
// Fill SCI2A
sci2_pdu->harq_pid = slotP%16; // slotP FIXIT - The value should only be 0-15 which can be in 4-bits
sci2_pdu->harq_pid = 0;
sci2_pdu->ndi = (1-sci2_pdu->ndi)&1;
sci2_pdu->rv_index=0;
sci2_pdu->source_id=0x12;
sci2_pdu->dest_id=0xabcd;
sci2_pdu->harq_feedback=0;
sci2_pdu->cast_type=1;
sci2_pdu->harq_feedback=1;
sci2_pdu->cast_type=0;
if (format2==NR_SL_SCI_FORMAT_2C || format2==NR_SL_SCI_FORMAT_2A)
sci2_pdu->csi_req=1;
if (format2==NR_SL_SCI_FORMAT_2B)
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures_sl.c
View file @ 7e83f75d
......@@ -24,10 +24,6 @@
#define SL_DEBUG
static const int sequence_cyclic_shift_harq_ack_or_ack_or_only_nack[2]
/* Sequence cyclic shift */ = { 0, 6 };
uint8_t sl_process_TDD_UL_DL_config_patterns(NR_TDD_UL_DL_ConfigCommon_t *TDD_UL_DL_Config,
uint8_t mu,
double *slot_period_P,
......@@ -492,12 +488,6 @@ uint8_t sl_determine_sci_1a_len(uint16_t *num_subchannels,
const uint8_t psfch_periods[] = {0,1,2,4};
psfch_period = (psfch_config->sl_PSFCH_Period_r16)
? psfch_periods[*psfch_config->sl_PSFCH_Period_r16] : 0;
LOG_D(NR_MAC, "sl_PSFCH_Period_r16: %ld\n", *psfch_config->sl_PSFCH_Period_r16);
LOG_D(NR_MAC, "sl_PSFCH_RB_Set_r16: %02X\n", *psfch_config->sl_PSFCH_RB_Set_r16->buf);
LOG_D(NR_MAC, "sl_NumMuxCS_Pair_r16: %ld\n", *psfch_config->sl_NumMuxCS_Pair_r16);
LOG_D(NR_MAC, "sl_MinTimeGapPSFCH_r16: %ld\n", *psfch_config->sl_MinTimeGapPSFCH_r16);
LOG_D(NR_MAC, "sl_PSFCH_HopID_r16: %ld\n", *psfch_config->sl_PSFCH_HopID_r16);
LOG_D(NR_MAC, "sl_PSFCH_CandidateResourceType_r16: %ld\n", *psfch_config->sl_PSFCH_CandidateResourceType_r16);
}
if ((psfch_period == 2) || (psfch_period == 4)) {
......@@ -585,49 +575,6 @@ uint32_t sl_determine_num_sidelink_slots(uint8_t mod_id, uint16_t *N_SSB_16frame
return N_SL_SLOTS;
}
uint8_t count_PSFCH_PRBs_bits(uint8_t* buf, size_t size) {
uint8_t count = 0;
uint8_t byte;
for (size_t i = 0; i < size; i++) {
byte = buf[i];
while(byte) {
count += byte & 1;
byte >>= 1;
}
}
return count;
}
static uint16_t compute_m0(int module_idP) {
NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP);
if (!mac->sl_tx_res_pool->sl_PSFCH_Config_r16 &&
mac->sl_tx_res_pool->sl_PSFCH_Config_r16->present != NR_SetupRelease_SL_PSFCH_Config_r16_PR_setup)
return;
NR_SL_PSFCH_Config_r16_t *sl_psfch_config = mac->sl_tx_res_pool->sl_PSFCH_Config_r16->choice.setup;
const int sl_num_muxcs_pair[4] = {1, 2, 3, 6};
uint8_t sci2_src_id = mac->sci_pdu_rx.source_id;
LOG_D(NR_MAC, "source id %d, module_idP %d\n", sci2_src_id, module_idP);
uint8_t *rb_buf = sl_psfch_config->sl_PSFCH_RB_Set_r16->buf;
size_t size = sl_psfch_config->sl_PSFCH_RB_Set_r16->size / sizeof(rb_buf[0]);
LOG_D(NR_MAC, "size %d, buff_size %d, element size %d\n", size, sl_psfch_config->sl_PSFCH_RB_Set_r16->size, sizeof(rb_buf[0]));
uint8_t m_psfch_prb_set = count_PSFCH_PRBs_bits(rb_buf, size);
long sl_numsubchannel = *mac->sl_tx_res_pool->sl_NumSubchannel_r16;
const uint8_t psfch_periods[] = {0,1,2,4};
long psfch_period = (sl_psfch_config->sl_PSFCH_Period_r16)
? psfch_periods[*sl_psfch_config->sl_PSFCH_Period_r16] : 0;
long n_psfch_cs = *sl_psfch_config->sl_NumMuxCS_Pair_r16;
double m_psfch_subch_slot = m_psfch_prb_set / sl_numsubchannel * psfch_period;
long n_psfch_type = *sl_psfch_config->sl_PSFCH_CandidateResourceType_r16 ? sl_numsubchannel : 1;
uint16_t r_psfch_prb_cs = n_psfch_type * m_psfch_subch_slot * sl_num_muxcs_pair[n_psfch_cs];
uint8_t psfch_rsc_idx = (sci2_src_id + module_idP) / r_psfch_prb_cs;
LOG_D(NR_MAC, "size %d, m_psfch_prb_set %d, sl_numsubchannel %d, sl_psfch_period %d, n_psfch_cs %d\n", size, m_psfch_prb_set, sl_numsubchannel, psfch_period, n_psfch_cs);
LOG_D(NR_MAC, "m_psfch_subch_slot %f, n_psfch_type %d, r_psfch_prb_cs %d, psfch_rsc_idx %d\n", m_psfch_subch_slot, n_psfch_type, r_psfch_prb_cs, psfch_rsc_idx);
return table_16_3_1[n_psfch_cs][psfch_rsc_idx];
}
void nr_ue_process_mac_sl_pdu(int module_idP,
sl_nr_rx_indication_t *rx_ind,
int pdu_id)
......@@ -636,64 +583,12 @@ void nr_ue_process_mac_sl_pdu(int module_idP,
uint8_t *pduP = (rx_ind->rx_indication_body + pdu_id)->rx_slsch_pdu.pdu;
int32_t pdu_len = (int32_t)(rx_ind->rx_indication_body + pdu_id)->rx_slsch_pdu.pdu_length;
uint8_t done = 0;
NR_UE_sl_harq_t *harq_proc;
NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP);
int frame = rx_ind->sfn;
int slot = rx_ind->slot;
uint16_t sched_frame, sched_slot;
if (!pduP){
return;
}
if (mac->sci_pdu_rx.harq_feedback) {
NR_SL_PSFCH_Config_r16_t *sl_psfch_config = mac->sl_tx_res_pool->sl_PSFCH_Config_r16->choice.setup;
const uint8_t time_gap[] = {2, 3};
uint8_t psfch_min_time_gap = time_gap[*sl_psfch_config->sl_MinTimeGapPSFCH_r16];
uint8_t harq_pid = (rx_ind->rx_indication_body + pdu_id)->rx_slsch_pdu.harq_pid;
mac->sl_info.list[0] = calloc(1, sizeof(NR_SL_UE_info_t));
harq_proc = &mac->sl_info.list[0]->UE_sched_ctrl.sl_harq_processes[harq_pid];
const uint8_t psfch_periods[] = {0,1,2,4};
long psfch_period = (sl_psfch_config->sl_PSFCH_Period_r16)
? psfch_periods[*sl_psfch_config->sl_PSFCH_Period_r16] : 0;
int delta_slots = (slot + psfch_min_time_gap) % psfch_period ? psfch_period - (slot + psfch_min_time_gap) % psfch_period: 0;
sched_slot = slot + psfch_min_time_gap + delta_slots;
sched_frame = frame;
if (sched_slot >= NR_MAX_SLOTS_PER_FRAME) {
sched_slot %= NR_MAX_SLOTS_PER_FRAME;
sched_frame = (sched_frame + 1) % 1024;
}
harq_proc->feedback_slot = sched_slot;
harq_proc->feedback_frame = sched_frame;
harq_proc->is_active = true;
LOG_D(NR_MAC, "harq pid: %p:%d:%d psfch_period %d, delta_slots %d, feedback frame:slot %d:%d, frame:slot %d:%d, time_gap %d, harq feedback %d\n", harq_proc, harq_pid, mac->sl_info.list[0]->UE_sched_ctrl.sl_harq_processes[harq_pid].is_active, psfch_period, delta_slots, harq_proc->feedback_frame, harq_proc->feedback_slot, frame, slot, psfch_min_time_gap, mac->sci_pdu_rx.harq_feedback);
uint8_t ack_nack = (rx_ind->rx_indication_body + pdu_id)->rx_slsch_pdu.ack_nack;
mac->sl_tx_config_psfch_pdu[harq_pid] = calloc(1, sizeof(sl_nr_tx_config_psfch_pdu_t));
uint16_t m0 = compute_m0(module_idP);
mac->sl_tx_config_psfch_pdu[harq_pid]->initial_cyclic_shift = m0;
if (mac->sci1_pdu.second_stage_sci_format == 2 ||
mac->sci_pdu_rx.cast_type == 1 ||
mac->sci_pdu_rx.cast_type == 2) {
mac->sl_tx_config_psfch_pdu[harq_pid]->mcs = sequence_cyclic_shift_harq_ack_or_ack_or_only_nack[ack_nack];
} else if (mac->sci1_pdu.second_stage_sci_format == 1 ||
(mac->sci1_pdu.second_stage_sci_format == 1 && mac->sci_pdu_rx.cast_type == 3)) {
mac->sl_tx_config_psfch_pdu[harq_pid]->mcs = sequence_cyclic_shift_harq_ack_or_ack_or_only_nack[0];
}
const uint8_t values[] = {7, 8, 9, 10, 11, 12, 13, 14};
NR_SL_BWP_Generic_r16_t *sl_bwp = mac->sl_bwp->sl_BWP_Generic_r16;
uint8_t sl_num_symbols = *sl_bwp->sl_LengthSymbols_r16 ?
values[*sl_bwp->sl_LengthSymbols_r16] : 0;
mac->sl_tx_config_psfch_pdu[harq_pid]->start_symbol_index = *sl_bwp->sl_StartSymbol_r16 + sl_num_symbols - 2; // start_symbol_index has been used as lprime and lprime should be computed as lprime = start symbol + sl_LengthSymbols_r16 - 2
mac->sl_tx_config_psfch_pdu[harq_pid]->hopping_id = *mac->sl_bwp->sl_BWP_PoolConfigCommon_r16->sl_TxPoolSelectedNormal_r16->list.array[0]->sl_ResourcePool_r16->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_HopID_r16;
mac->sl_tx_config_psfch_pdu[harq_pid]->prb = 1;
mac->sl_tx_config_psfch_pdu[harq_pid]->psfch_payload = 1;
mac->sl_tx_config_psfch_pdu[harq_pid]->bit_len_harq = 1;
LOG_I(NR_MAC,"Filled psfch pdu\n");
}
if ((rx_ind->rx_indication_body + pdu_id)->rx_slsch_pdu.ack_nack == 0)
return;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
View file @ 7e83f75d
......@@ -3266,7 +3266,7 @@ bool nr_ue_sl_pssch_scheduler(NR_UE_MAC_INST_t *mac,
if ((slot % 10) != 6) return false;
*/
LOG_I(NR_MAC,"[UE%d] SL-PSSCH SCHEDULER: Frame:SLOT %d:%d, slot_type:%d\n",
LOG_D(NR_MAC,"[UE%d] SL-PSSCH SCHEDULER: Frame:SLOT %d:%d, slot_type:%d\n",
sl_ind->module_id, frame, slot,sl_ind->slot_type);
uint16_t slsch_pdu_length_max;
......@@ -3293,7 +3293,6 @@ bool nr_ue_sl_pssch_scheduler(NR_UE_MAC_INST_t *mac,
NR_SL_SCI_FORMAT_2A);
int buflen = tx_config->tx_config_list[0].tx_pscch_pssch_config_pdu.tb_size;
LOG_I(NR_MAC, "\n", tx_config->tx_config_list[0].tx_pscch_pssch_config_pdu.sci2_payload);
NR_UE_MAC_CE_INFO mac_ce_info = {0};
NR_UE_MAC_CE_INFO *mac_ce_p=&mac_ce_info;
......@@ -3386,22 +3385,7 @@ bool nr_ue_sl_pssch_scheduler(NR_UE_MAC_INST_t *mac,
}
return true;
}
void nr_ue_sl_psfch_rx_scheduler(NR_UE_MAC_INST_t *mac,
nr_sidelink_indication_t *sl_ind,
const NR_SL_BWP_Generic_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool,
sl_nr_rx_config_request_t *rx_config,
uint8_t *config_type) {
*config_type = SL_NR_CONFIG_TYPE_RX_PSFCH;
rx_config->number_pdus = 1;
rx_config->sfn = sl_ind->frame_rx;
rx_config->slot = sl_ind->slot_rx;
rx_config->sl_rx_config_list[0].pdu_type = *config_type;
config_psfch_pdu_rx(mac, &rx_config->sl_rx_config_list[0].rx_pscch_config_pdu,
sl_bwp,
sl_res_pool);
LOG_D(NR_MAC, "[UE%d] TTI-%d:%d RX PSFCH REQ \n", sl_ind->module_id,sl_ind->frame_rx, sl_ind->slot_rx);
}
void nr_ue_sl_pscch_rx_scheduler(nr_sidelink_indication_t *sl_ind,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool,
......@@ -3537,13 +3521,13 @@ void nr_ue_sidelink_scheduler(nr_sidelink_indication_t *sl_ind) {
module_id_t mod_id = sl_ind->module_id;
frame_t frame = sl_ind->frame_rx;
slot_t slot = sl_ind->slot_rx;
if (sl_ind->slot_type == SIDELINK_SLOT_TYPE_TX) {
frame = sl_ind->frame_tx;
slot = sl_ind->slot_tx;
}
NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
LOG_D(NR_MAC, "frame: %d, slot %d, slot type: %d, harq feedback %d\n", frame, slot, sl_ind->slot_type, mac->sci_pdu_rx.harq_feedback);
sl_nr_ue_mac_params_t *sl_mac = mac->SL_MAC_PARAMS;
sl_nr_phy_config_request_t *sl_cfg = &sl_mac->sl_phy_config.sl_config_req;
......@@ -3571,8 +3555,6 @@ void nr_ue_sidelink_scheduler(nr_sidelink_indication_t *sl_ind) {
// Check if PSBCH slot and PSBCH should be transmitted or Received
is_psbch_slot = nr_ue_sl_psbch_scheduler(sl_ind, sl_mac, &rx_config, &tx_config, &tti_action);
if (is_psbch_slot)
LOG_I(NR_MAC, "frame %d, slot %d slot type PSBCH %d\n", frame, slot, sl_ind->slot_type);
bool tx_allowed=true,rx_allowed=true;
if (mac->sl_tx_res_pool && mac->sl_tx_res_pool->ext1 && mac->sl_tx_res_pool->ext1->sl_TimeResource_r16) {
......@@ -3588,63 +3570,20 @@ void nr_ue_sidelink_scheduler(nr_sidelink_indication_t *sl_ind) {
if (((1<<slot_mod_period) % mask) == 0) rx_allowed=false;
}
if (sl_ind->slot_type==SIDELINK_SLOT_TYPE_TX || sl_ind->phy_data==NULL) rx_allowed=false;
LOG_D(NR_MAC, "sync_ref %d, slot_rx %d, rx_allowed %d, psbch slot %d\n", get_nrUE_params()->sync_ref, sl_ind->slot_rx, rx_allowed, !is_psbch_slot);
// if (get_nrUE_params()->sync_ref && rx_allowed && !is_psbch_slot) {
// NR_SL_PSFCH_Config_r16_t *sl_psfch_config = mac->sl_rx_res_pool->sl_PSFCH_Config_r16->choice.setup;
// const uint8_t psfch_periods[] = {0,1,2,4};
// long psfch_period = (sl_psfch_config->sl_PSFCH_Period_r16)
// ? psfch_periods[*sl_psfch_config->sl_PSFCH_Period_r16] : 0;
// if (slot%psfch_period == 0) {
// LOG_D(NR_MAC,"Scheduling PSFCH RX processing slot %d, sync_ref %d\n",slot,get_nrUE_params()->sync_ref);
// nr_ue_sl_psfch_rx_scheduler(mac, sl_ind, mac->sl_bwp->sl_BWP_Generic_r16, mac->sl_rx_res_pool, &rx_config, &tti_action);
// }
// }
if (((get_nrUE_params()->sync_ref && sl_ind->slot_rx > 9) ||
(!get_nrUE_params()->sync_ref && sl_ind->slot_rx < 10)) && rx_allowed && !is_psbch_slot) {
LOG_I(NR_MAC, "frame %d, slot %d slot type %d\n", frame, slot, sl_ind->slot_type);
if (((get_nrUE_params()->sync_ref && sl_ind->slot_rx > 9) ||
(!get_nrUE_params()->sync_ref && sl_ind->slot_rx < 10)) && rx_allowed && !is_psbch_slot) {
LOG_D(NR_MAC,"Scheduling PSCCH RX processing slot %d, sync_ref %d\n",slot,get_nrUE_params()->sync_ref);
nr_ue_sl_pscch_rx_scheduler(sl_ind, mac->sl_bwp, mac->sl_rx_res_pool,&rx_config, &tti_action);
}
if (!is_psbch_slot && tx_allowed) {
//Check if reserved slot or a sidelink resource configured in Rx/Tx resource pool timeresource bitmap
nr_ue_sl_pssch_scheduler(mac,sl_ind, mac->sl_bwp, mac->sl_tx_res_pool,&tx_config, &tti_action);
LOG_I(NR_MAC, "frame %d, slot %d slot type %d\n", frame, slot, sl_ind->slot_type);
}
// FIXIT: harq_feedback value has issue, more often it is displaying as zero
if (sl_ind->slot_type == SIDELINK_SLOT_TYPE_TX && mac->sci_pdu_rx.harq_feedback) {
NR_SL_PSFCH_Config_r16_t *sl_psfch_config = mac->sl_tx_res_pool->sl_PSFCH_Config_r16->choice.setup;
const uint8_t psfch_periods[] = {0,1,2,4};
long psfch_period = (sl_psfch_config->sl_PSFCH_Period_r16)
? psfch_periods[*sl_psfch_config->sl_PSFCH_Period_r16] : 0;
NR_UE_sl_harq_t *current_harq;
if (slot%psfch_period == 0) {
for (int harq_pid = 0; harq_pid < 16; harq_pid++) {
current_harq = &mac->sl_info.list[0]->UE_sched_ctrl.sl_harq_processes[harq_pid];
LOG_D(NR_MAC, "harq is active %p:%d\n", current_harq, current_harq->is_active);
sl_ind->slot_tx = current_harq->feedback_slot;
sl_ind->frame_tx = current_harq->feedback_frame;
LOG_D(NR_MAC, "Feedback frame %d:%d HARQ is_active %d\n", current_harq->feedback_frame, current_harq->feedback_slot, current_harq->is_active);
if (current_harq->is_active) {
LOG_D(NR_MAC, "harq pid %d, sl_ind->frame_tx %d, sl_ind->slot_tx %d, frame %d, slot %d\n", harq_pid, sl_ind->frame_tx, sl_ind->slot_tx, frame, slot);
if (current_harq->feedback_slot == slot && current_harq->feedback_frame == frame && current_harq->is_active) {
LOG_I(NR_MAC, "frame %d, slot %d slot type tx feedback\n", frame, slot);
LOG_D(NR_MAC, "Scheduling PSFCH transmission at frame %d slot %d for harq_pid %d\n", current_harq->feedback_frame, current_harq->feedback_slot, harq_pid);
nr_ue_sl_psfch_scheduler(mac, sl_ind, mac->sl_bwp, mac->sl_tx_res_pool, &tx_config, &tti_action);
current_harq->is_active = false;
current_harq->feedback_slot = -1;
current_harq->feedback_frame = -1;
break;
}
}
}
}
}
}
if (tti_action == SL_NR_CONFIG_TYPE_RX_PSBCH || tti_action == SL_NR_CONFIG_TYPE_RX_PSCCH || tti_action == SL_NR_CONFIG_TYPE_RX_PSSCH_SCI || tti_action == SL_NR_CONFIG_TYPE_RX_PSSCH_SLSCH) {
fill_scheduled_response(&scheduled_response, NULL, NULL, NULL, &rx_config, NULL, mod_id, 0,frame, slot, sl_ind->phy_data);
}
if (tti_action == SL_NR_CONFIG_TYPE_TX_PSBCH || tti_action == SL_NR_CONFIG_TYPE_TX_PSFCH || tti_action == SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH) {
LOG_D(NR_MAC, "tti_action %d, frame:slot %d:%d\n", tti_action, frame, slot);
if (tti_action == SL_NR_CONFIG_TYPE_TX_PSBCH || tti_action == SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH) {
fill_scheduled_response(&scheduled_response, NULL, NULL, NULL, NULL, &tx_config, mod_id, 0,frame, slot, sl_ind->phy_data);
}
......@@ -3660,44 +3599,3 @@ void nr_ue_sidelink_scheduler(nr_sidelink_indication_t *sl_ind) {
}
}
void nr_ue_sl_psfch_scheduler(NR_UE_MAC_INST_t *mac,
nr_sidelink_indication_t *sl_ind,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool,
sl_nr_tx_config_request_t *tx_config,
uint8_t *config_type) {
uint16_t slot = sl_ind->slot_tx;
uint16_t frame = sl_ind->frame_tx;
if (sl_ind->slot_type != SIDELINK_SLOT_TYPE_TX) return false;
NR_UE_sl_harq_t *current_harq;
for (int harq_pid = 0; harq_pid < 16; harq_pid++) {
current_harq = &mac->sl_info.list[0]->UE_sched_ctrl.sl_harq_processes[harq_pid];
if (current_harq->feedback_slot == slot && current_harq->feedback_frame == frame && current_harq->is_active) {
sl_nr_tx_config_psfch_pdu_t *tx_psfch_pdu = &tx_config->tx_config_list[0].tx_psfch_config_pdu;
tx_psfch_pdu->start_symbol_index = mac->sl_tx_config_psfch_pdu[harq_pid]->start_symbol_index;
tx_psfch_pdu->hopping_id = mac->sl_tx_config_psfch_pdu[harq_pid]->hopping_id;
tx_psfch_pdu->prb = mac->sl_tx_config_psfch_pdu[harq_pid]->prb;
tx_psfch_pdu->initial_cyclic_shift = mac->sl_tx_config_psfch_pdu[harq_pid]->initial_cyclic_shift;
tx_psfch_pdu->mcs = mac->sl_tx_config_psfch_pdu[harq_pid]->mcs;
tx_psfch_pdu->freq_hop_flag = 0;
tx_psfch_pdu->second_hop_prb = 0;
tx_psfch_pdu->group_hop_flag = 0;
tx_psfch_pdu->sequence_hop_flag = 0;
tx_psfch_pdu->nr_of_symbols = 1;
tx_psfch_pdu->psfch_payload = mac->sl_tx_config_psfch_pdu[harq_pid]->psfch_payload;
*config_type = SL_NR_CONFIG_TYPE_TX_PSFCH;
tx_config->number_pdus = 1;
tx_config->sfn = frame;
tx_config->slot = slot;
tx_config->tx_config_list[0].pdu_type = *config_type;
LOG_I(NR_MAC,"Harq id: %d, SL-PSFCH SCHEDULER: Frame:SLOT %d:%d, slot_type:%d\n",
harq_pid, frame, slot,sl_ind->slot_type);
break;
}
}
}
\ No newline at end of file
openair2/LAYER2/NR_MAC_UE/nr_ue_sci_slsch.c
View file @ 7e83f75d
......@@ -249,7 +249,6 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p
if (num_psfch_symbols == 3) num_psfch_symbols++;
}
nr_sl_pssch_pscch_pdu->pssch_numsym=7+*sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16-num_psfch_symbols-2;
LOG_D(NR_PHY, "num_psfch_symbols %d, sl_LengthSymbols: %d, pssch_numsym: %d\n", num_psfch_symbols, *sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16, nr_sl_pssch_pscch_pdu->pssch_numsym);
nr_sl_pssch_pscch_pdu->pssch_startsym = *sl_bwp->sl_BWP_Generic_r16->sl_StartSymbol_r16;
nr_sl_pssch_pscch_pdu->sci2_beta_offset = *sl_res_pool->sl_PSSCH_Config_r16->choice.setup->sl_BetaOffsets2ndSCI_r16->list.array[sci_pdu->beta_offset_indicator];
......@@ -462,25 +461,7 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p
nr_sl_pssch_pscch_pdu->slsch_payload_length = slsch_pdu_length;
};
void config_psfch_pdu_rx(NR_UE_MAC_INST_t *mac,
sl_nr_rx_config_psfch_pdu_t *nr_sl_psfch_pdu,
const NR_SL_BWP_Generic_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool) {
nr_sl_psfch_pdu->freq_hop_flag = 0;
nr_sl_psfch_pdu->group_hop_flag = 0;
nr_sl_psfch_pdu->sequence_hop_flag = 0;
nr_sl_psfch_pdu->second_hop_prb = 0;
nr_sl_psfch_pdu->nr_of_symbols = 1;
const uint8_t values[] = {7, 8, 9, 10, 11, 12, 13, 14};
uint8_t sl_num_symbols = *sl_bwp->sl_LengthSymbols_r16 ?
values[*sl_bwp->sl_LengthSymbols_r16] : 0;
nr_sl_psfch_pdu->start_symbol_index = *sl_bwp->sl_StartSymbol_r16 + sl_num_symbols - 2;
nr_sl_psfch_pdu->hopping_id = 0;
nr_sl_psfch_pdu->prb = 1;
//TODO
// nr_sl_psfch_pdu->initial_cyclic_shift = mac->sl_;
// nr_sl_psfch_pdu->mcs = mac->sl_;
}
void config_pscch_pdu_rx(sl_nr_rx_config_pscch_pdu_t *nr_sl_pscch_pdu,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
......@@ -816,7 +797,7 @@ int nr_ue_process_sci2_indication_pdu(NR_UE_MAC_INST_t *mac,module_id_t mod_id,f
sci->sci_format_type,sci->Nid,sci->subch_index,sci->sci_payloadlen,*(unsigned long long*)sci->sci_payloadBits);
AssertFatal(sci->sci_format_type == SL_SCI_FORMAT_2_ON_PSSCH, "need to have format 2 here only\n");
extract_pssch_sci_pdu((uint64_t *)sci->sci_payloadBits, sci->sci_payloadlen,sl_bwp, sl_res_pool, sci_pdu);
LOG_I(NR_MAC,"SCI2A: harq_pid %d ndi %d RV %d SRC %x DST %x HARQ_FB %d Cast %d CSI_Req %d\n", sci_pdu->harq_pid,sci_pdu->ndi,sci_pdu->rv_index,sci_pdu->source_id,sci_pdu->dest_id,sci_pdu->harq_feedback,sci_pdu->cast_type,sci_pdu->csi_req);
LOG_D(NR_MAC,"SCI2A: harq_pid %d ndi %d RV %d SRC %x DST %x HARQ_FB %d Cast %d CSI_Req %d\n", sci_pdu->harq_pid,sci_pdu->ndi,sci_pdu->rv_index,sci_pdu->source_id,sci_pdu->dest_id,sci_pdu->harq_feedback,sci_pdu->cast_type,sci_pdu->csi_req);
// send schedule response
sl_nr_rx_config_request_t rx_config;
......@@ -882,7 +863,7 @@ extract_pssch_sci_pdu(uint64_t *sci2_payload, int len,
fsize = 1;
pos+=fsize;
sci_pdu->harq_feedback = *sci2_payload>>(sci2_size-pos)&((1<<fsize)-1);
LOG_I(NR_MAC,"harq_feedback (%d) in pos %d sci2_payload %lu, (sci2_size-pos) %d, mask %d\n",sci_pdu->harq_feedback, pos-fsize, *sci2_payload, (sci2_size-pos), ((1<<fsize)-1));
LOG_D(NR_MAC,"harq_feedback (%d) in pos %d\n",sci_pdu->harq_feedback,pos-fsize);
//cast_type // 2 bits formac 2A
fsize = 2;
......
sl_preconfiguration.conf
View file @ 7e83f75d
SIDELINK_PRECONFIGURATION = (
{
# TDD ULDL CONFIG used for sidelink
sl_dl_UL_TransmissionPeriodicity = 6;
sl_nrofDownlinkSlots = 1;
sl_nrofDownlinkSymbols = 10;
sl_nrofUplinkSlots = 8;
sl_nrofUplinkSymbols = 4;
sl_FrequencyCommonConfig = (
{
sl_offstToCarrier = 0;
sl_subcarrierSpacing = 1;//0-15Khz, 1-30Khz
sl_carrierBandwidth = 106;//numPRBs
#NR bands for Sidelink n47, n38. N47 - 5855Mhz - 5925Mhz
#SL SSB chosen to be located from RB10 to RB21. points to the middle of the SSB block.
#SSB location should be within Sidelink BWP
# this is 2584.95 MHz => 301 REs from PointA 25 PRBs + 1 RE
sl_absoluteFrequencySSB = 516990;
# this is 2575.92 MHz (center frequency is 2585.1 MHz
sl_absoluteFrequencyPointA = 515184;
}
);
sl_BWP = (
{
#RB start 0, RB size = 106. occupies complete Bw.
sl_locationAndBandwidth = 28875;
#Num Symbols used for Sidelink in an uplink slot
#Value can be between symbols 7 to 14
sl_LengthSymbols = 5;
#Sidelink Starting symbol in a slot
#Value can be between symbols 0 to 7
sl_StartSymbol = 0;
}
);
sl_syncCfg = (
{
#NUM SL-SSB within 16 frames
sl_NumSSB_WithinPeriod_0 = 4;
#Slot Offset for the first txn in the 16 frame period
sl_TimeOffsetSSB_0 = 8;
#interval in slots for repetition of SL-SSB
sl_TimeInterval_0 = 120;
}
);
sl_RxResPools = (
{
#Number of symbols which carry PSCCH.
#Possible values 0 means 2 symbols, 1 - means 3 symbols.
sl_TimeResourcePSCCH = 0;
#Number of RBS which carry PSCCH
#Possible values {n10,n12,n15,n20,n25}
sl_FreqResourcePSCCH = 1; //12RBs
#Size of subchannel in RBs
#Possible values - {n10,n12,n15,n20,n25,n50,n75,n100}
sl_SubchannelSize = 5;//10RBs
#start in RB of the lowest subchannel in a rpool
sl_StartRB_Subchannel = 0;
#number of PRBs in a rpool
sl_RB_Number = 50;
sl_NumSubchannel = 1;
# period of PSFCH resource in units of slots within this resource pool
# Possible values sl0 means no PSFCH resource, {sl0, sl1, sl2, sl4}
sl_PSFCH_Period = 3; //sl4
# set of PRBs used for PSFCH transmission and reception
# leftmost bit of the bitmap is lowest RB index in the resource pool
# value 0 in the bitmap means PRB is not used for PSFCH operations
sl_PSFCH_RB_Set = 0xAAAAAAAAAAAA8;
# Number of cyclic shift pairs used for a PSFCH transmission that can be multiplexed in a PRB
# Possible values {n1, n2, n3, n4}
sl_NumMuxCS_Pair = 1;
# Minimum time gap between PSFCH and the associated PSSCH in the unit of slots {sl2, sl3}
sl_MinTimeGapPSFCH = 1; //sl3
# Scrambling ID {0..1023} for sequence hopping of the PSFCH used in the resource pool
sl_PSFCH_HopID = 1;
# Number of PSFCH resources available {startSubCH, allocSubCH} for multiplexing HARQ-ACK information in a PSFCH transmission
sl_PSFCH_CandidateResourceType = 0; // startSubCH
}
);
sl_TxResPools = (
{
#Number of symbols which carry PSCCH.
#Possible values 0 means 2 symbols, 1 - means 3 symbols.
sl_TimeResourcePSCCH = 0;
#Number of RBS which carry PSCCH
#Possible values {n10,n12,n15,n20,n25}
sl_FreqResourcePSCCH = 1; //12RBs
#Size of subchannel in RBs
#Possible values - {n10,n12,n15,n20,n25,n50,n75,n100}
sl_SubchannelSize = 5;//50RBs
#start in RB of the lowest subchannel in a rpool
sl_StartRB_Subchannel = 0;
#number of PRBs in a rpool
sl_RB_Number = 50;
sl_NumSubchannel = 1;
}
);
sl_UEINFO = (
{
srcid = 0;
thirdOctet = 0;
fourthOctet = 1;
}
);
}
);
\ No newline at end of file
SIDELINK_PRECONFIGURATION = (
{
# TDD ULDL CONFIG used for sidelink
sl_dl_UL_TransmissionPeriodicity = 6;
sl_nrofDownlinkSlots = 1;
sl_nrofDownlinkSymbols = 10;
sl_nrofUplinkSlots = 8;
sl_nrofUplinkSymbols = 4;
sl_FrequencyCommonConfig = (
{
sl_offstToCarrier = 0;
sl_subcarrierSpacing = 1;//0-15Khz, 1-30Khz
sl_carrierBandwidth = 106;//numPRBs
#NR bands for Sidelink n47, n38. N47 - 5855Mhz - 5925Mhz
#SL SSB chosen to be located from RB10 to RB21. points to the middle of the SSB block.
#SSB location should be within Sidelink BWP
# this is 2584.95 MHz => 301 REs from PointA 25 PRBs + 1 RE
sl_absoluteFrequencySSB = 516990;
# this is 2575.92 MHz (center frequency is 2585.1 MHz
sl_absoluteFrequencyPointA = 515184;
}
);
sl_BWP = (
{
#RB start 0, RB size = 106. occupies complete Bw.
sl_locationAndBandwidth = 28875;
#Num Symbols used for Sidelink in an uplink slot
#Value can be between symbols 7 to 14
sl_LengthSymbols = 5;
#Sidelink Starting symbol in a slot
#Value can be between symbols 0 to 7
sl_StartSymbol = 0;
}
);
sl_syncCfg = (
{
#NUM SL-SSB within 16 frames
sl_NumSSB_WithinPeriod_0 = 4;
#Slot Offset for the first txn in the 16 frame period
sl_TimeOffsetSSB_0 = 8;
#interval in slots for repetition of SL-SSB
sl_TimeInterval_0 = 120;
}
);
sl_RxResPools = (
{
#Number of symbols which carry PSCCH.
#Possible values 0 means 2 symbols, 1 - means 3 symbols.
sl_TimeResourcePSCCH = 0;
#Number of RBS which carry PSCCH
#Possible values {n10,n12,n15,n20,n25}
sl_FreqResourcePSCCH = 1; //12RBs
#Size of subchannel in RBs
#Possible values - {n10,n12,n15,n20,n25,n50,n75,n100}
sl_SubchannelSize = 5;//10RBs
#start in RB of the lowest subchannel in a rpool
sl_StartRB_Subchannel = 0;
#number of PRBs in a rpool
sl_RB_Number = 50;
sl_NumSubchannel = 1;
# period of PSFCH resource in units of slots within this resource pool
# Possible values sl0 means no PSFCH resource, {sl0, sl1, sl2, sl4}
sl_PSFCH_Period = 3; //sl4
# set of PRBs used for PSFCH transmission and reception
# leftmost bit of the bitmap is lowest RB index in the resource pool
# value 0 in the bitmap means PRB is not used for PSFCH operations
sl_PSFCH_RB_Set = 0xAAAAAAAAAAAA8;
# Number of cyclic shift pairs used for a PSFCH transmission that can be multiplexed in a PRB
# Possible values {n1, n2, n3, n4}
sl_NumMuxCS_Pair = 1;
# Minimum time gap between PSFCH and the associated PSSCH in the unit of slots {sl2, sl3}
sl_MinTimeGapPSFCH = 1; //sl3
# Scrambling ID {0..1023} for sequence hopping of the PSFCH used in the resource pool
sl_PSFCH_HopID = 1;
# Number of PSFCH resources available {startSubCH, allocSubCH} for multiplexing HARQ-ACK information in a PSFCH transmission
sl_PSFCH_CandidateResourceType = 0; // startSubCH
}
);
sl_TxResPools = (
{
#Number of symbols which carry PSCCH.
#Possible values 0 means 2 symbols, 1 - means 3 symbols.
sl_TimeResourcePSCCH = 0;
#Number of RBS which carry PSCCH
#Possible values {n10,n12,n15,n20,n25}
sl_FreqResourcePSCCH = 1; //12RBs
#Size of subchannel in RBs
#Possible values - {n10,n12,n15,n20,n25,n50,n75,n100}
sl_SubchannelSize = 5;//50RBs
#start in RB of the lowest subchannel in a rpool
sl_StartRB_Subchannel = 0;
#number of PRBs in a rpool
sl_RB_Number = 50;
sl_NumSubchannel = 1;
}
);
sl_UEINFO = (
{
srcid = 0;
thirdOctet = 0;
fourthOctet = 1;
}
);
}
);
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