Commit b28ae819 authored by Xiwen JIANG's avatar Xiwen JIANG

Merge branch 'feature-21-TM7' of...

Merge branch 'feature-21-TM7' of https://gitlab.eurecom.fr/oai/openairinterface5g into feature-21-TM7
parents b53959c1 035fc74c
...@@ -226,8 +226,9 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc) ...@@ -226,8 +226,9 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
memcpy((void*)&DCI_pdu->dci_alloc[0].dci_pdu[0],(void *)&DLSCH_alloc_pdu1,sizeof(DCI2_5MHz_2A_M10PRB_TDD_t)); memcpy((void*)&DCI_pdu->dci_alloc[0].dci_pdu[0],(void *)&DLSCH_alloc_pdu1,sizeof(DCI2_5MHz_2A_M10PRB_TDD_t));
break; break;
*/ */
case 8:
case 9: case 9:
case 0:
DCI_pdu->Num_ue_spec_dci = 1; DCI_pdu->Num_ue_spec_dci = 1;
//user 1 //user 1
...@@ -244,7 +245,7 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc) ...@@ -244,7 +245,7 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
UL_alloc_pdu.type = 0; UL_alloc_pdu.type = 0;
UL_alloc_pdu.hopping = 0; UL_alloc_pdu.hopping = 0;
UL_alloc_pdu.rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb); UL_alloc_pdu.rballoc = computeRIV(25,0,25);
UL_alloc_pdu.mcs = eNB->target_ue_ul_mcs; UL_alloc_pdu.mcs = eNB->target_ue_ul_mcs;
UL_alloc_pdu.ndi = proc->frame_tx&1; UL_alloc_pdu.ndi = proc->frame_tx&1;
UL_alloc_pdu.TPC = 0; UL_alloc_pdu.TPC = 0;
...@@ -254,8 +255,7 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc) ...@@ -254,8 +255,7 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
memcpy((void*)&DCI_pdu->dci_alloc[0].dci_pdu[0],(void *)&UL_alloc_pdu,sizeof(DCI0_5MHz_TDD_1_6_t)); memcpy((void*)&DCI_pdu->dci_alloc[0].dci_pdu[0],(void *)&UL_alloc_pdu,sizeof(DCI0_5MHz_TDD_1_6_t));
break; break;
case 6:
default:
case 7: case 7:
DCI_pdu->Num_ue_spec_dci = 1; DCI_pdu->Num_ue_spec_dci = 1;
DCI_pdu->dci_alloc[0].L = 2; DCI_pdu->dci_alloc[0].L = 2;
...@@ -611,8 +611,8 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc) ...@@ -611,8 +611,8 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
break; break;
*/ */
/*default: default:
break;*/ break;
} }
/* /*
......
...@@ -2017,7 +2017,7 @@ void prach_procedures(PHY_VARS_eNB *eNB) { ...@@ -2017,7 +2017,7 @@ void prach_procedures(PHY_VARS_eNB *eNB) {
eNB->UE_stats[(uint32_t)UE_id].UE_timing_offset = preamble_delay_list[preamble_max]&0x1FFF; //limit to 13 (=11+2) bits eNB->UE_stats[(uint32_t)UE_id].UE_timing_offset = preamble_delay_list[preamble_max]&0x1FFF; //limit to 13 (=11+2) bits
eNB->UE_stats[(uint32_t)UE_id].sector = 0; eNB->UE_stats[(uint32_t)UE_id].sector = 0;
LOG_D(PHY,"[eNB %d/%d][RAPROC] Frame %d, subframe %d Initiating RA procedure (UE_id %d) with preamble %d, energy %d.%d dB, delay %d\n", LOG_I(PHY,"[eNB %d/%d][RAPROC] Frame %d, subframe %d Initiating RA procedure (UE_id %d) with preamble %d, energy %d.%d dB, delay %d\n",
eNB->Mod_id, eNB->Mod_id,
eNB->CC_id, eNB->CC_id,
frame, frame,
......
...@@ -853,7 +853,7 @@ void schedule_ulsch_rnti(module_id_t module_idP, ...@@ -853,7 +853,7 @@ void schedule_ulsch_rnti(module_id_t module_idP,
UE_list->eNB_UE_stats[CC_id][UE_id].normalized_rx_power=normalized_rx_power; UE_list->eNB_UE_stats[CC_id][UE_id].normalized_rx_power=normalized_rx_power;
UE_list->eNB_UE_stats[CC_id][UE_id].target_rx_power=target_rx_power; UE_list->eNB_UE_stats[CC_id][UE_id].target_rx_power=target_rx_power;
UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1=UE_template->pre_assigned_mcs_ul; UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1=UE_template->pre_assigned_mcs_ul;
mcs = UE_template->pre_assigned_mcs_ul;//cmin (UE_template->pre_assigned_mcs_ul, openair_daq_vars.target_ue_ul_mcs); // adjust, based on user-defined MCS mcs = cmin (UE_template->pre_assigned_mcs_ul, 10); // adjust, based on user-defined MCS
if (UE_template->pre_allocated_rb_table_index_ul >=0) { if (UE_template->pre_allocated_rb_table_index_ul >=0) {
rb_table_index=UE_template->pre_allocated_rb_table_index_ul; rb_table_index=UE_template->pre_allocated_rb_table_index_ul;
} else { } else {
......
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