Commit eac9ec05 authored by francescomani's avatar francescomani

handling MAC-CellGroupConfig at MAC UE

parent c5aeaf03
......@@ -942,6 +942,59 @@ void configure_physicalcellgroup(NR_UE_MAC_INST_t *mac,
*p_UE_FR1 : *p_NR_FR1);
}
void configure_maccellgroup(NR_UE_MAC_INST_t *mac, const NR_MAC_CellGroupConfig_t *mcg)
{
NR_UE_SCHEDULING_INFO *si = &mac->scheduling_info;
if (mcg->drx_Config)
LOG_E(NR_MAC, "DRX not implemented! Configuration not handled!\n");
if (mcg->schedulingRequestConfig) {
const NR_SchedulingRequestConfig_t *src = mcg->schedulingRequestConfig;
if (src->schedulingRequestToReleaseList) {
for (int i = 0; i < src->schedulingRequestToReleaseList->list.count; i++) {
if (*src->schedulingRequestToReleaseList->list.array[i] == si->sr_id) {
si->SR_COUNTER = 0;
si->sr_ProhibitTimer = 0;
si->sr_ProhibitTimer_Running = 0;
si->sr_id = -1; // invalid init value
}
else
LOG_E(NR_MAC, "Cannot release SchedulingRequestConfig. Not configured.\n");
}
}
if (src->schedulingRequestToAddModList) {
for (int i = 0; i < src->schedulingRequestToAddModList->list.count; i++) {
NR_SchedulingRequestToAddMod_t *sr = src->schedulingRequestToAddModList->list.array[i];
AssertFatal(si->sr_id == -1 ||
si->sr_id == sr->schedulingRequestId,
"Current implementation cannot handle more than 1 SR configuration\n");
si->sr_id = sr->schedulingRequestId;
si->sr_TransMax = sr->sr_TransMax;
if (sr->sr_ProhibitTimer)
LOG_E(NR_MAC, "SR prohibit timer not properly implemented\n");
}
}
}
if (mcg->bsr_Config) {
si->periodicBSR_Timer = mcg->bsr_Config->periodicBSR_Timer;
si->retxBSR_Timer = mcg->bsr_Config->retxBSR_Timer;
if (mcg->bsr_Config->logicalChannelSR_DelayTimer)
LOG_E(NR_MAC, "Handling of logicalChannelSR_DelayTimer not implemented\n");
}
if (mcg->tag_Config) {
// TODO TAG not handled
if(mcg->tag_Config->tag_ToAddModList) {
for (int i = 0; i < mcg->tag_Config->tag_ToAddModList->list.count; i++) {
if (mcg->tag_Config->tag_ToAddModList->list.array[i]->timeAlignmentTimer !=
NR_TimeAlignmentTimer_infinity)
LOG_E(NR_MAC, "TimeAlignmentTimer not handled\n");
}
}
}
if (mcg->phr_Config) {
// TODO configuration when PHR is implemented
}
}
void nr_rrc_mac_config_req_cg(module_id_t module_id,
int cc_idP,
NR_CellGroupConfig_t *cell_group_config)
......@@ -950,9 +1003,8 @@ void nr_rrc_mac_config_req_cg(module_id_t module_id,
AssertFatal(cell_group_config, "CellGroupConfig should not be NULL\n");
NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
if (cell_group_config->mac_CellGroupConfig) {
// TODO handle MAC-CellGroupConfig
}
if (cell_group_config->mac_CellGroupConfig)
configure_maccellgroup(mac, cell_group_config->mac_CellGroupConfig);
if (cell_group_config->physicalCellGroupConfig)
configure_physicalcellgroup(mac, cell_group_config->physicalCellGroupConfig);
......
......@@ -196,8 +196,6 @@ typedef struct {
NR_LC_SCHEDULING_INFO lc_sched_info[NR_MAX_NUM_LCID];
// lcg scheduling info
NR_LCG_SCHEDULING_INFO lcg_sched_info[NR_MAX_NUM_LCGID];
/// sum of all lcid buffer size
uint16_t All_lcid_buffer_size_lastTTI;
/// SR pending as defined in 38.321
uint8_t SR_pending;
/// SR_COUNTER as defined in 38.321
......@@ -214,14 +212,9 @@ typedef struct {
uint16_t sr_ProhibitTimer;
/// sr ProhibitTime running
uint8_t sr_ProhibitTimer_Running;
/// default value to n5
uint16_t maxHARQ_Tx;
/// default value is false
uint16_t ttiBundling;
/// default value is release
struct DRX_Config *drx_config;
/// default value is release
struct MAC_MainConfig__phr_Config *phr_config;
// Maximum number of SR transmissions
uint32_t sr_TransMax;
int sr_id;
///timer before triggering a periodic PHR
uint16_t periodicPHR_Timer;
///timer before triggering a prohibit PHR
......@@ -234,7 +227,6 @@ typedef struct {
int16_t prohibitPHR_SF;
///DL Pathloss Change in db
uint16_t PathlossChange_db;
/// default value is false
uint16_t extendedBSR_Sizes_r10;
/// default value is false
......
......@@ -182,6 +182,7 @@ void nr_ue_mac_default_configs(NR_UE_MAC_INST_t *mac)
mac->scheduling_info.SR_COUNTER = 0;
mac->scheduling_info.sr_ProhibitTimer = 0;
mac->scheduling_info.sr_ProhibitTimer_Running = 0;
mac->scheduling_info.sr_id = -1; // invalid init value
// set init value 0xFFFF, make sure periodic timer and retx time counters are NOT active, after bsr transmission set the value
// configured by the NW.
......@@ -2424,32 +2425,34 @@ bool trigger_periodic_scheduling_request(NR_UE_MAC_INST_t *mac, PUCCH_sched_t *p
return sr_count > 0 ? true : false;
}
int8_t nr_ue_get_SR(module_id_t module_idP, frame_t frameP, slot_t slot){
int8_t nr_ue_get_SR(module_id_t module_idP, frame_t frameP, slot_t slot)
{
// no UL-SCH resources available for this tti && UE has a valid PUCCH resources for SR configuration for this tti
DevCheck(module_idP < NB_NR_UE_MAC_INST, module_idP, NB_NR_UE_MAC_INST, 0);
NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP);
DSR_TRANSMAX_t dsr_TransMax = sr_n64; // todo
LOG_D(NR_MAC, "[UE %d] Frame %d slot %d send SR indication (SR_COUNTER/dsr_TransMax %d/%d), SR_pending %d\n",
NR_UE_SCHEDULING_INFO *si = &mac->scheduling_info;
int max_sr_transmissions = (1 << (2 + si->sr_TransMax));
LOG_D(NR_MAC, "[UE %d] Frame %d slot %d send SR indication (SR_COUNTER/sr_TransMax %d/%d), SR_pending %d\n",
module_idP, frameP, slot,
mac->scheduling_info.SR_COUNTER,
(1 << (2 + dsr_TransMax)),
mac->scheduling_info.SR_pending); // todo
si->SR_COUNTER,
max_sr_transmissions,
si->SR_pending); // todo
if ((mac->scheduling_info.SR_pending == 1) &&
(mac->scheduling_info.SR_COUNTER < (1 << (2 + dsr_TransMax)))) {
LOG_D(NR_MAC, "[UE %d] Frame %d slot %d PHY asks for SR (SR_COUNTER/dsr_TransMax %d/%d), SR_pending %d, increment SR_COUNTER\n",
if ((si->SR_pending == 1) &&
(si->SR_COUNTER < max_sr_transmissions)) {
LOG_D(NR_MAC, "[UE %d] Frame %d slot %d PHY asks for SR (SR_COUNTER/sr_TransMax %d/%d), SR_pending %d, increment SR_COUNTER\n",
module_idP, frameP, slot,
mac->scheduling_info.SR_COUNTER,
(1 << (2 + dsr_TransMax)),
mac->scheduling_info.SR_pending); // todo
mac->scheduling_info.SR_COUNTER++;
si->SR_COUNTER,
max_sr_transmissions,
si->SR_pending); // todo
si->SR_COUNTER++;
// start the sr-prohibittimer : rel 9 and above
if (mac->scheduling_info.sr_ProhibitTimer > 0) { // timer configured
mac->scheduling_info.sr_ProhibitTimer--;
mac->scheduling_info.sr_ProhibitTimer_Running = 1;
if (si->sr_ProhibitTimer > 0) { // timer configured
si->sr_ProhibitTimer--;
si->sr_ProhibitTimer_Running = 1;
} else {
mac->scheduling_info.sr_ProhibitTimer_Running = 0;
si->sr_ProhibitTimer_Running = 0;
}
//mac->ul_active =1;
return (1); //instruct phy to signal SR
......@@ -2457,7 +2460,7 @@ int8_t nr_ue_get_SR(module_id_t module_idP, frame_t frameP, slot_t slot){
// notify RRC to relase PUCCH/SRS
// clear any configured dl/ul
// initiate RA
if (mac->scheduling_info.SR_pending) {
if (si->SR_pending) {
// release all pucch resource
//mac->physicalConfigDedicated = NULL; // todo
//mac->ul_active = 0; // todo
......@@ -2465,9 +2468,8 @@ int8_t nr_ue_get_SR(module_id_t module_idP, frame_t frameP, slot_t slot){
NR_BSR_TRIGGER_NONE;
LOG_I(NR_MAC, "[UE %d] Release all SRs \n", module_idP);
}
mac->scheduling_info.SR_pending = 0;
mac->scheduling_info.SR_COUNTER = 0;
si->SR_pending = 0;
si->SR_COUNTER = 0;
return (0);
}
}
......
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