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Commit ebd07cb5 authored by Florian Kaltenberger's avatar Florian Kaltenberger
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Merge branch 'develop-nr' into nr-pdsch

parents 714cdc09 4280122c
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Showing with 125 additions and 72 deletions
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
View file @ ebd07cb5
......@@ -49,9 +49,10 @@
/// UL_CONFIG_REQ
#define FAPI_NR_UL_CONFIG_LIST_NUM 10
#define FAPI_NR_DL_CONFIG_TYPE_PRACH 0x01
#define FAPI_NR_DL_CONFIG_TYPE_PUCCH 0x02
#define FAPI_NR_DL_CONFIG_TYPE_PUSCH 0x03
#define FAPI_NR_UL_CONFIG_TYPE_PRACH 0x01
#define FAPI_NR_UL_CONFIG_TYPE_PUCCH 0x02
#define FAPI_NR_UL_CONFIG_TYPE_PUSCH 0x03
#define FAPI_NR_UL_CONFIG_TYPE_SRS 0x04
#endif
\ No newline at end of file
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
View file @ ebd07cb5
......@@ -219,8 +219,20 @@ typedef struct {
} fapi_nr_tx_request_t;
typedef struct {
} fapi_nr_ul_config_rach_pdu;
uint8_t preamble_index;
uint8_t prach_configuration_index;
uint16_t preamble_length;
uint8_t power_ramping_step;
uint16_t preamble_received_target_power;
uint8_t msg1_fdm;
uint8_t msg1_frequency_start;
uint8_t zero_correlation_zone_config;
uint8_t subcarrier_spacing;
uint8_t restrictedset_config;
uint16_t root_sequence_index;
uint16_t rsrp_threshold_ssb;
uint16_t rsrp_threshold_sul;
} fapi_nr_ul_config_prach_pdu;
typedef struct {
......@@ -232,6 +244,8 @@ typedef struct {
uint16_t number_symbols;
uint16_t start_symbol;
uint8_t mcs;
uint8_t tpc_command;
uint8_t rv;
} fapi_nr_ul_config_pusch_pdu_rel15_t;
typedef struct {
......@@ -239,16 +253,20 @@ typedef struct {
fapi_nr_ul_config_pusch_pdu_rel15_t ulsch_pdu_rel15;
} fapi_nr_ul_config_pusch_pdu;
typedef struct {
} fapi_nr_ul_config_srs_pdu;
typedef struct {
uint8_t pdu_type;
union {
fapi_nr_ul_config_rach_pdu prach_config_pdu;
fapi_nr_ul_config_prach_pdu prach_config_pdu;
fapi_nr_ul_config_pucch_pdu pucch_config_pdu;
fapi_nr_ul_config_pusch_pdu ulsch_config_pdu;
fapi_nr_ul_config_srs_pdu srs_config_pdu;
};
} fapi_nr_ul_config_request_pdu_t;
///
typedef struct {
uint32_t sfn_slot;
uint8_t number_pdus;
......@@ -273,7 +291,6 @@ typedef struct {
fapi_nr_dl_config_dci_dl_pdu_rel15_t dci_config_rel15;
} fapi_nr_dl_config_dci_pdu;
//typedef fapi_nr_dci_pdu_rel15_t fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
uint16_t number_rbs;
uint16_t start_rb;
......@@ -281,7 +298,9 @@ typedef struct {
uint16_t start_symbol;
uint8_t mcs;
uint8_t rv;
// to be check the fields needed to L1 with NR_DL_UE_HARQ_t and NR_UE_DLSCH_t
uint8_t harq_pid;
uint8_t ndi;
// TODO: check the fields needed to L1 with NR_DL_UE_HARQ_t and NR_UE_DLSCH_t
} fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
......
openair1/PHY/INIT/nr_parms.c
View file @ ebd07cb5
......@@ -274,7 +274,7 @@ int nr_init_frame_parms_ue(NR_DL_FRAME_PARMS *frame_parms)
frame_parms->ofdm_symbol_size = 2048;
frame_parms->samples_per_tti = 30720;
frame_parms->samples_per_subframe = 30720 * frame_parms->ttis_per_subframe;
frame_parms->first_carrier_offset = 2048-600;
//frame_parms->first_carrier_offset = 2048-600;
frame_parms->symbols_per_slot = ((Ncp == NORMAL)? 14 : 12); // to redefine for different slot formats
frame_parms->samples_per_subframe_wCP = frame_parms->ofdm_symbol_size * frame_parms->symbols_per_slot * frame_parms->slots_per_subframe;
......
openair1/PHY/MODULATION/slot_fep.c
View file @ ebd07cb5
......@@ -50,7 +50,7 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
unsigned int frame_length_samples = frame_parms->samples_per_subframe * 10;
unsigned int rx_offset;
//NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[Ns>>1]][0];
uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset;
uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset+516;
uint16_t nb_rb_coreset = 24;
uint16_t bwp_start_subcarrier = frame_parms->first_carrier_offset;
uint16_t nb_rb_pdsch = 100;
......@@ -239,7 +239,7 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
for (aa=0; aa<frame_parms->nb_antenna_ports_eNB; aa++) {
#ifdef DEBUG_FEP
printf("Channel estimation eNB %d, aatx %d, slot %d, symbol %d\n",eNB_id,aa,Ns,l);
printf("PDCCH Channel estimation eNB %d, aatx %d, slot %d, symbol %d start_sc %d\n",eNB_id,aa,Ns,l,coreset_start_subcarrier);
#endif
#if UE_TIMING_TRACE
start_meas(&ue->dlsch_channel_estimation_stats);
......
openair1/PHY/NR_REFSIG/nr_dmrs_rx.c
View file @ ebd07cb5
......@@ -205,8 +205,9 @@ int nr_pdcch_dmrs_rx(PHY_VARS_NR_UE *ue,
((int16_t*)output)[i<<1] = nr_rx_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1];
((int16_t*)output)[(i<<1)+1] = nr_rx_mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1];
#ifdef DEBUG_PDCCH
printf("i %d idx %d pdcch gold %d b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, nr_gold_pdcch[(i<<1)>>5], (((nr_gold_pdcch[(i<<1)>>5])>>((i<<1)&0x1f))&1),
(((nr_gold_pdcch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[i<<1], ((int16_t*)output)[(m<<1)+1],&output[0]);
if (i<8)
printf("i %d idx %d pdcch gold %u b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, nr_gold_pdcch[(i<<1)>>5], (((nr_gold_pdcch[(i<<1)>>5])>>((i<<1)&0x1f))&1),
(((nr_gold_pdcch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[i<<1], ((int16_t*)output)[(i<<1)+1],&output[0]);
#endif
}
}
......
openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
View file @ ebd07cb5
......@@ -112,21 +112,21 @@ int nr_pbch_channel_estimation(PHY_VARS_NR_UE *ue,
multadd_complex_vector_real_scalar(dl_ch-(ue->frame_parms.ofdm_symbol_size<<1),
ue->ch_est_alpha,dl_ch-(ue->frame_parms.ofdm_symbol_size<<1),
1,ue->frame_parms.ofdm_symbol_size);
//#ifdef DEBUG_CH
printf("ch est pilot addr %p RB_DL %d\n",&pilot[p][0], ue->frame_parms.N_RB_DL);
#ifdef DEBUG_CH
printf("pbch ch est pilot addr %p RB_DL %d\n",&pilot[p][0], ue->frame_parms.N_RB_DL);
printf("k %d, first_carrier %d\n",k,ue->frame_parms.first_carrier_offset);
printf("rxF addr %p\n", rxF);
printf("dl_ch addr %p\n",dl_ch);
//#endif
#endif
//if ((ue->frame_parms.N_RB_DL&1)==0) {
// Treat first 2 pilots specially (left edge)
ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
//#ifdef DEBUG_CH
#ifdef DEBUG_CH
printf("ch 0 %d\n",((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1]));
printf("pilot 0 : rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],&rxF[0],ch[0],ch[1],pil[0],pil[1]);
//#endif
#endif
multadd_real_vector_complex_scalar(fl,
ch,
dl_ch,
......@@ -257,7 +257,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
k = coreset_start_subcarrier;
#ifdef DEBUG_CH
printf("PBCH Channel Estimation : ThreadId %d, eNB_offset %d cell_id %d ch_offset %d, OFDM size %d, Ncp=%d, l=%d, Ns=%d, k=%d symbol %d\n",ue->current_thread_id[Ns>>1], eNB_offset,Nid_cell,ch_offset,ue->frame_parms.ofdm_symbol_size,
printf("PDCCH Channel Estimation : ThreadId %d, eNB_offset %d ch_offset %d, OFDM size %d, Ncp=%d, l=%d, Ns=%d, k=%d symbol %d\n",ue->current_thread_id[Ns>>1], eNB_offset,ch_offset,ue->frame_parms.ofdm_symbol_size,
ue->frame_parms.Ncp,l,Ns,k, symbol);
#endif
......@@ -279,12 +279,12 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
multadd_complex_vector_real_scalar(dl_ch-(ue->frame_parms.ofdm_symbol_size<<1),
ue->ch_est_alpha,dl_ch-(ue->frame_parms.ofdm_symbol_size<<1),
1,ue->frame_parms.ofdm_symbol_size);
#ifdef DEBUG_CH
printf("ch est pilot addr %p RB_DL %d\n",&pilot[p][0], ue->frame_parms.N_RB_DL);
//#ifdef DEBUG_CH
printf("pdcch ch est pilot addr %p RB_DL %d\n",&pilot[p][0], ue->frame_parms.N_RB_DL);
printf("k %d, first_carrier %d\n",k,ue->frame_parms.first_carrier_offset);
printf("rxF addr %p\n", rxF);
printf("dl_ch addr %p\n",dl_ch);
#endif
//#endif
if ((ue->frame_parms.N_RB_DL&1)==0) {
// Treat first 2 pilots specially (left edge)
......
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @ ebd07cb5
......@@ -50,7 +50,7 @@
//#define NR_LTE_PDCCH_DCI_SWITCH
#define NR_PDCCH_DCI_RUN // activates new nr functions
#define NR_PDCCH_DCI_DEBUG // activates NR_PDCCH_DCI_DEBUG logs
//#define NR_PDCCH_DCI_DEBUG // activates NR_PDCCH_DCI_DEBUG logs
#define NR_NBR_CORESET_ACT_BWP 3 // The number of CoreSets per BWP is limited to 3 (including initial CORESET: ControlResourceId 0)
#define NR_NBR_SEARCHSPACE_ACT_BWP 10 // The number of SearSpaces per BWP is limited to 10 (including initial SEARCHSPACE: SearchSpaceId 0)
......
openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c
View file @ ebd07cb5
......@@ -238,6 +238,11 @@ int nr_initial_sync(PHY_VARS_NR_UE *ue, runmode_t mode)
nr_gold_pbch(ue);
ret = nr_pbch_detection(ue,mode);
nr_gold_pdcch(ue,0, 2);
nr_slot_fep(ue,0, 0, ue->rx_offset, 1, 1, NR_PDCCH_EST);
nr_slot_fep(ue,1, 0, ue->rx_offset, 1, 1, NR_PDCCH_EST);
LOG_I(PHY,"[UE %d] AUTOTEST Cell Sync : frame = %d, rx_offset %d, freq_offset %d \n",
ue->Mod_id,
......
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
View file @ ebd07cb5
......@@ -48,7 +48,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
uint32_t i;
if(scheduled_response != NULL){
NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[0][0];
PHY_VARS_NR_UE *ue = PHY_vars_UE_g[module_id][cc_id];
NR_UE_PDCCH *pdcch_vars2 = ue->pdcch_vars[0][0];
if(scheduled_response->dl_config != NULL){
fapi_nr_dl_config_request_t *dl_config = scheduled_response->dl_config;
......@@ -88,6 +89,22 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
pdcch_vars2->coreset[i].pdcchDMRSScramblingID = dci_config->coreset.pdcch_dmrs_scrambling_id;
}else{ //FAPI_NR_DL_CONFIG_TYPE_DLSCH
// dlsch config pdu
fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15;
NR_UE_DLSCH_t **dlsch = ue->dlsch[ue->current_thread_id[0]][0]; //nr_tti_rx
NR_UE_DLSCH_t *dlsch0 = dlsch[0];
NR_DL_UE_HARQ_t *dlsch0_harq = dlsch[0]->harq_processes[dlsch_pdu->harq_pid];
dlsch0->rnti = dl_config->dl_config_list[i].dlsch_config_pdu.rnti;
dlsch0_harq->start_rb = dlsch_pdu->start_rb;
dlsch0_harq->nb_rb = dlsch_pdu->number_rbs;
dlsch0_harq->nb_symbols = dlsch_pdu->number_symbols;
dlsch0_harq->nb_symbols = dlsch_pdu->number_symbols;
dlsch0_harq->start_symbol = dlsch_pdu->start_symbol;
dlsch0->current_harq_pid = dlsch_pdu->harq_pid;
dlsch0->active = 1;
dlsch0_harq->mcs = dlsch_pdu->mcs;
dlsch0_harq->DCINdi = dlsch_pdu->ndi;
}
}
}else{
......
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
View file @ ebd07cb5
......@@ -54,9 +54,9 @@
#define DEBUG_PHY_PROC
#define NR_PDCCH_SCHED
#define NR_PDCCH_SCHED_DEBUG
#define NR_PUCCH_SCHED
#define NR_PUCCH_SCHED_DEBUG
//#define NR_PDCCH_SCHED_DEBUG
//#define NR_PUCCH_SCHED
//#define NR_PUCCH_SCHED_DEBUG
#ifndef PUCCH
#define PUCCH
......@@ -5522,28 +5522,28 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eN
LOG_D(PHY," ------ slot 0 Processing: AbsSubframe %d.%d ------ \n", frame_rx%1024, nr_tti_rx);
LOG_D(PHY," ------ --> FFT/ChannelEst/PDCCH slot 0: AbsSubframe %d.%d ------ \n", frame_rx%1024, nr_tti_rx);
nr_gold_pdcch(ue,0, 3);
for (; l<=3; l++) {
//nr_gold_pdcch(ue,0, 2);
/*
for (l=0; l<2; l++) {
if (abstraction_flag == 0) {
#if UE_TIMING_TRACE
start_meas(&ue->ofdm_demod_stats);
#endif
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SLOT_FEP, VCD_FUNCTION_IN);
nr_slot_fep(ue,
l,
(nr_tti_rx<<1),
0,
0,
nr_tti_rx,
0,
1,
1,
NR_PDCCH_EST);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SLOT_FEP, VCD_FUNCTION_OUT);
#if UE_TIMING_TRACE
stop_meas(&ue->ofdm_demod_stats);
#endif
}
}
}*/
//ue_measurement_procedures(l-1,ue,proc,eNB_id,(nr_tti_rx<<1),abstraction_flag,mode);
if (do_pdcch_flag) {
......@@ -5594,7 +5594,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eN
#endif
#endif
#if 0
LOG_D(PHY," ------ --> PDSCH ChannelComp/LLR slot 0: AbsSubframe %d.%d ------ \n", frame_rx%1024, nr_tti_rx);
//to update from pdsch config
nr_gold_pdsch(ue,0,0, 1);
......@@ -5933,6 +5933,8 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eN
#endif
#endif
#endif //pdsch
LOG_D(PHY," ****** end RX-Chain for AbsSubframe %d.%d ****** \n", frame_rx%1024, nr_tti_rx);
return (0);
}
......
openair2/LAYER2/NR_MAC_UE/mac_defs.h
View file @ ebd07cb5
......@@ -91,8 +91,6 @@ typedef struct {
fapi_nr_tx_request_t tx_request;
fapi_nr_ul_config_request_t ul_config_request;
fapi_nr_dl_config_request_t dl_config_request;
fapi_nr_dci_indication_t dci_indication;
fapi_nr_rx_indication_t rx_indication;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @ ebd07cb5
......@@ -475,9 +475,6 @@ NR_UE_L2_STATE_t nr_ue_scheduler(
search_space_mask = search_space_mask | type0_pdcch;
mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
}
//if((mac->type0_pdcch_ss_sfn_c == SFN_C_EQ_SFN_SSB) && ( get_ssb_frame() )){
// search_space_mask = search_space_mask | type0_pdcch;
//}
}
if(mac->type0_pdcch_ss_mux_pattern == 2){
// 38.213 Table 13-13, 13-14
......@@ -495,20 +492,8 @@ NR_UE_L2_STATE_t nr_ue_scheduler(
}
}
#if 0
uint16_t rnti;
fapi_nr_coreset_t coreset;
uint32_t duration;
uint8_t aggregation_level;
uint8_t number_of_candidates;
uint16_t monitoring_symbols_within_slot;
// DCI foramt-specific
uint8_t format_2_0_number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint8_t format_2_3_monitorying_periodicity;
uint8_t format_2_3_number_of_candidates;
#endif
fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
// Type0 PDCCH search space
if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){
mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1;
......@@ -582,7 +567,7 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fa
}
// UL_CONFIG_REQ
ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_PUSCH;
ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15;
ulsch_config_pdu->number_rbs = l_RB;
......@@ -590,6 +575,7 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fa
ulsch_config_pdu->number_symbols = sliv_L;
ulsch_config_pdu->start_symbol = sliv_S;
ulsch_config_pdu->mcs = dci->mcs;
//ulsch0->harq_processes[dci->harq_process_number]->first_rb = start_RB;
//ulsch0->harq_processes[dci->harq_process_number]->nb_rb = l_RB;
//ulsch0->harq_processes[dci->harq_process_number]->mcs = dci->mcs;
......@@ -637,14 +623,8 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fa
dlsch_config_pdu->number_symbols = sliv_L;
dlsch_config_pdu->start_symbol = sliv_S;
dlsch_config_pdu->mcs = dci->mcs;
//pdlsch0_harq->nb_rb = l_RB;
//pdlsch0->current_harq_pid = dci->harq_process_number;
//pdlsch0->active = 1;
//pdlsch0->rnti = rnti;
//pdlsch0_harq->mcs = nr_pdci_info_extracted->mcs;
//pdlsch0_harq->DCINdi = nr_pdci_info_extracted->ndi;
dlsch_config_pdu->ndi = dci->ndi;
dlsch_config_pdu->harq_pid = dci->harq_process_number;
dl_config->number_pdus = dl_config->number_pdus + 1;
break;
......
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
View file @ ebd07cb5
......@@ -72,6 +72,12 @@ int8_t nr_ue_ul_indication(nr_uplink_indication_t *ul_info){
module_id_t module_id = ul_info->module_id;
NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
// clean previous FAPI messages
mac->tx_request.number_of_pdus = 0;
mac->ul_config_request.number_pdus = 0;
mac->dl_config_request.number_pdus = 0;
// clean previous FAPI messages
ret = nr_ue_scheduler(
ul_info->module_id,
ul_info->gNB_index,
......
targets/RT/USER/nr-ue.c
View file @ ebd07cb5
......@@ -674,6 +674,12 @@ static void *UE_thread_rxn_txnp4(void *arg) {
(sf_type==SF_S ? "SF_S" : "UNKNOWN_SF_TYPE"))));
}
#endif
//clean previous FAPI MESSAGE
UE->rx_ind.number_pdus = 0;
UE->dci_ind.number_of_dcis = 0;
//clean previous FAPI MESSAGE
#ifdef UE_SLOT_PARALLELISATION
phy_procedures_slot_parallelization_UE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL );
#else
......@@ -892,13 +898,28 @@ void *UE_thread(void *arg) {
start_rx_stream=1;
if (UE->mode != loop_through_memory) {
if (UE->no_timing_correction==0) {
LOG_I(PHY,"Resynchronizing RX by %d samples (mode = %d)\n",UE->rx_offset,UE->mode);
printf("before resync\n");
//nr_slot_fep(UE,0, 0, UE->rx_offset, 1, 1, NR_PDCCH_EST);
//nr_slot_fep(UE,1, 0, UE->rx_offset, 1, 1, NR_PDCCH_EST);
//write_output("txdata_pre.m", "txdata_pre", UE->common_vars.rxdata[0], UE->frame_parms.samples_per_subframe*10, 1, 1);
/*LOG_I(PHY,"Resynchronizing RX by %d samples (mode = %d)\n",UE->rx_offset,UE->mode);
AssertFatal(UE->rx_offset ==
UE->rfdevice.trx_read_func(&UE->rfdevice,
&timestamp,
(void**)UE->common_vars.rxdata,
UE->rx_offset,
UE->frame_parms.nb_antennas_rx),"");
AssertFatal(UE->frame_parms.samples_per_subframe*10 ==
UE->rfdevice.trx_read_func(&UE->rfdevice,
&timestamp,
(void**)UE->common_vars.rxdata,
UE->frame_parms.samples_per_subframe*10,
UE->frame_parms.nb_antennas_rx),"");*/
//write_output("txdataF_ue.m", "txdataF_ue", UE->common_vars.rxdata[0], UE->frame_parms.samples_per_subframe*10, 1, 1);
}
UE->rx_offset=0;
UE->time_sync_cell=0;
......@@ -907,6 +928,8 @@ void *UE_thread(void *arg) {
for (th_id=0; th_id < RX_NB_TH; th_id++) {
UE->proc.proc_rxtx[th_id].frame_rx++;
}
//printf("first stream frame rx %d\n",UE->proc.proc_rxtx[0].frame_rx);
// read in first symbol
AssertFatal (UE->frame_parms.ofdm_symbol_size+UE->frame_parms.nb_prefix_samples0 ==
......@@ -915,7 +938,8 @@ void *UE_thread(void *arg) {
(void**)UE->common_vars.rxdata,
UE->frame_parms.ofdm_symbol_size+UE->frame_parms.nb_prefix_samples0,
UE->frame_parms.nb_antennas_rx),"");
nr_slot_fep(UE,0, 0, 0, 0, 0, NR_PBCH_EST);
//write_output("txdata_sym.m", "txdata_sym", UE->common_vars.rxdata[0], (UE->frame_parms.ofdm_symbol_size+UE->frame_parms.nb_prefix_samples0), 1, 1);
//nr_slot_fep(UE,0, 0, 0, 1, 1, NR_PDCCH_EST);
} //UE->mode != loop_through_memory
else
rt_sleep_ns(1000*1000);
......@@ -967,7 +991,7 @@ void *UE_thread(void *arg) {
UE->rx_offset_diff;
}
AssertFatal(readBlockSize ==
/*AssertFatal(readBlockSize ==
UE->rfdevice.trx_read_func(&UE->rfdevice,
&timestamp,
rxp,
......@@ -982,17 +1006,17 @@ void *UE_thread(void *arg) {
txp,
writeBlockSize,
UE->frame_parms.nb_antennas_tx,
1),"");
1),"");*/
if( tti_nr==(ttis_per_frame-1)) {
// read in first symbol of next frame and adjust for timing drift
int first_symbols=writeBlockSize-readBlockSize;
if ( first_symbols > 0 )
AssertFatal(first_symbols ==
/*AssertFatal(first_symbols ==
UE->rfdevice.trx_read_func(&UE->rfdevice,
&timestamp1,
(void**)UE->common_vars.rxdata,
first_symbols,
UE->frame_parms.nb_antennas_rx),"");
UE->frame_parms.nb_antennas_rx),"");*/
if ( first_symbols <0 )
LOG_E(PHY,"can't compensate: diff =%d\n", first_symbols);
}
......
targets/RT/USER/nr-uesoftmodem.c
View file @ ebd07cb5
......@@ -1238,7 +1238,7 @@ int main( int argc, char **argv ) {
//}
// connect the TX/RX buffers
if (UE_flag==1) {
//if (UE_flag==1) {
for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
......@@ -1265,7 +1265,7 @@ int main( int argc, char **argv ) {
printf("error reading from file\n");
}
//p_exmimo_config->framing.tdd_config = TXRXSWITCH_TESTRX;
}
//}
sleep(3);
......
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