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Commit f5250c1e authored by Ejaz Ahmed's avatar Ejaz Ahmed
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Added but commented out due to issue with slsch reception

parent 156b806a
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Showing with 218 additions and 181 deletions
executables/nr-ue.c
View file @ f5250c1e
......@@ -625,6 +625,12 @@ void processSlotTX(void *arg) {
if (proc->tx_slot_type == NR_SIDELINK_SLOT && UE->sl_mode == 2) {
// wait for rx slots to send indication (if any) that SLSCH decoding is finished
// for(int i=0; i < rxtxD->tx_wait_for_slsch; i++) {
// LOG_I(NR_PHY, "EJJ: tx slot: %d, rxtxD->tx_wait_for_slsch: %d pullNotifiedFIFO\n", proc->nr_slot_tx, rxtxD->tx_wait_for_slsch);
// notifiedFIFO_elt_t *res = pullNotifiedFIFO(UE->tx_resume_ind_fifo[proc->nr_slot_tx]);
// delNotifiedFIFO_elt(res);
// }
// trigger L2 to run ue_scheduler thru IF module
if(UE->if_inst != NULL && UE->if_inst->sl_indication != NULL) {
start_meas(&UE->ue_ul_indication_stats);
......@@ -642,6 +648,7 @@ void processSlotTX(void *arg) {
sl_indication.slot_type = SIDELINK_SLOT_TYPE_TX;
LOG_D(NR_PHY,"Sending SL indication RX %d.%d TX %d.%d\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
UE->if_inst->sl_indication(&sl_indication);
stop_meas(&UE->ue_ul_indication_stats);
......@@ -719,10 +726,24 @@ nr_phy_data_t UE_dl_preprocessing(PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc)
if(UE->if_inst != NULL && UE->if_inst->sl_indication != NULL) {
nr_sidelink_indication_t sl_indication;
nr_fill_sl_indication(&sl_indication, NULL, NULL, proc, UE, &phy_data);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
UE->if_inst->sl_indication(&sl_indication);
}
uint64_t a=rdtsc_oai();
psbch_pscch_pssch_processing(UE, proc, &phy_data);
// if (phy_data.sl_active) {
// LOG_I(NR_PHY, "%s sl_active: %d\n", __FUNCTION__, phy_data.sl_active);
// // indicate to tx thread to wait for DLSCH decoding
// sl_nr_phy_config_request_t *sl_cfg = NULL;
// sl_cfg = &UE->SL_UE_PHY_PARAMS.sl_config;
// uint8_t psfch_period = sl_cfg->psfch_period;
// uint8_t psfch_min_time_gap = sl_cfg->time_gap;
// int delta_slots = (proc->nr_slot_rx + psfch_min_time_gap) % psfch_period ? psfch_period - (proc->nr_slot_rx + psfch_min_time_gap) % psfch_period: 0;
// uint8_t feedback_slot = proc->nr_slot_rx + psfch_min_time_gap + delta_slots;
// feedback_slot %= NR_MAX_SLOTS_PER_FRAME;
// UE->tx_wait_for_slsch[feedback_slot]++;
// phy_data.sl_active = false;
// }
LOG_D(PHY, "In %s: slot %d:%d, time %llu\n", __FUNCTION__, proc->frame_rx, proc->nr_slot_rx, (rdtsc_oai()-a)/3500);
}
} else {
......@@ -917,6 +938,7 @@ void *UE_thread(void *arg)
int num_ind_fifo = nb_slot_frame;
for(int i=0; i < num_ind_fifo; i++) {
UE->tx_wait_for_dlsch[num_ind_fifo] = 0;
//UE->tx_wait_for_slsch[num_ind_fifo] = 0;
UE->tx_resume_ind_fifo[i] = malloc(sizeof(*UE->tx_resume_ind_fifo[i]));
initNotifiedFIFO(UE->tx_resume_ind_fifo[i]);
}
......@@ -1085,8 +1107,13 @@ void *UE_thread(void *arg)
curMsgTx->writeBlockSize = writeBlockSize;
curMsgTx->proc.timestamp_tx = writeTimestamp;
curMsgTx->UE = UE;
curMsgTx->tx_wait_for_dlsch = UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx];
UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx] = 0;
// if (UE->tx_wait_for_slsch[curMsgTx->proc.nr_slot_tx] > 0) {
// curMsgTx->tx_wait_for_slsch = UE->tx_wait_for_slsch[curMsgTx->proc.nr_slot_tx];
// UE->tx_wait_for_slsch[curMsgTx->proc.nr_slot_tx] = 0;
// } else {
curMsgTx->tx_wait_for_dlsch = UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx];
UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx] = 0;
//}
pushTpool(&(get_nrUE_params()->Tpool), newElt);
// RX slot processing. We launch and forget.
......
nfapi/open-nFAPI/nfapi/public_inc/sidelink_nr_ue_interface.h
View file @ f5250c1e
......@@ -303,6 +303,7 @@ typedef struct sl_nr_tx_config_psfch_pdu {
uint8_t prb;
uint16_t initial_cyclic_shift;
uint8_t mcs;
uint8_t bit_len_harq;
uint8_t psfch_payload;
} sl_nr_tx_config_psfch_pdu_t;
......@@ -319,7 +320,6 @@ typedef struct sl_nr_rx_config_psfch_pdu {
uint16_t initial_cyclic_shift;
uint8_t mcs;
uint8_t psfch_payload;
} sl_nr_rx_config_psfch_pdu_t;
// MAC commands PHY to perform an action on TX RESOURCE POOL or TX PSBCH using this TX CONFIG
......@@ -407,6 +407,7 @@ typedef struct
} sl_nr_carrier_config_t;
typedef struct {
// Mask indicating which of the below configs are changed
// Bit0 - carrier_config, Bit1 - syncsource cfg
......@@ -422,6 +423,10 @@ typedef struct {
sl_nr_bwp_config_t sl_bwp_config;
uint32_t sl_DMRS_ScrambleId;
// PSFCH related configuration to find feedback slot
uint8_t time_gap;
uint8_t psfch_period;
} sl_nr_phy_config_request_t;
......
openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c
View file @ f5250c1e
......@@ -2260,7 +2260,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB,
pssch_pdu->sci2_len,
sci2_re);
// send SCI indication with SCI2 payload and get SLSCH information if CRC is OK
LOG_D(NR_PHY,"SCI indication (crc %x)\n",crc);
LOG_I(NR_PHY,"SCI indication (crc %x)\n",crc);
if (crc==0) ue->SL_UE_PHY_PARAMS.pssch.rx_sci2_ok++;
else ue->SL_UE_PHY_PARAMS.pssch.rx_sci2_errors++;
sl_nr_sci_indication_t sci_ind={0};
......@@ -2277,9 +2277,10 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB,
memcpy(sci_ind.sci_pdu[sci_ind.number_of_SCIs].sci_payloadBits,&sci_estimation,8);
sci_ind.number_of_SCIs++;
nr_sidelink_indication_t sl_indication;
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
nr_fill_sl_indication(&sl_indication, NULL, &sci_ind, proc, ue, phy_data);
ue->if_inst->sl_indication(&sl_indication);
LOG_D(NR_PHY,"Returning from SCI2 SL indication\n");
LOG_I(NR_PHY,"Returning from SCI2 SL indication\n");
//
}
} // (not ML || nrOfLayers==1 ) AND pssch and sci2 REs to handle
......
openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync_sl.c
View file @ f5250c1e
......@@ -575,7 +575,7 @@ int sl_nr_slss_search(PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc, int num_frame
LOG_D(PHY,"Sidelink SLSS SEARCH PSBCH RX OK. Send SL-SSB TO MAC\n");
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
if (UE->if_inst && UE->if_inst->sl_indication)
UE->if_inst->sl_indication(&sl_indication);
......
openair1/PHY/NR_UE_TRANSPORT/nr_psfch_tx.c
View file @ f5250c1e
......@@ -61,5 +61,6 @@ void nr_generate_psfch0(const PHY_VARS_NR_UE *ue,
pucch_pdu.mcs = psfch_pdu->mcs;
pucch_pdu.nr_of_symbols = psfch_pdu->nr_of_symbols;
pucch_pdu.payload = psfch_pdu->psfch_payload;
pucch_pdu.n_bit = psfch_pdu->bit_len_harq;
nr_generate_pucch0(ue,txdataF,frame_parms,amp,nr_slot_tx,&pucch_pdu);
}
openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c
View file @ f5250c1e
......@@ -111,13 +111,6 @@ void nr_generate_pucch0(const PHY_VARS_NR_UE *ue,
nr_group_sequence_hopping(pucch_GroupHopping,pucch_pdu->hopping_id,1,nr_slot_tx,&u[1],&v[1]); // calculating u and v value
prb_offset[1] = pucch_pdu->second_hop_prb + pucch_pdu->bwp_start;
}
LOG_D(PHY, "prb_start %d\n", pucch_pdu->prb_start);
LOG_D(PHY,"nr_of_symbols %d\n", pucch_pdu->nr_of_symbols);
LOG_D(PHY,"hopping_id %d\n", pucch_pdu->hopping_id);
LOG_D(PHY,"initial_cyclic_shift %d\n", pucch_pdu->initial_cyclic_shift);
LOG_D(PHY,"mcs %d\n", pucch_pdu->mcs);
LOG_D(PHY,"start_sym_index %d\n", pucch_pdu->start_symbol_index);
LOG_D(PHY,"nr_slot_tx %d\n", nr_slot_tx);
for (int l=0; l<pucch_pdu->nr_of_symbols; l++) {
alpha = nr_cyclic_shift_hopping(pucch_pdu->hopping_id,
pucch_pdu->initial_cyclic_shift,
......@@ -161,7 +154,6 @@ void nr_generate_pucch0(const PHY_VARS_NR_UE *ue,
txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset].r = (int16_t)(((int32_t)(amp) * x_n_re[l][n])>>15);
txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset].i = (int16_t)(((int32_t)(amp) * x_n_im[l][n])>>15);
LOG_I(NR_PHY, "re %x, i %x\n", txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset].r, txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset].i);
//((int16_t *)txptr[0][re_offset])[0] = (int16_t)((int32_t)amp * x_n_re[(12*l)+n])>>15;
//((int16_t *)txptr[0][re_offset])[1] = (int16_t)((int32_t)amp * x_n_im[(12*l)+n])>>15;
//txptr[re_offset] = (x_n_re[(12*l)+n]<<16) + x_n_im[(12*l)+n];
......
openair1/PHY/defs_nr_UE.h
View file @ f5250c1e
......@@ -223,16 +223,6 @@ typedef struct {
typedef struct {
int max_nb_pucch;
/// \brief Pointers (dynamic) to the received data in the frequency domain.
/// - first index: rx antenna [0..nb_antennas_rx[
/// - second index: ? [0..2*ofdm_symbol_size*frame_parms->symbols_per_tti[
c16_t **rxdataF;
/// \brief holds the transmit data in the frequency domain.
/// For IFFT_FPGA this points to the same memory as PHY_vars->rx_vars[a].RX_DMA_BUFFER. //?
/// - first index: eNB id [0..2] (hard coded)
/// - second index: tx antenna [0..14[ where 14 is the total supported antenna ports.
/// - third index: sample [0..samples_per_frame_woCP]
c16_t **txdataF;
/// \brief Holds the transmit data in time domain.
/// For IFFT_FPGA this points to the same memory as PHY_vars->tx_vars[a].TX_DMA_BUFFER.
/// - first index: tx antenna [0..nb_antennas_tx[
......@@ -664,6 +654,7 @@ typedef struct PHY_VARS_NR_UE_s {
notifiedFIFO_t phy_config_ind;
notifiedFIFO_t *tx_resume_ind_fifo[NR_MAX_SLOTS_PER_FRAME];
int tx_wait_for_dlsch[NR_MAX_SLOTS_PER_FRAME];
//int tx_wait_for_slsch[NR_MAX_SLOTS_PER_FRAME];
//Sidelink parameters
sl_nr_sidelink_mode_t sl_mode;
......@@ -714,13 +705,14 @@ typedef struct nr_phy_data_tx_s {
typedef struct nr_phy_data_s {
NR_UE_PDCCH_CONFIG phy_pdcch_config;
NR_UE_DLSCH_t dlsch[2];
bool sl_active;
//Sidelink Rx action decided by MAC
sl_nr_rx_config_type_enum_t sl_rx_action;
sl_nr_rx_config_pscch_pdu_t nr_sl_pscch_pdu;
sl_nr_rx_config_pssch_sci_pdu_t nr_sl_pssch_sci_pdu;
sl_nr_rx_config_pssch_pdu_t nr_sl_pssch_pdu;
sl_nr_rx_config_psfch_pdu_t nr_sl_psfch_pdu;
//sl_nr_rx_config_psfch_pdu_t nr_sl_psfch_pdu;
} nr_phy_data_t;
/* this structure is used to pass both UE phy vars and
* proc to the function UE_thread_rxn_txnp4
......@@ -732,6 +724,7 @@ typedef struct nr_rxtx_thread_data_s {
notifiedFIFO_t txFifo;
nr_phy_data_t phy_data;
int tx_wait_for_dlsch;
//int tx_wait_for_slsch;
} nr_rxtx_thread_data_t;
typedef struct LDPCDecode_ue_s {
......
openair1/PHY/defs_nr_sl_UE.h
View file @ f5250c1e
......@@ -184,9 +184,6 @@ typedef struct SL_NR_UE_PSBCH {
} SL_NR_UE_PSBCH_t;
typedef struct SL_NR_UE_PSFCH {
// STATS - Receptions with CRC OK
uint16_t rx_ok;
// STATS - transmissions of PSFCH by the UE
uint16_t num_psfch_tx;
......
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
View file @ f5250c1e
......@@ -760,9 +760,9 @@ int8_t sl_handle_scheduled_response(nr_scheduled_response_t *scheduled_response)
phy_data_tx->nr_sl_pssch_pscch_pdu.tbslbrm);
break;
case SL_NR_CONFIG_TYPE_TX_PSFCH:
LOG_I(PHY, "Recvd CONFIG_TYPE_TX_PSFCH\n");
phy_data_tx->sl_tx_action = SL_NR_CONFIG_TYPE_TX_PSFCH;
phy_data_tx->nr_sl_psfch_pdu = sl_tx_config->tx_config_list[0].tx_psfch_config_pdu;
LOG_I(NR_PHY, "Recvd CONFIG_TYPE_TX_PSFCH\n");
//phy_data_tx->sl_tx_action = SL_NR_CONFIG_TYPE_TX_PSFCH;
//phy_data_tx->nr_sl_psfch_pdu = sl_tx_config->tx_config_list[0].tx_psfch_config_pdu;
break;
default:
AssertFatal(0,"Incorrect sl_tx config req pdutype \n");
......
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
View file @ f5250c1e
......@@ -494,6 +494,7 @@ int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue,
sci_ind.number_of_SCIs = dci_cnt;
// fill sl_indication message
nr_fill_sl_indication(&sl_indication, NULL, &sci_ind, proc, ue, phy_data);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
// send to mac
ue->if_inst->sl_indication(&sl_indication);
}
......
openair1/SCHED_NR_UE/phy_procedures_nr_ue_sl.c
View file @ f5250c1e
......@@ -92,7 +92,6 @@ void nr_fill_sl_rx_indication(sl_nr_rx_indication_t *rx_ind,
rx_slsch_pdu->pdu_length = slsch_status->rdata->ulsch_harq->TBS;
rx_slsch_pdu->harq_pid = slsch_status->rdata->harq_pid;
rx_slsch_pdu->ack_nack = (slsch_status->rxok==true) ? 1 : 0;
if (slsch_status->rxok==true) ue->SL_UE_PHY_PARAMS.pssch.rx_ok++;
else ue->SL_UE_PHY_PARAMS.pssch.rx_errors[0]++;
}
......@@ -219,6 +218,18 @@ int nr_slsch_procedures(PHY_VARS_NR_UE *ue, int frame_rx, int slot_rx, int SLSCH
int nbDecode =
nr_ulsch_decoding(NULL, ue, SLSCH_id, ue->pssch_vars[SLSCH_id].llr, fp, &pusch_pdu, frame_rx, slot_rx, harq_pid, G,proc,phy_data);
// sl_nr_phy_config_request_t *sl_cfg = NULL;
// sl_cfg = &ue->SL_UE_PHY_PARAMS.sl_config;
// uint8_t psfch_period = sl_cfg->psfch_period;
// uint8_t psfch_min_time_gap = sl_cfg->time_gap;
// int delta_slots = (slot_rx + psfch_min_time_gap) % psfch_period ? psfch_period - (slot_rx + psfch_min_time_gap) % psfch_period: 0;
// uint8_t feedback_slot = slot_rx + psfch_min_time_gap + delta_slots;
// feedback_slot %= NR_MAX_SLOTS_PER_FRAME;
// phy_data->sl_active = true;
// send_slot_ind(ue->tx_resume_ind_fifo[feedback_slot], slot_rx);
// LOG_I(NR_PHY, "%s EJJ: Sent slot indication: slot_rx %d feedback_slot %d, sl_active %d\n", __FUNCTION__, slot_rx, feedback_slot, phy_data->sl_active);
// LOG_I(NR_MAC, "harq pid: %d psfch_period %d, slot_rx %d, delta_slots %d, feedback_slot %d, time_gap %d\n", harq_pid, psfch_period, slot_rx, delta_slots, feedback_slot, psfch_min_time_gap);
return nbDecode;
}
......@@ -268,7 +279,7 @@ void nr_postDecode_slsch(PHY_VARS_NR_UE *UE, notifiedFIFO_elt_t *req,UE_nr_rxtx_
slsch_status.rxok = true;
//dumpsig=1;
} else {
LOG_I(NR_PHY,
LOG_D(NR_PHY,
"[UE] SLSCH: Setting NAK for SFN/SF %d/%d (pid %d, ndi %d, status %d, round %d, RV %d, prb_start %d, prb_size %d, "
"TBS %d) r %d\n",
slsch->frame,
......@@ -289,11 +300,11 @@ void nr_postDecode_slsch(PHY_VARS_NR_UE *UE, notifiedFIFO_elt_t *req,UE_nr_rxtx_
// dumpsig=1;
}
slsch->last_iteration_cnt = rdata->decodeIterations;
sl_rx_indication.sfn = proc->frame_rx;
sl_rx_indication.slot = proc->nr_slot_rx;
// sl_rx_indication.sfn = proc->frame_rx;
// sl_rx_indication.slot = proc->nr_slot_rx;
nr_fill_sl_rx_indication(&sl_rx_indication,SL_NR_RX_PDU_TYPE_SLSCH,UE,1,proc,(void*)&slsch_status,0);
nr_fill_sl_indication(&sl_indication,&sl_rx_indication,NULL,proc,UE,phy_data);
LOG_D(NR_PHY, "sl_ind frame %d, slot %d\n", sl_indication.rx_ind->sfn, sl_indication.rx_ind->slot);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
if (UE->if_inst && UE->if_inst->sl_indication)
UE->if_inst->sl_indication(&sl_indication);
/*
......@@ -384,7 +395,7 @@ static int nr_ue_psbch_procedures(PHY_VARS_NR_UE *ue,
nr_fill_sl_indication(&sl_indication, &rx_ind, NULL, proc, ue, phy_data);
nr_fill_sl_rx_indication(&rx_ind, SL_NR_RX_PDU_TYPE_SSB, ue, number_pdus, proc, (void *)result, rx_slss_id);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
if (ue->if_inst && ue->if_inst->sl_indication)
ue->if_inst->sl_indication(&sl_indication);
......@@ -726,7 +737,6 @@ int phy_procedures_nrUE_SL_TX(PHY_VARS_NR_UE *ue,
}
else if (phy_data->sl_tx_action == SL_NR_CONFIG_TYPE_TX_PSFCH) {
LOG_I(NR_PHY,"Generating PSFCH ( )\n");
nr_generate_psfch0(ue,
txdataF,
fp,
......@@ -735,9 +745,9 @@ int phy_procedures_nrUE_SL_TX(PHY_VARS_NR_UE *ue,
&phy_data->nr_sl_psfch_pdu);
sl_phy_params->psfch.num_psfch_tx ++;
tx_action = 1;
LOG_I(NR_PHY, "Sending SL data frame %d slot %d\n", frame_tx, slot_tx);
}
if (tx_action) {
LOG_D(PHY, "Sending SL data frame %d slot %d\n", frame_tx, slot_tx);
nr_ue_pusch_common_procedures(ue,
proc->nr_slot_tx,
fp,
......
openair1/SCHED_NR_UE/pucch_uci_ue_nr.c
View file @ f5250c1e
......@@ -230,7 +230,7 @@ void pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, n
tx_amp = AMP;
LOG_D(PHY,"Generation of PUCCH format %d at frame.slot %d.%d\n",pucch_pdu->format_type,proc->frame_tx,nr_slot_tx);
LOG_I(PHY,"Generation of PUCCH format %d at frame.slot %d.%d\n",pucch_pdu->format_type,proc->frame_tx,nr_slot_tx);
switch(pucch_pdu->format_type) {
case 0:
......
openair2/LAYER2/NR_MAC_UE/config_ue_sl.c
View file @ f5250c1e
......@@ -457,6 +457,13 @@ int nr_rrc_mac_config_req_sl_preconfig(module_id_t module_id,
nr_sl_phy_config_t *sl_phy_cfg = &sl_mac->sl_phy_config;
sl_phy_cfg->Mod_id = module_id;
sl_phy_cfg->CC_id = 0;
const uint8_t psfch_periods[] = {0,1,2,4};
const uint8_t time_gaps[] = {2, 3};
NR_SL_PSFCH_Config_r16_t *psfch_config = mac->sl_tx_res_pool->sl_PSFCH_Config_r16->choice.setup;
uint8_t psfch_period_index = *psfch_config->sl_PSFCH_Period_r16;
uint8_t psfch_time_gap_indx = *psfch_config->sl_MinTimeGapPSFCH_r16;
sl_phy_cfg->sl_config_req.psfch_period = psfch_periods[psfch_period_index];
sl_phy_cfg->sl_config_req.time_gap = time_gaps[psfch_time_gap_indx];
sl_prepare_phy_config(module_id, &sl_phy_cfg->sl_config_req,
freqcfg, sync_source, sl_OffsetDFN, sl_mac->sl_TDD_config);
......
openair2/LAYER2/NR_MAC_UE/mac_defs.h
View file @ f5250c1e
......@@ -454,6 +454,7 @@ typedef struct {
uint8_t round;
uint16_t feedback_slot;
uint16_t feedback_frame;
int8_t sl_harq_pid;
/// sched_pusch keeps information on MCS etc used for the initial transmission
NR_sched_pssch_t sched_pssch;
......@@ -602,7 +603,7 @@ typedef struct {
NR_SSB_meas_t ssb_measurements;
dci_pdu_rel15_t def_dci_pdu_rel15[NR_MAX_SLOTS_PER_FRAME][8];
sl_nr_tx_config_psfch_pdu_t *sl_tx_config_psfch_pdu;
sl_nr_tx_config_psfch_pdu_t *sl_tx_config_psfch_pdu[NR_MAX_HARQ_PROCESSES];
// Defined for abstracted mode
nr_downlink_indication_t dl_info;
......
openair2/LAYER2/NR_MAC_UE/mac_proto.h
View file @ f5250c1e
......@@ -498,6 +498,7 @@ bool nr_schedule_slsch(NR_UE_MAC_INST_t *mac, int frameP, int slotP, nr_sci_pdu_
uint8_t *slsch_pdu,
nr_sci_format_t format2,
uint16_t *slsch_pdu_length);
void config_psfch_pdu_rx(NR_UE_MAC_INST_t *mac,
sl_nr_rx_config_psfch_pdu_t *nr_sl_psfch_pdu,
const NR_SL_BWP_Generic_r16_t *sl_bwp,
......
openair2/LAYER2/NR_MAC_UE/nr_slsch_scheduler.c
View file @ f5250c1e
......@@ -64,13 +64,13 @@ bool nr_schedule_slsch(NR_UE_MAC_INST_t *mac, int frameP,int slotP, nr_sci_pdu_t
sci_pdu->beta_offset_indicator = 0;
// Fill SCI2A
sci2_pdu->harq_pid = 0;
sci2_pdu->harq_pid = 0; // slotP FIXIT - The value should only be 0-15 which can be in 4-bits
sci2_pdu->ndi = (1-sci2_pdu->ndi)&1;
sci2_pdu->rv_index=0;
sci2_pdu->source_id=0x12;
sci2_pdu->dest_id=0xabcd;
sci2_pdu->harq_feedback=1;
sci2_pdu->cast_type=2;
sci2_pdu->cast_type=0;
if (format2==NR_SL_SCI_FORMAT_2C || format2==NR_SL_SCI_FORMAT_2A)
sci2_pdu->csi_req=1;
if (format2==NR_SL_SCI_FORMAT_2B)
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures_sl.c
View file @ f5250c1e
......@@ -599,7 +599,7 @@ uint8_t count_PSFCH_PRBs_bits(uint8_t* buf, size_t size) {
return count;
}
static uint16_t nr_ue_configure_psfch(int module_idP) {
static uint16_t compute_m0(int module_idP) {
NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP);
if (!mac->sl_tx_res_pool->sl_PSFCH_Config_r16 &&
mac->sl_tx_res_pool->sl_PSFCH_Config_r16->present != NR_SetupRelease_SL_PSFCH_Config_r16_PR_setup)
......@@ -611,16 +611,19 @@ static uint16_t nr_ue_configure_psfch(int module_idP) {
LOG_D(NR_MAC, "source id %d, module_idP %d\n", sci2_src_id, module_idP);
uint8_t *rb_buf = sl_psfch_config->sl_PSFCH_RB_Set_r16->buf;
size_t size = sl_psfch_config->sl_PSFCH_RB_Set_r16->size / sizeof(rb_buf[0]);
LOG_D(NR_MAC, "size %d, buff_size %d, element size %d\n", size, sl_psfch_config->sl_PSFCH_RB_Set_r16->size, sizeof(rb_buf[0]));
uint8_t m_psfch_prb_set = count_PSFCH_PRBs_bits(rb_buf, size);
long sl_numsubchannel = *mac->sl_tx_res_pool->sl_NumSubchannel_r16;
long sl_psfch_period = *sl_psfch_config->sl_PSFCH_Period_r16;
const uint8_t psfch_periods[] = {0,1,2,4};
long psfch_period = (sl_psfch_config->sl_PSFCH_Period_r16)
? psfch_periods[*sl_psfch_config->sl_PSFCH_Period_r16] : 0;
long n_psfch_cs = *sl_psfch_config->sl_NumMuxCS_Pair_r16;
double m_psfch_subch_slot = m_psfch_prb_set / sl_numsubchannel * sl_psfch_period;
double m_psfch_subch_slot = m_psfch_prb_set / sl_numsubchannel * psfch_period;
long n_psfch_type = *sl_psfch_config->sl_PSFCH_CandidateResourceType_r16 ? sl_numsubchannel : 1;
uint16_t r_psfch_prb_cs = n_psfch_type * m_psfch_subch_slot * sl_num_muxcs_pair[n_psfch_cs];
uint8_t psfch_rsc_idx = (sci2_src_id + module_idP) / r_psfch_prb_cs;
LOG_D(NR_MAC, "size %d, m_psfch_prb_set %d, sl_numsubchannel %d, sl_psfch_period %d, n_psfch_cs %d\n", size, m_psfch_prb_set, sl_numsubchannel, sl_psfch_period, n_psfch_cs);
LOG_D(NR_MAC, "size %d, m_psfch_prb_set %d, sl_numsubchannel %d, sl_psfch_period %d, n_psfch_cs %d\n", size, m_psfch_prb_set, sl_numsubchannel, psfch_period, n_psfch_cs);
LOG_D(NR_MAC, "m_psfch_subch_slot %f, n_psfch_type %d, r_psfch_prb_cs %d, psfch_rsc_idx %d\n", m_psfch_subch_slot, n_psfch_type, r_psfch_prb_cs, psfch_rsc_idx);
return table_16_3_1[n_psfch_cs][psfch_rsc_idx];
}
......@@ -647,15 +650,18 @@ void nr_ue_process_mac_sl_pdu(int module_idP,
const uint8_t time_gap[] = {2, 3};
uint8_t psfch_min_time_gap = time_gap[*sl_psfch_config->sl_MinTimeGapPSFCH_r16];
uint8_t harq_pid = (rx_ind->rx_indication_body + pdu_id)->rx_slsch_pdu.harq_pid;
mac->sl_info.list[0] = calloc(1, sizeof(NR_SL_UE_info_t));
harq_proc = &mac->sl_info.list[0]->UE_sched_ctrl.sl_harq_processes[harq_pid];
mac->sl_info.list[0]->dest_id = mac->sci_pdu_rx.source_id;
mac->sl_info.list[0]->uid = module_idP;
long psfch_period = *sl_psfch_config->sl_PSFCH_Period_r16;
// mac->sl_info.list[0]->dest_id = mac->sci_pdu_rx.source_id;
// mac->sl_info.list[0]->uid = module_idP;
const uint8_t psfch_periods[] = {0,1,2,4};
long psfch_period = (sl_psfch_config->sl_PSFCH_Period_r16)
? psfch_periods[*sl_psfch_config->sl_PSFCH_Period_r16] : 0;
int delta_slots = (slot + psfch_min_time_gap) % psfch_period ? psfch_period - (slot + psfch_min_time_gap) % psfch_period: 0;
sched_slot = slot + psfch_min_time_gap + delta_slots;
LOG_D(NR_MAC, "psfch_period %d, slot %d, delta_slots %d, sched_slot %d, time_gap %d\n", psfch_period, slot, delta_slots, sched_slot, psfch_min_time_gap);
sched_frame = frame;
LOG_I(NR_MAC, "harq pid: %d psfch_period %d, slot %d, delta_slots %d, sched_slot %d, time_gap %d\n", harq_pid, psfch_period, slot, delta_slots, sched_slot, psfch_min_time_gap);
if (sched_slot >= NR_MAX_SLOTS_PER_FRAME) {
sched_slot %= NR_MAX_SLOTS_PER_FRAME;
sched_frame = (sched_frame + 1) %1024;
......@@ -664,35 +670,32 @@ void nr_ue_process_mac_sl_pdu(int module_idP,
harq_proc->feedback_slot = sched_slot;
harq_proc->feedback_frame = sched_frame;
harq_proc->is_active = true;
LOG_D(NR_MAC, "feedback_slot %d, feedback_frame %d, slot %d, frame %d\n", harq_proc->feedback_slot, harq_proc->feedback_frame, slot, frame);
LOG_I(NR_MAC, "feedback_slot %d, feedback_frame %d, slot %d, frame %d\n", harq_proc->feedback_slot, harq_proc->feedback_frame, slot, frame);
uint8_t ack_nack = (rx_ind->rx_indication_body + pdu_id)->rx_slsch_pdu.ack_nack;
uint16_t m0 = nr_ue_configure_psfch(module_idP);
LOG_I(NR_MAC, "EJAZ:: m0\n", m0);
mac->sl_tx_config_psfch_pdu = calloc(1, sizeof(sl_nr_tx_config_psfch_pdu_t));
mac->sl_tx_config_psfch_pdu->initial_cyclic_shift = m0;
mac->sl_tx_config_psfch_pdu[harq_pid] = calloc(1, sizeof(sl_nr_tx_config_psfch_pdu_t));
uint16_t m0 = compute_m0(module_idP);
mac->sl_tx_config_psfch_pdu[harq_pid]->initial_cyclic_shift = m0;
if (mac->sci1_pdu.second_stage_sci_format == 2 ||
mac->sci_pdu_rx.cast_type == 1 ||
mac->sci_pdu_rx.cast_type == 2) {
mac->sl_tx_config_psfch_pdu->mcs = sequence_cyclic_shift_harq_ack_or_ack_or_only_nack[ack_nack];
mac->sl_tx_config_psfch_pdu[harq_pid]->mcs = sequence_cyclic_shift_harq_ack_or_ack_or_only_nack[ack_nack];
} else if (mac->sci1_pdu.second_stage_sci_format == 1 ||
(mac->sci1_pdu.second_stage_sci_format == 1 && mac->sci_pdu_rx.cast_type == 3)) {
mac->sl_tx_config_psfch_pdu->mcs = sequence_cyclic_shift_harq_ack_or_ack_or_only_nack[0];
mac->sl_tx_config_psfch_pdu[harq_pid]->mcs = sequence_cyclic_shift_harq_ack_or_ack_or_only_nack[0];
}
const uint8_t values[] = {7, 8, 9, 10, 11, 12, 13, 14};
NR_SL_BWP_Generic_r16_t *sl_bwp = mac->sl_bwp->sl_BWP_Generic_r16;
uint8_t sl_num_symbols = *sl_bwp->sl_LengthSymbols_r16 ?
values[*sl_bwp->sl_LengthSymbols_r16] : 0;
mac->sl_tx_config_psfch_pdu->start_symbol_index = *sl_bwp->sl_StartSymbol_r16 + sl_num_symbols - 2; // start_symbol_index has been used as lprime and lprime should be computed as lprime = start symbol + sl_LengthSymbols_r16 - 2
mac->sl_tx_config_psfch_pdu->hopping_id = *mac->sl_bwp->sl_BWP_PoolConfigCommon_r16->sl_TxPoolSelectedNormal_r16->list.array[0]->sl_ResourcePool_r16->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_HopID_r16;
mac->sl_tx_config_psfch_pdu->prb = 1;
mac->sl_tx_config_psfch_pdu->psfch_payload = 1;
LOG_D(NR_MAC,"Filled psfch pdu %d\n", module_idP);
LOG_D(NR_MAC,"pucch_pdu->hopping_id %d\n", mac->sl_tx_config_psfch_pdu->hopping_id);
LOG_D(NR_MAC,"pucch_pdu->initial_cyclic_shift %d\n", mac->sl_tx_config_psfch_pdu->initial_cyclic_shift);
LOG_D(NR_MAC,"pucch_pdu->mcs %d\n", mac->sl_tx_config_psfch_pdu->mcs);
LOG_D(NR_MAC,"start_sym_index %d\n", mac->sl_tx_config_psfch_pdu->start_symbol_index);
values[*sl_bwp->sl_LengthSymbols_r16] : 0;
mac->sl_tx_config_psfch_pdu[harq_pid]->start_symbol_index = *sl_bwp->sl_StartSymbol_r16 + sl_num_symbols - 2; // start_symbol_index has been used as lprime and lprime should be computed as lprime = start symbol + sl_LengthSymbols_r16 - 2
mac->sl_tx_config_psfch_pdu[harq_pid]->hopping_id = *mac->sl_bwp->sl_BWP_PoolConfigCommon_r16->sl_TxPoolSelectedNormal_r16->list.array[0]->sl_ResourcePool_r16->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_HopID_r16;
mac->sl_tx_config_psfch_pdu[harq_pid]->prb = 1;
mac->sl_tx_config_psfch_pdu[harq_pid]->psfch_payload = 1;
mac->sl_tx_config_psfch_pdu[harq_pid]->bit_len_harq = 1;
LOG_D(NR_MAC,"Filled psfch pdu\n");
//nr_ue_sidelink_scheduler(nr_sidelink_indication_t *sl_ind);
if ((rx_ind->rx_indication_body + pdu_id)->rx_slsch_pdu.ack_nack == 0)
return;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
View file @ f5250c1e
......@@ -3385,22 +3385,22 @@ bool nr_ue_sl_pssch_scheduler(NR_UE_MAC_INST_t *mac,
}
return true;
}
void nr_ue_sl_psfch_rx_scheduler(NR_UE_MAC_INST_t *mac,
nr_sidelink_indication_t *sl_ind,
const NR_SL_BWP_Generic_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool,
sl_nr_rx_config_request_t *rx_config,
uint8_t *config_type) {
*config_type = SL_NR_CONFIG_TYPE_RX_PSFCH;
rx_config->number_pdus = 1;
rx_config->sfn = sl_ind->frame_rx;
rx_config->slot = sl_ind->slot_rx;
rx_config->sl_rx_config_list[0].pdu_type = *config_type;
config_psfch_pdu_rx(mac, &rx_config->sl_rx_config_list[0].rx_pscch_config_pdu,
sl_bwp,
sl_res_pool);
LOG_D(NR_MAC, "[UE%d] TTI-%d:%d RX PSFCH REQ \n", sl_ind->module_id,sl_ind->frame_rx, sl_ind->slot_rx);
}
// void nr_ue_sl_psfch_rx_scheduler(NR_UE_MAC_INST_t *mac,
// nr_sidelink_indication_t *sl_ind,
// const NR_SL_BWP_Generic_r16_t *sl_bwp,
// const NR_SL_ResourcePool_r16_t *sl_res_pool,
// sl_nr_rx_config_request_t *rx_config,
// uint8_t *config_type) {
// *config_type = SL_NR_CONFIG_TYPE_RX_PSFCH;
// rx_config->number_pdus = 1;
// rx_config->sfn = sl_ind->frame_rx;
// rx_config->slot = sl_ind->slot_rx;
// rx_config->sl_rx_config_list[0].pdu_type = *config_type;
// config_psfch_pdu_rx(mac, &rx_config->sl_rx_config_list[0].rx_pscch_config_pdu,
// sl_bwp,
// sl_res_pool);
// LOG_D(NR_MAC, "[UE%d] TTI-%d:%d RX PSFCH REQ \n", sl_ind->module_id,sl_ind->frame_rx, sl_ind->slot_rx);
// }
void nr_ue_sl_pscch_rx_scheduler(nr_sidelink_indication_t *sl_ind,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool,
......@@ -3536,12 +3536,11 @@ void nr_ue_sidelink_scheduler(nr_sidelink_indication_t *sl_ind) {
module_id_t mod_id = sl_ind->module_id;
frame_t frame = sl_ind->frame_rx;
slot_t slot = sl_ind->slot_rx;
if (sl_ind->slot_type == SIDELINK_SLOT_TYPE_TX) {
frame = sl_ind->frame_tx;
slot = sl_ind->slot_tx;
}
LOG_D(NR_PHY, "frame: %d, slot %d, type: %d\n", frame, slot, sl_ind->slot_type);
NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
sl_nr_ue_mac_params_t *sl_mac = mac->SL_MAC_PARAMS;
sl_nr_phy_config_request_t *sl_cfg = &sl_mac->sl_phy_config.sl_config_req;
......@@ -3585,15 +3584,17 @@ void nr_ue_sidelink_scheduler(nr_sidelink_indication_t *sl_ind) {
if (((1<<slot_mod_period) % mask) == 0) rx_allowed=false;
}
if (sl_ind->slot_type==SIDELINK_SLOT_TYPE_TX || sl_ind->phy_data==NULL) rx_allowed=false;
LOG_D(NR_MAC, "sync_ref %d, slot_rx %d, rx_allowed %d, psbch slot %d\n", get_nrUE_params()->sync_ref, sl_ind->slot_rx, rx_allowed, !is_psbch_slot);
if (get_nrUE_params()->sync_ref && rx_allowed && !is_psbch_slot) {
NR_SL_PSFCH_Config_r16_t *sl_psfch_config = mac->sl_rx_res_pool->sl_PSFCH_Config_r16->choice.setup;
long psfch_period = *sl_psfch_config->sl_PSFCH_Period_r16;
if (slot%psfch_period == 0) {
LOG_D(NR_MAC,"Scheduling PSFCH RX processing slot %d, sync_ref %d\n",slot,get_nrUE_params()->sync_ref);
nr_ue_sl_psfch_rx_scheduler(mac, sl_ind, mac->sl_bwp->sl_BWP_Generic_r16, mac->sl_rx_res_pool, &rx_config, &tti_action);
}
}
// LOG_D(NR_MAC, "sync_ref %d, slot_rx %d, rx_allowed %d, psbch slot %d\n", get_nrUE_params()->sync_ref, sl_ind->slot_rx, rx_allowed, !is_psbch_slot);
// if (get_nrUE_params()->sync_ref && rx_allowed && !is_psbch_slot) {
// NR_SL_PSFCH_Config_r16_t *sl_psfch_config = mac->sl_rx_res_pool->sl_PSFCH_Config_r16->choice.setup;
// const uint8_t psfch_periods[] = {0,1,2,4};
// long psfch_period = (sl_psfch_config->sl_PSFCH_Period_r16)
// ? psfch_periods[*sl_psfch_config->sl_PSFCH_Period_r16] : 0;
// if (slot%psfch_period == 0) {
// LOG_D(NR_MAC,"Scheduling PSFCH RX processing slot %d, sync_ref %d\n",slot,get_nrUE_params()->sync_ref);
// nr_ue_sl_psfch_rx_scheduler(mac, sl_ind, mac->sl_bwp->sl_BWP_Generic_r16, mac->sl_rx_res_pool, &rx_config, &tti_action);
// }
// }
if (((get_nrUE_params()->sync_ref && sl_ind->slot_rx > 9) ||
(!get_nrUE_params()->sync_ref && sl_ind->slot_rx < 10)) && rx_allowed && !is_psbch_slot) {
......@@ -3606,19 +3607,26 @@ void nr_ue_sidelink_scheduler(nr_sidelink_indication_t *sl_ind) {
if (sl_ind->slot_type == SIDELINK_SLOT_TYPE_TX && mac->sci_pdu_rx.harq_feedback) {
NR_SL_PSFCH_Config_r16_t *sl_psfch_config = mac->sl_tx_res_pool->sl_PSFCH_Config_r16->choice.setup;
long psfch_period = *sl_psfch_config->sl_PSFCH_Period_r16;
const uint8_t psfch_periods[] = {0,1,2,4};
long psfch_period = (sl_psfch_config->sl_PSFCH_Period_r16)
? psfch_periods[*sl_psfch_config->sl_PSFCH_Period_r16] : 0;
NR_UE_sl_harq_t *current_harq;
for (int harq_pid = 0; harq_pid < 16; harq_pid++) {
current_harq = &mac->sl_info.list[0]->UE_sched_ctrl.sl_harq_processes[harq_pid];
sl_ind->slot_tx = current_harq->feedback_slot;
sl_ind->frame_tx = current_harq->feedback_frame;
if (slot%psfch_period == 0 && current_harq->feedback_slot == slot && current_harq->feedback_frame == frame && current_harq->is_active) {
LOG_I(NR_MAC, "Scheduling PSFCH transmission at frame %d slot %d \n", current_harq->feedback_frame, current_harq->feedback_slot);
nr_ue_sl_psfch_scheduler(mac, sl_ind, mac->sl_bwp, mac->sl_tx_res_pool, &tx_config, &tti_action);
current_harq->is_active = false;
break;
}
}
// if (slot%psfch_period == 0) {
// for (int harq_pid = 0; harq_pid < 16; harq_pid++) {
// current_harq = &mac->sl_info.list[0]->UE_sched_ctrl.sl_harq_processes[harq_pid];
// sl_ind->slot_tx = current_harq->feedback_slot;
// sl_ind->frame_tx = current_harq->feedback_frame;
// if (current_harq->feedback_slot > 0 && current_harq->feedback_frame > 0 && current_harq->is_active) {
// LOG_D(NR_MAC, "harq pid %d, sl_ind->frame_tx %d, sl_ind->slot_tx %d, frame %d, slot %d\n", harq_pid, sl_ind->frame_tx, sl_ind->slot_tx, frame, slot);
// if (current_harq->feedback_slot == slot && current_harq->feedback_frame == frame && current_harq->is_active) {
// LOG_I(NR_MAC, "Scheduling PSFCH transmission at frame %d slot %d for harq_pid %d\n", current_harq->feedback_frame, current_harq->feedback_slot, harq_pid);
// nr_ue_sl_psfch_scheduler(mac, sl_ind, mac->sl_bwp, mac->sl_tx_res_pool, &tx_config, &tti_action);
// current_harq->is_active = false;
// break;
// }
// }
// }
// }
}
}
if (tti_action == SL_NR_CONFIG_TYPE_RX_PSBCH || tti_action == SL_NR_CONFIG_TYPE_RX_PSCCH || tti_action == SL_NR_CONFIG_TYPE_RX_PSSCH_SCI || tti_action == SL_NR_CONFIG_TYPE_RX_PSSCH_SLSCH) {
......@@ -3641,52 +3649,43 @@ void nr_ue_sidelink_scheduler(nr_sidelink_indication_t *sl_ind) {
}
void nr_ue_sl_psfch_scheduler(NR_UE_MAC_INST_t *mac,
nr_sidelink_indication_t *sl_ind,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool,
sl_nr_tx_config_request_t *tx_config,
uint8_t *config_type) {
uint8_t ret_status = 0;
uint16_t slot = sl_ind->slot_tx;
uint16_t frame = sl_ind->frame_tx;
int lcid = 4;
int sdu_length = 0;
if ((frame & 127) == 0 && slot == 0) {
print_meas(&mac->rlc_data_req,"rlc_data_req",NULL,NULL);
}
if (sl_ind->slot_type != SIDELINK_SLOT_TYPE_TX) return false;
// if (slot > 9 && get_nrUE_params()->sync_ref) return false;
// if (slot < 10 && !get_nrUE_params()->sync_ref) return false;
/*
if ((frame&127) > 0) return false;
if ((slot % 10) != 6) return false;
*/
LOG_D(NR_MAC,"[UE%d] SL-PSFCH SCHEDULER: Frame:SLOT %d:%d, slot_type:%d\n",
sl_ind->module_id, frame, slot,sl_ind->slot_type);
sl_nr_tx_config_psfch_pdu_t *tx_psfch_pdu = &tx_config->tx_config_list[0].tx_psfch_config_pdu;
tx_psfch_pdu->start_symbol_index = mac->sl_tx_config_psfch_pdu->start_symbol_index;
tx_psfch_pdu->hopping_id = mac->sl_tx_config_psfch_pdu->hopping_id;
tx_psfch_pdu->prb = mac->sl_tx_config_psfch_pdu->prb;
tx_psfch_pdu->initial_cyclic_shift = mac->sl_tx_config_psfch_pdu->initial_cyclic_shift;
tx_psfch_pdu->mcs = mac->sl_tx_config_psfch_pdu->mcs;
tx_psfch_pdu->freq_hop_flag = 0;
tx_psfch_pdu->second_hop_prb = 0;
tx_psfch_pdu->group_hop_flag = 0;
tx_psfch_pdu->sequence_hop_flag = 0;
tx_psfch_pdu->nr_of_symbols = 1;
tx_psfch_pdu->psfch_payload = mac->sl_tx_config_psfch_pdu->psfch_payload;
*config_type = SL_NR_CONFIG_TYPE_TX_PSFCH;
tx_config->number_pdus = 1;
tx_config->sfn = frame;
tx_config->slot = slot;
tx_config->tx_config_list[0].pdu_type = *config_type;
}
\ No newline at end of file
// void nr_ue_sl_psfch_scheduler(NR_UE_MAC_INST_t *mac,
// nr_sidelink_indication_t *sl_ind,
// const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
// const NR_SL_ResourcePool_r16_t *sl_res_pool,
// sl_nr_tx_config_request_t *tx_config,
// uint8_t *config_type) {
// uint16_t slot = sl_ind->slot_tx;
// uint16_t frame = sl_ind->frame_tx;
// if (sl_ind->slot_type != SIDELINK_SLOT_TYPE_TX) return false;
// NR_UE_sl_harq_t *current_harq;
// for (int harq_pid = 0; harq_pid < 16; harq_pid++) {
// current_harq = &mac->sl_info.list[0]->UE_sched_ctrl.sl_harq_processes[harq_pid];
// if (current_harq->feedback_slot == slot && current_harq->feedback_frame == frame && current_harq->is_active) {
// sl_nr_tx_config_psfch_pdu_t *tx_psfch_pdu = &tx_config->tx_config_list[0].tx_psfch_config_pdu;
// tx_psfch_pdu->start_symbol_index = mac->sl_tx_config_psfch_pdu[harq_pid]->start_symbol_index;
// tx_psfch_pdu->hopping_id = mac->sl_tx_config_psfch_pdu[harq_pid]->hopping_id;
// tx_psfch_pdu->prb = mac->sl_tx_config_psfch_pdu[harq_pid]->prb;
// tx_psfch_pdu->initial_cyclic_shift = mac->sl_tx_config_psfch_pdu[harq_pid]->initial_cyclic_shift;
// tx_psfch_pdu->mcs = mac->sl_tx_config_psfch_pdu[harq_pid]->mcs;
// tx_psfch_pdu->freq_hop_flag = 0;
// tx_psfch_pdu->second_hop_prb = 0;
// tx_psfch_pdu->group_hop_flag = 0;
// tx_psfch_pdu->sequence_hop_flag = 0;
// tx_psfch_pdu->nr_of_symbols = 1;
// tx_psfch_pdu->psfch_payload = mac->sl_tx_config_psfch_pdu[harq_pid]->psfch_payload;
// *config_type = SL_NR_CONFIG_TYPE_TX_PSFCH;
// tx_config->number_pdus = 1;
// tx_config->sfn = frame;
// tx_config->slot = slot;
// tx_config->tx_config_list[0].pdu_type = *config_type;
// LOG_D(NR_MAC,"[UE%d] Harq id: %d, SL-PSFCH SCHEDULER: Frame:SLOT %d:%d, slot_type:%d\n",
// harq_pid, sl_ind->module_id, frame, slot,sl_ind->slot_type);
// break;
// }
// }
// }
\ No newline at end of file
openair2/LAYER2/NR_MAC_UE/nr_ue_sci_slsch.c
View file @ f5250c1e
......@@ -249,7 +249,7 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p
if (num_psfch_symbols == 3) num_psfch_symbols++;
}
nr_sl_pssch_pscch_pdu->pssch_numsym=7+*sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16-num_psfch_symbols-2;
LOG_I(NR_PHY, "num_psfch_symbols %d, sl_LengthSymbols: %d, pssch_numsym: %d\n", num_psfch_symbols, *sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16, nr_sl_pssch_pscch_pdu->pssch_numsym);
LOG_D(NR_PHY, "num_psfch_symbols %d, sl_LengthSymbols: %d, pssch_numsym: %d\n", num_psfch_symbols, *sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16, nr_sl_pssch_pscch_pdu->pssch_numsym);
nr_sl_pssch_pscch_pdu->pssch_startsym = *sl_bwp->sl_BWP_Generic_r16->sl_StartSymbol_r16;
nr_sl_pssch_pscch_pdu->sci2_beta_offset = *sl_res_pool->sl_PSSCH_Config_r16->choice.setup->sl_BetaOffsets2ndSCI_r16->list.array[sci_pdu->beta_offset_indicator];
......@@ -355,7 +355,7 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p
N_RE,1+(sci_pdu->number_of_dmrs_port&1))>>3;
nr_sl_pssch_pscch_pdu->mcs = sci_pdu->mcs;
nr_sl_pssch_pscch_pdu->num_layers = sci_pdu->number_of_dmrs_port+1;
LOG_I(NR_MAC,"PSSCH: mcs %d, coderate %d, Nl %d => tbs %d\n",sci_pdu->mcs,nr_sl_pssch_pscch_pdu->target_coderate,nr_sl_pssch_pscch_pdu->num_layers,nr_sl_pssch_pscch_pdu->tb_size);
LOG_D(NR_MAC,"PSSCH: mcs %d, coderate %d, Nl %d => tbs %d\n",sci_pdu->mcs,nr_sl_pssch_pscch_pdu->target_coderate,nr_sl_pssch_pscch_pdu->num_layers,nr_sl_pssch_pscch_pdu->tb_size);
nr_sl_pssch_pscch_pdu->tbslbrm = nr_compute_tbslbrm(mcs_tb_ind,NRRIV2BW(sl_bwp->sl_BWP_Generic_r16->sl_BWP_r16->locationAndBandwidth,273),nr_sl_pssch_pscch_pdu->num_layers);
nr_sl_pssch_pscch_pdu->mcs_table=mcs_tb_ind;
nr_sl_pssch_pscch_pdu->rv_index = sci2_pdu->rv_index;
......@@ -462,26 +462,25 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p
nr_sl_pssch_pscch_pdu->slsch_payload_length = slsch_pdu_length;
};
void config_psfch_pdu_rx(NR_UE_MAC_INST_t *mac,
sl_nr_rx_config_psfch_pdu_t *nr_sl_psfch_pdu,
const NR_SL_BWP_Generic_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool) {
nr_sl_psfch_pdu->freq_hop_flag = 0;
nr_sl_psfch_pdu->group_hop_flag = 0;
nr_sl_psfch_pdu->sequence_hop_flag = 0;
nr_sl_psfch_pdu->second_hop_prb = 0;
nr_sl_psfch_pdu->nr_of_symbols = 1;
const uint8_t values[] = {7, 8, 9, 10, 11, 12, 13, 14};
LOG_D(NR_MAC, "E1 *sl_bwp->sl_LengthSymbols_r16 %d\n", *sl_bwp->sl_LengthSymbols_r16);
uint8_t sl_num_symbols = *sl_bwp->sl_LengthSymbols_r16 ?
values[*sl_bwp->sl_LengthSymbols_r16] : 0;
nr_sl_psfch_pdu->start_symbol_index = *sl_bwp->sl_StartSymbol_r16 + sl_num_symbols - 2;
nr_sl_psfch_pdu->hopping_id = 0;
nr_sl_psfch_pdu->prb = 1;
// nr_sl_psfch_pdu->initial_cyclic_shift = mac->sl_;
// nr_sl_psfch_pdu->mcs = mac->sl_;
nr_sl_psfch_pdu->psfch_payload = 0;
}
// void config_psfch_pdu_rx(NR_UE_MAC_INST_t *mac,
// sl_nr_rx_config_psfch_pdu_t *nr_sl_psfch_pdu,
// const NR_SL_BWP_Generic_r16_t *sl_bwp,
// const NR_SL_ResourcePool_r16_t *sl_res_pool) {
// nr_sl_psfch_pdu->freq_hop_flag = 0;
// nr_sl_psfch_pdu->group_hop_flag = 0;
// nr_sl_psfch_pdu->sequence_hop_flag = 0;
// nr_sl_psfch_pdu->second_hop_prb = 0;
// nr_sl_psfch_pdu->nr_of_symbols = 1;
// const uint8_t values[] = {7, 8, 9, 10, 11, 12, 13, 14};
// uint8_t sl_num_symbols = *sl_bwp->sl_LengthSymbols_r16 ?
// values[*sl_bwp->sl_LengthSymbols_r16] : 0;
// nr_sl_psfch_pdu->start_symbol_index = *sl_bwp->sl_StartSymbol_r16 + sl_num_symbols - 2;
// nr_sl_psfch_pdu->hopping_id = 0;
// nr_sl_psfch_pdu->prb = 1;
// //TODO
// // nr_sl_psfch_pdu->initial_cyclic_shift = mac->sl_;
// // nr_sl_psfch_pdu->mcs = mac->sl_;
// }
void config_pscch_pdu_rx(sl_nr_rx_config_pscch_pdu_t *nr_sl_pscch_pdu,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
......
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
View file @ f5250c1e
......@@ -1498,7 +1498,7 @@ void sl_nr_process_rx_ind(uint16_t mod_id,
break;
case SL_NR_RX_PDU_TYPE_SLSCH:
LOG_I(NR_MAC, "%s[UE%d]SL-MAC Received SLSCH: rx_slsch_pdu:%p, rx_slsch_len %d, ack_nack %d, harq_pid %d\n",KGRN,
LOG_D(NR_MAC, "%s[UE%d]SL-MAC Received SLSCH: rx_slsch_pdu:%p, rx_slsch_len %d, ack_nack %d, harq_pid %d\n",KGRN,
mod_id,rx_ind->rx_indication_body[num_pdus - 1].rx_slsch_pdu.pdu,
rx_ind->rx_indication_body[num_pdus - 1].rx_slsch_pdu.pdu_length,
rx_ind->rx_indication_body[num_pdus - 1].rx_slsch_pdu.ack_nack,
......
openair2/RRC/NR_UE/rrc_sl_preconfig.c
View file @ f5250c1e
......@@ -141,7 +141,7 @@ static void prepare_NR_SL_ResourcePool(NR_SL_ResourcePool_r16_t *sl_res_pool,
//and HARQ feedback for all transmissions in the resource pool is disabled.
// {sl0, sl1, sl2, sl4}
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 = calloc(1, sizeof(long));
*sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 = NR_SL_PSFCH_Config_r16__sl_PSFCH_Period_r16_sl2;
*sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 = NR_SL_PSFCH_Config_r16__sl_PSFCH_Period_r16_sl4;
// Set of PRBs that are actually used for PSFCH transmission and reception (bitmap)
// 0b10101010101010101010101010101010101010101010101001 (PRBs bitmap)
......
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