dci_tools.c 377 KB
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/*
 * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.
 * The OpenAirInterface Software Alliance licenses this file to You under
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 * the OAI Public License, Version 1.1  (the "License"); you may not use this file
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 * except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.openairinterface.org/?page_id=698
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *-------------------------------------------------------------------------------
 * For more information about the OpenAirInterface (OAI) Software Alliance:
 *      contact@openairinterface.org
 */

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/*! \file PHY/LTE_TRANSPORT/dci_tools.c
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 * \brief PHY Support routines (eNB/UE) for filling PDSCH/PUSCH/DLSCH/ULSCH data structures based on DCI PDUs generated by eNB MAC scheduler.
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 * \author R. Knopp
 * \date 2011
 * \version 0.1
 * \company Eurecom
 * \email: knopp@eurecom.fr
 * \note
 * \warning
 */
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#include "PHY/defs.h"
#include "PHY/extern.h"
#include "SCHED/defs.h"
#ifdef DEBUG_DCI_TOOLS
#include "PHY/vars.h"
#endif
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#include "assertions.h"
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#include "nfapi_interface.h"
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//#define DEBUG_HARQ
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#include "LAYER2/MAC/extern.h"
#include "LAYER2/MAC/defs.h"

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/*#undef LOG_D
#define LOG_D(A,B,C...) printf(B,C)
#undef LOG_I
#define LOG_I(A,B,C...) printf(B,C)
*/
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//#define DEBUG_DCI

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uint32_t localRIV2alloc_LUT6[32];
uint32_t distRIV2alloc_even_LUT6[32];
uint32_t distRIV2alloc_odd_LUT6[32];
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uint16_t RIV2nb_rb_LUT6[32];
uint16_t RIV2first_rb_LUT6[32];
uint16_t RIV_max6=0;

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uint32_t localRIV2alloc_LUT25[512];
uint32_t distRIV2alloc_even_LUT25[512];
uint32_t distRIV2alloc_odd_LUT25[512];
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uint16_t RIV2nb_rb_LUT25[512];
uint16_t RIV2first_rb_LUT25[512];
uint16_t RIV_max25=0;


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uint32_t localRIV2alloc_LUT50_0[1600];
uint32_t localRIV2alloc_LUT50_1[1600];
uint32_t distRIV2alloc_gap0_even_LUT50_0[1600];
uint32_t distRIV2alloc_gap0_odd_LUT50_0[1600];
uint32_t distRIV2alloc_gap0_even_LUT50_1[1600];
uint32_t distRIV2alloc_gap0_odd_LUT50_1[1600];
uint32_t distRIV2alloc_gap1_even_LUT50_0[1600];
uint32_t distRIV2alloc_gap1_odd_LUT50_0[1600];
uint32_t distRIV2alloc_gap1_even_LUT50_1[1600];
uint32_t distRIV2alloc_gap1_odd_LUT50_1[1600];
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uint16_t RIV2nb_rb_LUT50[1600];
uint16_t RIV2first_rb_LUT50[1600];
uint16_t RIV_max50=0;

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uint32_t localRIV2alloc_LUT100_0[6000];
uint32_t localRIV2alloc_LUT100_1[6000];
uint32_t localRIV2alloc_LUT100_2[6000];
uint32_t localRIV2alloc_LUT100_3[6000];
uint32_t distRIV2alloc_gap0_even_LUT100_0[6000];
uint32_t distRIV2alloc_gap0_odd_LUT100_0[6000];
uint32_t distRIV2alloc_gap0_even_LUT100_1[6000];
uint32_t distRIV2alloc_gap0_odd_LUT100_1[6000];
uint32_t distRIV2alloc_gap0_even_LUT100_2[6000];
uint32_t distRIV2alloc_gap0_odd_LUT100_2[6000];
uint32_t distRIV2alloc_gap0_even_LUT100_3[6000];
uint32_t distRIV2alloc_gap0_odd_LUT100_3[6000];
uint32_t distRIV2alloc_gap1_even_LUT100_0[6000];
uint32_t distRIV2alloc_gap1_odd_LUT100_0[6000];
uint32_t distRIV2alloc_gap1_even_LUT100_1[6000];
uint32_t distRIV2alloc_gap1_odd_LUT100_1[6000];
uint32_t distRIV2alloc_gap1_even_LUT100_2[6000];
uint32_t distRIV2alloc_gap1_odd_LUT100_2[6000];
uint32_t distRIV2alloc_gap1_even_LUT100_3[6000];
uint32_t distRIV2alloc_gap1_odd_LUT100_3[6000];
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uint16_t RIV2nb_rb_LUT100[6000];
uint16_t RIV2first_rb_LUT100[6000];
uint16_t RIV_max100=0;


extern uint32_t current_dlsch_cqi;

// Table 8.6.3-3 36.213
uint16_t beta_cqi[16] = {0,   //reserved
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                         0,   //reserved
                         9,   //1.125
                         10,  //1.250
                         11,  //1.375
                         13,  //1.625
                         14,  //1.750
                         16,  //2.000
                         18,  //2.250
                         20,  //2.500
                         23,  //2.875
                         25,  //3.125
                         28,  //3.500
                         32,  //4.000
                         40,  //5.000
                         50
                        }; //6.250
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// Table 8.6.3-2 36.213
uint16_t beta_ri[16] = {10,   //1.250
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                        13,   //1.625
                        16,   //2.000
                        20,   //2.500
                        25,   //3.125
                        32,   //4.000
                        40,   //5.000
                        50,   //6.250
                        64,   //8.000
                        80,   //10.000
                        101,  //12.625
                        127,  //15.875
                        160,  //20.000
                        0,    //reserved
                        0,    //reserved
                        0
                       };   //reserved
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// Table 8.6.3-2 36.213
uint16_t beta_ack[16] = {16,  //2.000
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                         20,  //2.500
                         25,  //3.125
                         32,  //4.000
                         40,  //5.000
                         50,  //6.250
                         64,  //8.000
                         80,  //10.000
                         101, //12.625
                         127, //15.875
                         160, //20.000
                         248, //31.000
                         400, //50.000
                         640, //80.000
                         808
                        };//126.00
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int8_t delta_PUSCH_abs[4] = {-4,-1,1,4};
int8_t delta_PUSCH_acc[4] = {-1,0,1,3};

int8_t *delta_PUCCH_lut = delta_PUSCH_acc;
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void conv_eMTC_rballoc(uint16_t resource_block_coding,
		       uint32_t N_RB_DL,
		       uint32_t *rb_alloc) {

   
  int narrowband = resource_block_coding>>5;
  int RIV        = resource_block_coding&31;
  int N_NB_DL    = N_RB_DL/6;
  int i0         = (N_RB_DL>>1) - (3*N_NB_DL);
  int first_rb   = (6*narrowband)+i0;
  int alloc      = localRIV2alloc_LUT6[RIV];
  int ind        = first_rb>>5;
  int ind_mod    = first_rb&31;

  if (((N_RB_DL&1) > 0) && (narrowband>=(N_NB_DL>>1))) first_rb++;
  rb_alloc[0]                        = 0;
  rb_alloc[1]                        = 0;
  rb_alloc[2]                        = 0;
  rb_alloc[3]                        = 0;
  rb_alloc[ind]                      = alloc<<ind_mod;
  if (ind_mod > 26)  rb_alloc[ind+1] = alloc>>(6-(ind_mod-26)); 
}

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void conv_rballoc(uint8_t ra_header,uint32_t rb_alloc,uint32_t N_RB_DL,uint32_t *rb_alloc2)
{
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  uint32_t i,shift,subset;
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  rb_alloc2[0] = 0;
  rb_alloc2[1] = 0;
  rb_alloc2[2] = 0;
  rb_alloc2[3] = 0;
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  //  printf("N_RB_DL %d, ra_header %d, rb_alloc %x\n",N_RB_DL,ra_header,rb_alloc);

  switch (N_RB_DL) {

  case 6:
    rb_alloc2[0] = rb_alloc&0x3f;
    break;

  case 25:
    if (ra_header == 0) {// Type 0 Allocation
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      for (i=12; i>0; i--) {
        if ((rb_alloc&(1<<i)) != 0)
          rb_alloc2[0] |= (3<<((2*(12-i))));

        //      printf("rb_alloc2 (type 0) %x\n",rb_alloc2);
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      }
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      if ((rb_alloc&1) != 0)
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        rb_alloc2[0] |= (1<<24);
    } else {
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      subset = rb_alloc&1;
      shift  = (rb_alloc>>1)&1;
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      for (i=0; i<11; i++) {
        if ((rb_alloc&(1<<(i+2))) != 0)
          rb_alloc2[0] |= (1<<(2*i));

        //printf("rb_alloc2 (type 1) %x\n",rb_alloc2);
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      }
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      if ((shift == 0) && (subset == 1))
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        rb_alloc2[0]<<=1;
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      else if ((shift == 1) && (subset == 0))
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        rb_alloc2[0]<<=4;
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      else if ((shift == 1) && (subset == 1))
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        rb_alloc2[0]<<=3;
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    }
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    break;
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  case 50:
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    AssertFatal(ra_header==0,"resource type 1 not supported for  N_RB_DL=50\n");
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    for (i=16; i>0; i--) {
      if ((rb_alloc&(1<<i)) != 0)
	rb_alloc2[(3*(16-i))>>5] |= (7<<((3*(16-i))%32));
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    }
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    // bit mask across
    if ((rb_alloc2[0]>>31)==1)
      rb_alloc2[1] |= 1;
    
    if ((rb_alloc&1) != 0)
      rb_alloc2[1] |= (3<<16);
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    break;

  case 100:
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    AssertFatal(ra_header==0,"resource type 1 not supported for  N_RB_DL=100\n");
    for (i=0; i<25; i++) {
      if ((rb_alloc&(1<<(24-i))) != 0)
	rb_alloc2[(4*i)>>5] |= (0xf<<((4*i)%32));
      
      //  printf("rb_alloc2[%d] (type 0) %x (%d)\n",(4*i)>>5,rb_alloc2[(4*i)>>5],rb_alloc&(1<<i));
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    }
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    break;

  default:
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    LOG_E(PHY,"Invalid N_RB_DL %d\n", N_RB_DL);
    DevParam (N_RB_DL, 0, 0);
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    break;
  }

}



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uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL)
{
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  uint32_t nprb=0,i;

  switch (N_RB_DL) {
  case 6:
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    for (i=0; i<6; i++) {
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      if ((rb_alloc&(1<<i)) != 0)
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        nprb += 1;
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    }
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    break;
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  case 25:
    if (ra_header == 0) {// Type 0 Allocation
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      for (i=12; i>0; i--) {
        if ((rb_alloc&(1<<i)) != 0)
          nprb += 2;
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      }
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      if ((rb_alloc&1) != 0)
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        nprb += 1;
    } else {
      for (i=0; i<11; i++) {
        if ((rb_alloc&(1<<(i+2))) != 0)
          nprb += 1;
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      }
    }
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    break;
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  case 50:
    if (ra_header == 0) {// Type 0 Allocation
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      for (i=0; i<16; i++) {
        if ((rb_alloc&(1<<(16-i))) != 0)
          nprb += 3;
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      }
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      if ((rb_alloc&1) != 0)
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        nprb += 2;
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    } else {
      for (i=0; i<17; i++) {
        if ((rb_alloc&(1<<(i+2))) != 0)
          nprb += 1;
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      }
    }
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    break;
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  case 100:
    if (ra_header == 0) {// Type 0 Allocation
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      for (i=0; i<25; i++) {
        if ((rb_alloc&(1<<(24-i))) != 0)
          nprb += 4;
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      }
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    } else {
      for (i=0; i<25; i++) {
        if ((rb_alloc&(1<<(i+2))) != 0)
          nprb += 1;
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      }
    }
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    break;
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  default:
    LOG_E(PHY,"Invalide N_RB_DL %d\n", N_RB_DL);
    DevParam (N_RB_DL, 0, 0);
    break;
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  }

  return(nprb);
}

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uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs)
{
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  uint16_t RIV;
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  if (Lcrbs<=(1+(N_RB_DL>>1)))
    RIV = (N_RB_DL*(Lcrbs-1)) + RBstart;
  else
    RIV = (N_RB_DL*(N_RB_DL+1-Lcrbs)) + (N_RB_DL-1-RBstart);
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  return(RIV);
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}

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// Convert a DCI Format 1C RIV to a Format 1A RIV
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// This extracts the start and length in PRBs from the 1C rballoc and
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// recomputes the RIV as if it were the 1A rballoc

uint32_t conv_1C_RIV(int32_t rballoc,uint32_t N_RB_DL) {

  int NpDLVRB,N_RB_step,LpCRBsm1,RBpstart;

  switch (N_RB_DL) {

  case 6: // N_RB_step = 2, NDLVRB = 6, NpDLVRB = 3
    NpDLVRB   = 3;
    N_RB_step = 2;
    break;
  case 25: // N_RB_step = 2, NDLVRB = 24, NpDLVRB = 12
    NpDLVRB   = 12;
    N_RB_step = 2;
    break;
  case 50: // N_RB_step = 4, NDLVRB = 46, NpDLVRB = 11
    NpDLVRB   = 11;
    N_RB_step = 4;
    break;
  case 100: // N_RB_step = 4, NDLVRB = 96, NpDLVRB = 24
    NpDLVRB   = 24;
    N_RB_step = 4;
    break;
  default:
    NpDLVRB   = 24;
    N_RB_step = 4;
    break;
  }

  // This is the 1C part from 7.1.6.3 in 36.213
  LpCRBsm1 = rballoc/NpDLVRB;
  //  printf("LpCRBs = %d\n",LpCRBsm1+1);

  if (LpCRBsm1 <= (NpDLVRB/2)) {
    RBpstart = rballoc % NpDLVRB;
  }
  else {
    LpCRBsm1 = NpDLVRB-LpCRBsm1;
    RBpstart = NpDLVRB-(rballoc%NpDLVRB);
  }
  //  printf("RBpstart %d\n",RBpstart);
  return(computeRIV(N_RB_DL,N_RB_step*RBpstart,N_RB_step*(LpCRBsm1+1)));
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}

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uint32_t get_prb(int N_RB_DL,int odd_slot,int vrb,int Ngap) {
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  int offset;

  switch (N_RB_DL) {
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  case 6:
  // N_RB_DL = tildeN_RB_DL = 6
  // Ngap = 4 , P=1, Nrow = 2, Nnull = 2
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    switch (vrb) {
    case 0:  // even: 0->0, 1->2, odd: 0->3, 1->5
    case 1:
      return ((3*odd_slot) + 2*(vrb&3))%6;
      break;
    case 2:  // even: 2->3, 3->5, odd: 2->0, 3->2
    case 3:
      return ((3*odd_slot) + 2*(vrb&3) + 5)%6;
      break;
    case 4:  // even: 4->1, odd: 4->4
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      return ((3*odd_slot) + 1)%6;
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    case 5:  // even: 5->4, odd: 5->1
      return ((3*odd_slot) + 4)%6;
      break;
    }
    break;
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  case 15:
    if (vrb<12) {
      if ((vrb&3) < 2)     // even: 0->0, 1->4, 4->1, 5->5, 8->2, 9->6 odd: 0->7, 1->11
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  return(((7*odd_slot) + 4*(vrb&3) + (vrb>>2))%14) + 14*(vrb/14);
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      else if (vrb < 12) // even: 2->7, 3->11, 6->8, 7->12, 10->9, 11->13
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  return (((7*odd_slot) + 4*(vrb&3) + (vrb>>2) +13 )%14) + 14*(vrb/14);
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    }
    if (vrb==12)
      return (3+(7*odd_slot)) % 14;
    if (vrb==13)
      return (10+(7*odd_slot)) % 14;
    return 14;
    break;
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  case 25:
    return (((12*odd_slot) + 6*(vrb&3) + (vrb>>2))%24) + 24*(vrb/24);
    break;
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  case 50: // P=3
    if (Ngap==0) {
      // Nrow=12,Nnull=2,NVRBDL=46,Ngap1= 27
      if (vrb>=23)
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  offset=4;
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      else
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  offset=0;
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      if (vrb<44) {
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  if ((vrb&3)>=2)
    return offset+((23*odd_slot) + 12*(vrb&3) + (vrb>>2) + 45)%46;
  else
    return offset+((23*odd_slot) + 12*(vrb&3) + (vrb>>2))%46;
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      }
      if (vrb==44)  // even: 44->11, odd: 45->34
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  return offset+((23*odd_slot) + 22-12+1);
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      if (vrb==45)  // even: 45->10, odd: 45->33
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  return offset+((23*odd_slot) + 22+12);
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      if (vrb==46)
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  return offset+46+((23*odd_slot) + 23-12+1) % 46;
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      if (vrb==47)
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  return offset+46+((23*odd_slot) + 23+12) % 46;
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      if (vrb==48)
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  return offset+46+((23*odd_slot) + 23-12+1) % 46;
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      if (vrb==49)
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  return offset+46+((23*odd_slot) + 23+12) % 46;
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    }
    else {
      // Nrow=6,Nnull=6,NVRBDL=18,Ngap1= 27
      if (vrb>=9)
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  offset=18;
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      else
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  offset=0;
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      if (vrb<12) {
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  if ((vrb&3)>=2)
    return offset+((9*odd_slot) + 6*(vrb&3) + (vrb>>2) + 17)%18;
  else
    return offset+((9*odd_slot) + 6*(vrb&3) + (vrb>>2))%18;
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      }
      else {
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  return offset+((9*odd_slot) + 12*(vrb&1)+(vrb>>1) )%18 + 18*(vrb/18);
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      }
    }
    break;
  case 75:
    // Ngap1 = 32, NVRBRL=64, P=4, Nrow= 16, Nnull=0
    if (Ngap ==0) {
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      return ((32*odd_slot) + 16*(vrb&3) + (vrb>>2))%64 + (vrb/64);
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    } else {
      // Ngap2 = 16, NVRBDL=32, Nrow=8, Nnull=0
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      return ((16*odd_slot) + 8*(vrb&3) + (vrb>>2))%32 + (vrb/32);
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    }
    break;
  case 100:
    // Ngap1 = 48, NVRBDL=96, Nrow=24, Nnull=0
    if (Ngap ==0) {
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      return ((48*odd_slot) + 24*(vrb&3) + (vrb>>2))%96 + (vrb/96);
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    } else {
      // Ngap2 = 16, NVRBDL=32, Nrow=8, Nnull=0
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      return ((16*odd_slot) + 8*(vrb&3) + (vrb>>2))%32 + (vrb/32);
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    }
    break;
  default:
    LOG_E(PHY,"Unknown N_RB_DL %d\n",N_RB_DL);
    return 0;
  }
  return 0;
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}

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void generate_RIV_tables()
{
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  // 6RBs localized RIV
  uint8_t Lcrbs,RBstart;
  uint16_t RIV;
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  uint32_t alloc0,allocdist0_0_even,allocdist0_0_odd,allocdist0_1_even,allocdist0_1_odd;
  uint32_t alloc1,allocdist1_0_even,allocdist1_0_odd,allocdist1_1_even,allocdist1_1_odd;
  uint32_t alloc2,allocdist2_0_even,allocdist2_0_odd,allocdist2_1_even,allocdist2_1_odd;
  uint32_t alloc3,allocdist3_0_even,allocdist3_0_odd,allocdist3_1_even,allocdist3_1_odd;
  uint32_t nVRB,nVRB_even_dist,nVRB_odd_dist;
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  for (RBstart=0; RBstart<6; RBstart++) {
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    alloc0 = 0;
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    allocdist0_0_even = 0;
    allocdist0_0_odd  = 0;
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    for (Lcrbs=1; Lcrbs<=(6-RBstart); Lcrbs++) {
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      //printf("RBstart %d, len %d --> ",RBstart,Lcrbs);
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      nVRB             = Lcrbs-1+RBstart;
      alloc0          |= (1<<nVRB);
      allocdist0_0_even |= (1<<get_prb(6,0,nVRB,0));
      allocdist0_0_odd  |= (1<<get_prb(6,1,nVRB,0));
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      RIV=computeRIV(6,RBstart,Lcrbs);
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      if (RIV>RIV_max6)
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        RIV_max6 = RIV;
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      //      printf("RIV %d (%d) : first_rb %d NBRB %d\n",RIV,localRIV2alloc_LUT25[RIV],RBstart,Lcrbs);
      localRIV2alloc_LUT6[RIV] = alloc0;
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      distRIV2alloc_even_LUT6[RIV]  = allocdist0_0_even;
      distRIV2alloc_odd_LUT6[RIV]  = allocdist0_0_odd;
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      RIV2nb_rb_LUT6[RIV]      = Lcrbs;
      RIV2first_rb_LUT6[RIV]   = RBstart;
    }
  }


574
  for (RBstart=0; RBstart<25; RBstart++) {
575
    alloc0 = 0;
576 577
    allocdist0_0_even = 0;
    allocdist0_0_odd  = 0;
578
    for (Lcrbs=1; Lcrbs<=(25-RBstart); Lcrbs++) {
579
      nVRB = Lcrbs-1+RBstart;
580
      //printf("RBstart %d, len %d --> ",RBstart,Lcrbs);
581 582 583
      alloc0     |= (1<<nVRB);
      allocdist0_0_even |= (1<<get_prb(25,0,nVRB,0));
      allocdist0_0_odd  |= (1<<get_prb(25,1,nVRB,0));
584

585
      //printf("alloc 0 %x, allocdist0_even %x, allocdist0_odd %x\n",alloc0,allocdist0_0_even,allocdist0_0_odd);
586
      RIV=computeRIV(25,RBstart,Lcrbs);
587

588
      if (RIV>RIV_max25)
589
        RIV_max25 = RIV;;
590

591 592 593 594 595 596

      localRIV2alloc_LUT25[RIV]      = alloc0;
      distRIV2alloc_even_LUT25[RIV]  = allocdist0_0_even;
      distRIV2alloc_odd_LUT25[RIV]   = allocdist0_0_odd;
      RIV2nb_rb_LUT25[RIV]           = Lcrbs;
      RIV2first_rb_LUT25[RIV]        = RBstart;
597
    }
598 599 600
  }


601
  for (RBstart=0; RBstart<50; RBstart++) {
602 603
    alloc0 = 0;
    alloc1 = 0;
604 605 606 607 608 609 610 611
    allocdist0_0_even=0;
    allocdist1_0_even=0;
    allocdist0_0_odd=0;
    allocdist1_0_odd=0;
    allocdist0_1_even=0;
    allocdist1_1_even=0;
    allocdist0_1_odd=0;
    allocdist1_1_odd=0;
612 613

    for (Lcrbs=1; Lcrbs<=(50-RBstart); Lcrbs++) {
614

615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633
      nVRB = Lcrbs-1+RBstart;


      if (nVRB<32)
        alloc0 |= (1<<nVRB);
      else
        alloc1 |= (1<<(nVRB-32));

      // Distributed Gap1, even slot
      nVRB_even_dist = get_prb(50,0,nVRB,0);
      if (nVRB_even_dist<32)
        allocdist0_0_even |= (1<<nVRB_even_dist);
      else
        allocdist1_0_even |= (1<<(nVRB_even_dist-32));

      // Distributed Gap1, odd slot
      nVRB_odd_dist = get_prb(50,1,nVRB,0);
      if (nVRB_odd_dist<32)
        allocdist0_0_odd |= (1<<nVRB_odd_dist);
634
      else
635
        allocdist1_0_odd |= (1<<(nVRB_odd_dist-32));
636

637 638 639 640
      // Distributed Gap2, even slot
      nVRB_even_dist = get_prb(50,0,nVRB,1);
      if (nVRB_even_dist<32)
        allocdist0_1_even |= (1<<nVRB_even_dist);
641
      else
642 643 644 645 646 647 648 649
        allocdist1_1_even |= (1<<(nVRB_even_dist-32));

      // Distributed Gap2, odd slot
      nVRB_odd_dist = get_prb(50,1,nVRB,1);
      if (nVRB_odd_dist<32)
        allocdist0_1_odd |= (1<<nVRB_odd_dist);
      else
        allocdist1_1_odd |= (1<<(nVRB_odd_dist-32));
650 651

      RIV=computeRIV(50,RBstart,Lcrbs);
652

653
      if (RIV>RIV_max50)
654
        RIV_max50 = RIV;
655 656

      //      printf("RIV %d : first_rb %d NBRB %d\n",RIV,RBstart,Lcrbs);
657 658 659 660 661 662 663 664 665 666
      localRIV2alloc_LUT50_0[RIV]      = alloc0;
      localRIV2alloc_LUT50_1[RIV]      = alloc1;
      distRIV2alloc_gap0_even_LUT50_0[RIV]  = allocdist0_0_even;
      distRIV2alloc_gap0_even_LUT50_1[RIV]  = allocdist1_0_even;
      distRIV2alloc_gap0_odd_LUT50_0[RIV]   = allocdist0_0_odd;
      distRIV2alloc_gap0_odd_LUT50_1[RIV]   = allocdist1_0_odd;
      distRIV2alloc_gap1_even_LUT50_0[RIV]  = allocdist0_1_even;
      distRIV2alloc_gap1_even_LUT50_1[RIV]  = allocdist1_1_even;
      distRIV2alloc_gap1_odd_LUT50_0[RIV]   = allocdist0_1_odd;
      distRIV2alloc_gap1_odd_LUT50_1[RIV]   = allocdist1_1_odd;
667 668 669 670 671 672
      RIV2nb_rb_LUT50[RIV]        = Lcrbs;
      RIV2first_rb_LUT50[RIV]     = RBstart;
    }
  }


673
  for (RBstart=0; RBstart<100; RBstart++) {
674 675 676 677
    alloc0 = 0;
    alloc1 = 0;
    alloc2 = 0;
    alloc3 = 0;
678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693
    allocdist0_0_even=0;
    allocdist1_0_even=0;
    allocdist2_0_even=0;
    allocdist3_0_even=0;
    allocdist0_0_odd=0;
    allocdist1_0_odd=0;
    allocdist2_0_odd=0;
    allocdist3_0_odd=0;
    allocdist0_1_even=0;
    allocdist1_1_even=0;
    allocdist2_1_even=0;
    allocdist3_1_even=0;
    allocdist0_1_odd=0;
    allocdist1_1_odd=0;
    allocdist2_1_odd=0;
    allocdist3_1_odd=0;
694

695
    for (Lcrbs=1; Lcrbs<=(100-RBstart); Lcrbs++) {
696

697 698 699 700 701
      nVRB = Lcrbs-1+RBstart;

      if (nVRB<32)
        alloc0 |= (1<<nVRB);
      else if (nVRB<64)
702
        alloc1 |= (1<<(nVRB-32));
703
      else if (nVRB<96)
704
        alloc2 |= (1<<(nVRB-64));
705
      else
706
        alloc3 |= (1<<(nVRB-96));
707 708 709 710

      // Distributed Gap1, even slot
      nVRB_even_dist = get_prb(100,0,nVRB,0);

711
//      if ((RBstart==0) && (Lcrbs<=8))
712
//  printf("nVRB %d => nVRB_even_dist %d\n",nVRB,nVRB_even_dist);
713 714 715 716 717 718 719


      if (nVRB_even_dist<32)
        allocdist0_0_even |= (1<<nVRB_even_dist);
      else if (nVRB_even_dist<64)
        allocdist1_0_even |= (1<<(nVRB_even_dist-32));
      else if (nVRB_even_dist<96)
720
  allocdist2_0_even |= (1<<(nVRB_even_dist-64));
721
      else
722
  allocdist3_0_even |= (1<<(nVRB_even_dist-96));
723
/*      if ((RBstart==0) && (Lcrbs<=8))
724 725 726 727 728 729
  printf("rballoc =>(%08x.%08x.%08x.%08x)\n",
         allocdist0_0_even,
         allocdist1_0_even,
         allocdist2_0_even,
         allocdist3_0_even
         );
730
*/
731 732 733 734 735 736 737
      // Distributed Gap1, odd slot
      nVRB_odd_dist = get_prb(100,1,nVRB,0);
      if (nVRB_odd_dist<32)
        allocdist0_0_odd |= (1<<nVRB_odd_dist);
      else if (nVRB_odd_dist<64)
        allocdist1_0_odd |= (1<<(nVRB_odd_dist-32));
      else if (nVRB_odd_dist<96)
738
  allocdist2_0_odd |= (1<<(nVRB_odd_dist-64));
739
      else
740
  allocdist3_0_odd |= (1<<(nVRB_odd_dist-96));
741 742


743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818
      // Distributed Gap2, even slot
      nVRB_even_dist = get_prb(100,0,nVRB,1);
      if (nVRB_even_dist<32)
        allocdist0_1_even |= (1<<nVRB_even_dist);
      else if (nVRB_even_dist<64)
        allocdist1_1_even |= (1<<(nVRB_even_dist-32));
      else if (nVRB_even_dist<96)
  allocdist2_1_even |= (1<<(nVRB_even_dist-64));
      else
  allocdist3_1_even |= (1<<(nVRB_even_dist-96));


      // Distributed Gap2, odd slot
      nVRB_odd_dist = get_prb(100,1,nVRB,1);
      if (nVRB_odd_dist<32)
        allocdist0_1_odd |= (1<<nVRB_odd_dist);
      else if (nVRB_odd_dist<64)
        allocdist1_1_odd |= (1<<(nVRB_odd_dist-32));
      else if (nVRB_odd_dist<96)
  allocdist2_1_odd |= (1<<(nVRB_odd_dist-64));
      else
  allocdist3_1_odd |= (1<<(nVRB_odd_dist-96));


      RIV=computeRIV(100,RBstart,Lcrbs);

      if (RIV>RIV_max100)
        RIV_max100 = RIV;

      //      printf("RIV %d : first_rb %d NBRB %d\n",RIV,RBstart,Lcrbs);
      localRIV2alloc_LUT100_0[RIV] = alloc0;
      localRIV2alloc_LUT100_1[RIV] = alloc1;
      localRIV2alloc_LUT100_2[RIV] = alloc2;
      localRIV2alloc_LUT100_3[RIV] = alloc3;
      distRIV2alloc_gap0_even_LUT100_0[RIV]  = allocdist0_0_even;
      distRIV2alloc_gap0_even_LUT100_1[RIV]  = allocdist1_0_even;
      distRIV2alloc_gap0_even_LUT100_2[RIV]  = allocdist2_0_even;
      distRIV2alloc_gap0_even_LUT100_3[RIV]  = allocdist3_0_even;
      distRIV2alloc_gap0_odd_LUT100_0[RIV]   = allocdist0_0_odd;
      distRIV2alloc_gap0_odd_LUT100_1[RIV]   = allocdist1_0_odd;
      distRIV2alloc_gap0_odd_LUT100_2[RIV]   = allocdist2_0_odd;
      distRIV2alloc_gap0_odd_LUT100_3[RIV]   = allocdist3_0_odd;
      distRIV2alloc_gap1_even_LUT100_0[RIV]  = allocdist0_1_even;
      distRIV2alloc_gap1_even_LUT100_1[RIV]  = allocdist1_1_even;
      distRIV2alloc_gap1_even_LUT100_2[RIV]  = allocdist2_1_even;
      distRIV2alloc_gap1_even_LUT100_3[RIV]  = allocdist3_1_even;
      distRIV2alloc_gap1_odd_LUT100_0[RIV]   = allocdist0_1_odd;
      distRIV2alloc_gap1_odd_LUT100_1[RIV]   = allocdist1_1_odd;
      distRIV2alloc_gap1_odd_LUT100_2[RIV]   = allocdist2_1_odd;
      distRIV2alloc_gap1_odd_LUT100_3[RIV]   = allocdist3_1_odd;

      RIV2nb_rb_LUT100[RIV]      = Lcrbs;
      RIV2first_rb_LUT100[RIV]   = RBstart;
    }
  }
}

// Ngap = 3, N_VRB_DL=6, P=1, N_row=2, N_null=4*2-6=2
// permutation for even slots :
//    n_PRB'(0,2,4) = (0,1,2), n_PRB'(1,3,5) = (4,5,6)
//    n_PRB''(0,1,2,3) = (0,2,4,6)
//    => n_tilde_PRB(5) = (4)
//       n_tilde_PRB(4) = (1)
//       n_tilde_PRB(2,3) = (3,5)
//       n_tilde_PRB(0,1) = (0,2)


int8_t find_dlsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type)
{
  uint8_t i;
  int8_t first_free_index=-1;

  AssertFatal(eNB!=NULL,"eNB is null\n");
  for (i=0; i<NUMBER_OF_UE_MAX; i++) {
    AssertFatal(eNB->dlsch[i]!=NULL,"eNB->dlsch[%d] is null\n",i);
    AssertFatal(eNB->dlsch[i]!=NULL,"eNB->dlsch[%d][0] is null\n",i);
819
    LOG_D(PHY,"searching for rnti %x : UE index %d=> harq_mask %x, rnti %x, first_free_index %d\n", rnti,i,eNB->dlsch[i][0]->harq_mask,eNB->dlsch[i][0]->rnti,first_free_index);
820
    if ((eNB->dlsch[i][0]->harq_mask >0) &&
821
        (eNB->dlsch[i][0]->rnti==rnti))       return i;
822 823
    else if ((eNB->dlsch[i][0]->harq_mask == 0) && (first_free_index==-1)) first_free_index=i;
  }
824 825
  if (type == SEARCH_EXIST) return -1;
  if (first_free_index != -1)
826
    eNB->dlsch[first_free_index][0]->rnti = 0;
827
  return first_free_index;
828 829 830 831 832 833 834
}

int8_t find_ulsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type)
{
  uint8_t i;
  int8_t first_free_index=-1;

835
  AssertFatal(eNB!=NULL,"eNB is null\n");
836
  for (i=0; i<NUMBER_OF_UE_MAX; i++) {
837
    AssertFatal(eNB->ulsch[i]!=NULL,"eNB->ulsch[%d] is null\n",i);
838
    if ((eNB->ulsch[i]->harq_mask >0) &&
839
        (eNB->ulsch[i]->rnti==rnti))       return i;
840 841
    else if ((eNB->ulsch[i]->harq_mask == 0) && (first_free_index==-1)) first_free_index=i;
  }
842 843
  if (type == SEARCH_EXIST) return -1;
  if (first_free_index != -1)
844
    eNB->ulsch[first_free_index]->rnti = 0;
845
  return first_free_index;
846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868
}


uint32_t get_rballoc(vrb_t vrb_type,uint16_t rb_alloc_dci)
{

  return(localRIV2alloc_LUT25[rb_alloc_dci]);

}

/*
uint8_t get_transmission_mode(module_id_t Mod_id, uint8_t CC_id, rnti_t rnti)
{
  unsigned char UE_id;

  // find the UE_index corresponding to rnti
  UE_id = find_ue(rnti,RC.eNB[Mod_id][CC_id]);
  DevAssert( UE_id != (unsigned char)-1 );

  return(RC.eNB[Mod_id][CC_id]->transmission_mode[UE_id]);
}
*/

869 870 871 872 873
void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_alloc,nfapi_dl_config_dci_dl_pdu *pdu)
{
  LTE_DL_FRAME_PARMS                *fp      = &eNB->frame_parms;
  uint8_t                           *dci_pdu = &dci_alloc->dci_pdu[0];
  nfapi_dl_config_dci_dl_pdu_rel8_t *rel8    = &pdu->dci_dl_pdu_rel8;
874

875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897
  dci_alloc->firstCCE = rel8->cce_idx;
  dci_alloc->L        = rel8->aggregation_level;
  dci_alloc->rnti     = rel8->rnti;
  dci_alloc->harq_pid = rel8->harq_process;
  dci_alloc->ra_flag  = 0;
  dci_alloc->format   = format1A;

  LOG_D(PHY,"NFAPI: DCI format %d, nCCE %d, L %d, rnti %x,harq_pid %d\n",
        rel8->dci_format,rel8->cce_idx,rel8->aggregation_level,rel8->rnti,rel8->harq_process);

  switch (fp->N_RB_DL) {
  case 6:
    if (fp->frame_type == TDD) {
      dci_alloc->dci_length                         = sizeof_DCI1A_1_5MHz_TDD_1_6_t;
      ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->type     = 1;
      ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type = rel8->virtual_resource_block_assignment_flag;
      ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs      = rel8->mcs_1;
      ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi      = rel8->new_data_indicator_1;
      ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
      ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv       = rel8->redundancy_version_1;
      ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC      = rel8->tpc;
      ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process;
      ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->dai      = rel8->downlink_assignment_index;
898
      ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->padding  = 0;
899 900 901 902 903 904 905 906 907 908
    } else {
      dci_alloc->dci_length                         = sizeof_DCI1A_1_5MHz_FDD_t;
      ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->type         = 1;
      ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->vrb_type     = rel8->virtual_resource_block_assignment_flag;
      ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs          = rel8->mcs_1;
      ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->ndi          = rel8->new_data_indicator_1;
      ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc      = rel8->resource_block_coding;
      ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv           = rel8->redundancy_version_1;
      ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC          = rel8->tpc;
      ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid     = rel8->harq_process;
909
      ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->padding      = 0;
910 911 912 913 914 915 916 917 918 919 920 921 922 923
      //      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
    }
    break;
  case 25:
    if (fp->frame_type == TDD) {
      dci_alloc->dci_length                         = sizeof_DCI1A_5MHz_TDD_1_6_t;
      ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->type       = 1;
      ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type   = rel8->virtual_resource_block_assignment_flag;
      ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs        = rel8->mcs_1;
      ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->ndi        = rel8->new_data_indicator_1;
      ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc    = rel8->resource_block_coding;
      ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv         = rel8->redundancy_version_1;
      ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC        = rel8->tpc;
      ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid   = rel8->harq_process;
924 925
      ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->dai        = rel8->downlink_assignment_index;
      ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->padding    = 0;
926 927 928 929 930 931 932 933 934 935 936
       //        printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
    } else {
      dci_alloc->dci_length                         = sizeof_DCI1A_5MHz_FDD_t;
      ((DCI1A_5MHz_FDD_t *)dci_pdu)->type           = 1;
      ((DCI1A_5MHz_FDD_t *)dci_pdu)->vrb_type       = rel8->virtual_resource_block_assignment_flag;
      ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs            = rel8->mcs_1;
      ((DCI1A_5MHz_FDD_t *)dci_pdu)->ndi            = rel8->new_data_indicator_1;
      ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc        = rel8->resource_block_coding;
      ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv             = rel8->redundancy_version_1;
      ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC            = rel8->tpc;
      ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid       = rel8->harq_process;
937
      ((DCI1A_5MHz_FDD_t *)dci_pdu)->padding        = 0;
938 939 940 941 942 943 944 945 946 947 948 949 950 951 952
      //      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
    }
    break;
  case 50:
    if (fp->frame_type == TDD) {
      dci_alloc->dci_length                         = sizeof_DCI1A_10MHz_TDD_1_6_t;
      ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->type      = 1;
      ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->vrb_type  = rel8->virtual_resource_block_assignment_flag;
      ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs       = rel8->mcs_1;
      ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->ndi       = rel8->new_data_indicator_1;
      ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
      ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv        = rel8->redundancy_version_1;
      ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC       = rel8->tpc;
      ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid  = rel8->harq_process;
      ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->dai       = rel8->downlink_assignment_index;
953
      ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->padding   = 0;
954 955 956 957 958 959 960 961 962 963 964
      //        printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
    } else {
      dci_alloc->dci_length                         = sizeof_DCI1A_10MHz_FDD_t;
      ((DCI1A_10MHz_FDD_t *)dci_pdu)->type          = 1;
      ((DCI1A_10MHz_FDD_t *)dci_pdu)->vrb_type      = rel8->virtual_resource_block_assignment_flag;
      ((DCI1A_10MHz_FDD_t *)dci_pdu)->mcs           = rel8->mcs_1;
      ((DCI1A_10MHz_FDD_t *)dci_pdu)->ndi           = rel8->new_data_indicator_1;
      ((DCI1A_10MHz_FDD_t *)dci_pdu)->rballoc       = rel8->resource_block_coding;
      ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv            = rel8->redundancy_version_1;
      ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC           = rel8->tpc;
      ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid      = rel8->harq_process;
965
      ((DCI1A_10MHz_FDD_t *)dci_pdu)->padding       = 0;
966 967 968 969 970 971 972 973 974 975 976 977 978 979 980
      //      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
    }
    break;
  case 100:
    if (fp->frame_type == TDD) {
      dci_alloc->dci_length                         = sizeof_DCI1A_20MHz_TDD_1_6_t;
      ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->type      = 1;
      ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->vrb_type  = rel8->virtual_resource_block_assignment_flag;
      ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->mcs       = rel8->mcs_1;
      ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->ndi       = rel8->new_data_indicator_1;
      ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
      ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rv        = rel8->redundancy_version_1;
      ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC       = rel8->tpc;
      ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid  = rel8->harq_process;
      ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->dai       = rel8->downlink_assignment_index;
981
      ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->padding   = 0;
982 983 984 985 986 987 988 989 990 991 992
      //        printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
    } else {
      dci_alloc->dci_length                         = sizeof_DCI1A_20MHz_FDD_t;
      ((DCI1A_20MHz_FDD_t *)dci_pdu)->type          = 1;
      ((DCI1A_20MHz_FDD_t *)dci_pdu)->vrb_type      = rel8->virtual_resource_block_assignment_flag;
      ((DCI1A_20MHz_FDD_t *)dci_pdu)->mcs           = rel8->mcs_1;
      ((DCI1A_20MHz_FDD_t *)dci_pdu)->ndi           = rel8->new_data_indicator_1;
      ((DCI1A_20MHz_FDD_t *)dci_pdu)->rballoc       = rel8->resource_block_coding;
      ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv            = rel8->redundancy_version_1;
      ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC           = rel8->tpc;
      ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid      = rel8->harq_process;
993
      ((DCI1A_20MHz_FDD_t *)dci_pdu)->padding       = 0;
994 995 996 997
      //      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
    }
    break;
  }
998

999 1000 1001 1002
  LOG_I(PHY,"%d.%d: DCI 1A: rnti %x, PDCCH order to do PRACH\n",
        proc->frame_tx, proc->subframe_tx, rel8->rnti);
}

1003
void fill_dci_and_dlsch(PHY_VARS_eNB *eNB,int frame,int subframe,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_alloc,nfapi_dl_config_dci_dl_pdu *pdu)
1004 1005
{
  LTE_DL_FRAME_PARMS *fp = &eNB->frame_parms;
1006 1007
  uint8_t *dci_pdu = &dci_alloc->dci_pdu[0];
  nfapi_dl_config_dci_dl_pdu_rel8_t *rel8 = &pdu->dci_dl_pdu_rel8;
1008

1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022
  /* check if this is a DCI 1A PDCCH order for RAPROC */
  if (rel8->dci_format == NFAPI_DL_DCI_FORMAT_1A && rel8->rnti_type == 1) {
    int full_rb;
    switch (fp->N_RB_DL) {
    case 6:   full_rb = 63;   break;
    case 25:  full_rb = 511;  break;
    case 50:  full_rb = 2047; break;
    case 100: full_rb = 8191; break;
    default:  abort();
    }
    if (rel8->resource_block_coding == full_rb)
      return fill_pdcch_order(eNB, proc, dci_alloc, pdu);
  }

1023 1024 1025 1026 1027 1028 1029 1030 1031
  LTE_eNB_DLSCH_t *dlsch0=NULL,*dlsch1=NULL;
  LTE_DL_eNB_HARQ_t *dlsch0_harq=NULL,*dlsch1_harq=NULL;
  int beamforming_mode = 0;
  int UE_id=-1;
  int NPRB;
  int TB0_active;
  int TB1_active;
  uint16_t DL_pmi_single=0; // This should be taken from DLSCH parameters for PUSCH precoding
  uint8_t I_mcs = 0;
1032
 
1033 1034 1035 1036 1037 1038
  dci_alloc->firstCCE = rel8->cce_idx;
  dci_alloc->L        = rel8->aggregation_level;
  dci_alloc->rnti     = rel8->rnti;
  dci_alloc->harq_pid = rel8->harq_process;
  dci_alloc->ra_flag  = 0;

1039 1040
  LOG_D(PHY,"NFAPI: SFN/SF:%04d%d proc:TX:[SFN/SF:%04d%d] DCI format %d, nCCE %d, L %d, rnti %x, harq_pid %d\n",
	frame,subframe,proc->frame_tx,proc->subframe_tx,rel8->dci_format,rel8->cce_idx,rel8->aggregation_level,rel8->rnti,rel8->harq_process);
1041 1042 1043 1044 1045 1046 1047
  if ((rel8->rnti_type == 2 ) && (rel8->rnti != SI_RNTI) && (rel8->rnti != P_RNTI)) dci_alloc->ra_flag = 1;

  UE_id = find_dlsch(rel8->rnti,eNB,SEARCH_EXIST_OR_FREE);
  AssertFatal(UE_id!=-1,"no free or exiting dlsch_context\n");
  AssertFatal(UE_id<NUMBER_OF_UE_MAX,"returned UE_id %d >= %d(NUMBER_OF_UE_MAX)\n",UE_id,NUMBER_OF_UE_MAX);
  dlsch0 = eNB->dlsch[UE_id][0];
  dlsch1 = eNB->dlsch[UE_id][1];
1048 1049

    
1050 1051 1052 1053 1054
  beamforming_mode                          = eNB->transmission_mode[(uint8_t)UE_id]<7?0:eNB->transmission_mode[(uint8_t)UE_id];
  dlsch0_harq                               = dlsch0->harq_processes[rel8->harq_process];
  dlsch0_harq->codeword                     = 0;
  dlsch1_harq                               = dlsch1->harq_processes[rel8->harq_process];
  dlsch1_harq->codeword                     = 1;
1055
  dlsch0->subframe_tx[subframe]             = 1;
1056 1057 1058 1059 1060 1061 1062 1063

  LOG_D(PHY,"NFAPI: SFN/SF:%04d%d proc:TX:SFN/SF:%04d%d dlsch0[rnti:%x harq_mask:%04x] dci_pdu[rnti:%x rnti_type:%d harq_process:%d ndi1:%d] dlsch0_harq[round:%d harq_mask:%x ndi:%d]\n", 
      frame,subframe,
      proc->frame_tx,proc->subframe_tx,
      dlsch0->rnti,dlsch0->harq_mask,
      rel8->rnti, rel8->rnti_type, rel8->harq_process, rel8->new_data_indicator_1,
      dlsch0_harq->round, dlsch0->harq_mask, dlsch0_harq->ndi);

1064 1065 1066 1067
  if (dlsch0->rnti != rel8->rnti) { // if rnti of dlsch is not the same as in the config, this is a new entry
    dlsch0_harq->round=0;
    dlsch0->harq_mask=0;
  }
1068 1069 1070 1071 1072 1073 1074
  if ((dlsch0->harq_mask & (1<<rel8->harq_process)) > 0 ) {
    if (rel8->new_data_indicator_1 != dlsch0_harq->ndi)
      dlsch0_harq->round=0;
  }
  else  { // process is inactive, so activate and set round to 0
    dlsch0_harq->round=0;
  }
1075 1076
  dlsch0_harq->ndi = rel8->new_data_indicator_1;

1077 1078 1079
  dlsch0->active        = 1;
  if (rel8->rnti_type == 2)
      dlsch0_harq->round    = 0;
1080 1081 1082 1083 1084 1085

  LOG_D(PHY,"NFAPI: rel8[rnti %x dci_format %d harq_process %d ndi1 %d rnti type %d] dlsch0[rnti %x harq_mask %x] dlsch0_harq[round %d ndi %d]\n",
      rel8->rnti,rel8->dci_format,rel8->harq_process, rel8->new_data_indicator_1, rel8->rnti_type,
      dlsch0->rnti,dlsch0->harq_mask,
      dlsch0_harq->round,dlsch0_harq->ndi
      );
1086

1087 1088 1089
  switch (rel8->dci_format) {

  case NFAPI_DL_DCI_FORMAT_1A:
1090

1091 1092
      AssertFatal(rel8->resource_block_coding < 8192, "SFN/SF:%04d%d proc:TX:SFN/SF:%04d%d: rel8->resource_block_coding (%p) %u >= 8192 (rnti %x, rnti_type %d, format %d, harq_id %d\n",
                frame,subframe,proc->frame_tx,subframe,
1093 1094 1095
                &rel8->resource_block_coding,rel8->resource_block_coding,rel8->rnti,rel8->rnti_type,rel8->dci_format,rel8->harq_process);
  

1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110
    dci_alloc->format     = format1A;

    switch (fp->N_RB_DL) {
    case 6:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                         = sizeof_DCI1A_1_5MHz_TDD_1_6_t; 
        ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->type     = 1;
        ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type = rel8->virtual_resource_block_assignment_flag;
        ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs      = rel8->mcs_1;
        ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi      = rel8->new_data_indicator_1;
        ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv       = rel8->redundancy_version_1;
        ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process;
        ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->dai      = rel8->downlink_assignment_index;
1111
        ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->padding  = 0;
1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122
	
      } else {
	dci_alloc->dci_length                         = sizeof_DCI1A_1_5MHz_FDD_t; 
	((DCI1A_1_5MHz_FDD_t *)dci_pdu)->type         = 1;
        ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->vrb_type     = rel8->virtual_resource_block_assignment_flag;
        ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs          = rel8->mcs_1;
        ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->ndi          = rel8->new_data_indicator_1;
        ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc      = rel8->resource_block_coding;
        ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv           = rel8->redundancy_version_1;
        ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC          = rel8->tpc;
        ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid     = rel8->harq_process;
1123
        ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->padding      = 0;
1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141
        //      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      AssertFatal(rel8->virtual_resource_block_assignment_flag==LOCALIZED,"Distributed RB allocation not done yet\n");
      dlsch0_harq->rb_alloc[0]    = localRIV2alloc_LUT6[rel8->resource_block_coding];
      dlsch0_harq->vrb_type           =  rel8->virtual_resource_block_assignment_flag;
      dlsch0_harq->nb_rb          = RIV2nb_rb_LUT6[rel8->resource_block_coding];//NPRB;
      break;
    case 25:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                         = sizeof_DCI1A_5MHz_TDD_1_6_t; 
        ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->type       = 1;
        ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type   = rel8->virtual_resource_block_assignment_flag;
        ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs        = rel8->mcs_1;
        ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->ndi        = rel8->new_data_indicator_1;
        ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc    = rel8->resource_block_coding;
        ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv         = rel8->redundancy_version_1;
        ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC        = rel8->tpc;
        ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid   = rel8->harq_process;
1142 1143
        ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->dai        = rel8->downlink_assignment_index;
        ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->padding    = 0;
1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154
         //        printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                         = sizeof_DCI1A_5MHz_FDD_t; 
	((DCI1A_5MHz_FDD_t *)dci_pdu)->type           = 1;
        ((DCI1A_5MHz_FDD_t *)dci_pdu)->vrb_type       = rel8->virtual_resource_block_assignment_flag;
        ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs            = rel8->mcs_1;
        ((DCI1A_5MHz_FDD_t *)dci_pdu)->ndi            = rel8->new_data_indicator_1;
        ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc        = rel8->resource_block_coding;
        ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv             = rel8->redundancy_version_1;
        ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC            = rel8->tpc;
        ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid       = rel8->harq_process;
1155
        ((DCI1A_5MHz_FDD_t *)dci_pdu)->padding        = 0;
1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173
        //      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      AssertFatal(rel8->virtual_resource_block_assignment_flag==LOCALIZED,"Distributed RB allocation not done yet\n");
      dlsch0_harq->rb_alloc[0]    = localRIV2alloc_LUT25[rel8->resource_block_coding];
      dlsch0_harq->vrb_type           =  rel8->virtual_resource_block_assignment_flag;
      dlsch0_harq->nb_rb          = RIV2nb_rb_LUT25[rel8->resource_block_coding];//NPRB;
      break;
    case 50:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                         = sizeof_DCI1A_10MHz_TDD_1_6_t; 
        ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->type      = 1;
        ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->vrb_type  = rel8->virtual_resource_block_assignment_flag;
        ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs       = rel8->mcs_1;
        ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->ndi       = rel8->new_data_indicator_1;
        ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
        ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv        = rel8->redundancy_version_1;
        ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC       = rel8->tpc;
        ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid  = rel8->harq_process;
1174 1175
        ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->dai       = rel8->downlink_assignment_index;
        ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->padding   = 0;
1176 1177
        //        printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
1178
	dci_alloc->dci_length                         = sizeof_DCI1A_10MHz_FDD_t; 
1179 1180 1181 1182 1183 1184 1185 1186
	((DCI1A_10MHz_FDD_t *)dci_pdu)->type          = 1;
        ((DCI1A_10MHz_FDD_t *)dci_pdu)->vrb_type      = rel8->virtual_resource_block_assignment_flag;
        ((DCI1A_10MHz_FDD_t *)dci_pdu)->mcs           = rel8->mcs_1;
        ((DCI1A_10MHz_FDD_t *)dci_pdu)->ndi           = rel8->new_data_indicator_1;
        ((DCI1A_10MHz_FDD_t *)dci_pdu)->rballoc       = rel8->resource_block_coding;
        ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv            = rel8->redundancy_version_1;
        ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC           = rel8->tpc;
        ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid      = rel8->harq_process;
1187
        ((DCI1A_10MHz_FDD_t *)dci_pdu)->padding       = 0;
1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206
	//      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      AssertFatal(rel8->virtual_resource_block_assignment_flag==LOCALIZED,"Distributed RB allocation not done yet\n");
      dlsch0_harq->rb_alloc[0]     = localRIV2alloc_LUT50_0[rel8->resource_block_coding];
      dlsch0_harq->rb_alloc[1]     = localRIV2alloc_LUT50_1[rel8->resource_block_coding];
      dlsch0_harq->vrb_type           =  rel8->virtual_resource_block_assignment_flag;
      dlsch0_harq->nb_rb              = RIV2nb_rb_LUT50[rel8->resource_block_coding];//NPRB;
      break;
    case 100:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                         = sizeof_DCI1A_20MHz_TDD_1_6_t; 
        ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->type      = 1;
        ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->vrb_type  = rel8->virtual_resource_block_assignment_flag;
        ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->mcs       = rel8->mcs_1;
        ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->ndi       = rel8->new_data_indicator_1;
        ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
        ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rv        = rel8->redundancy_version_1;
        ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC       = rel8->tpc;
        ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid  = rel8->harq_process;
1207 1208
        ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->dai       = rel8->downlink_assignment_index;
        ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->padding   = 0;
1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219
        //        printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                         = sizeof_DCI1A_20MHz_FDD_t; 
	((DCI1A_20MHz_FDD_t *)dci_pdu)->type          = 1;
        ((DCI1A_20MHz_FDD_t *)dci_pdu)->vrb_type      = rel8->virtual_resource_block_assignment_flag;
        ((DCI1A_20MHz_FDD_t *)dci_pdu)->mcs           = rel8->mcs_1;
        ((DCI1A_20MHz_FDD_t *)dci_pdu)->ndi           = rel8->new_data_indicator_1;
        ((DCI1A_20MHz_FDD_t *)dci_pdu)->rballoc       = rel8->resource_block_coding;
        ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv            = rel8->redundancy_version_1;
        ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC           = rel8->tpc;
        ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid      = rel8->harq_process;
1220
        ((DCI1A_20MHz_FDD_t *)dci_pdu)->padding       = 0;
1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242
	//      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      AssertFatal(rel8->virtual_resource_block_assignment_flag==LOCALIZED,"Distributed RB allocation not done yet\n");
      dlsch0_harq->rb_alloc[0]      = localRIV2alloc_LUT100_0[rel8->resource_block_coding];
      dlsch0_harq->rb_alloc[1]      = localRIV2alloc_LUT100_1[rel8->resource_block_coding];
      dlsch0_harq->rb_alloc[2]      = localRIV2alloc_LUT100_2[rel8->resource_block_coding];
      dlsch0_harq->rb_alloc[3]      = localRIV2alloc_LUT100_3[rel8->resource_block_coding];
      dlsch0_harq->vrb_type         =  rel8->virtual_resource_block_assignment_flag;
      dlsch0_harq->nb_rb            = RIV2nb_rb_LUT100[rel8->resource_block_coding];//NPRB;
      break;
    }

    if (rel8->rnti_type == 2 ) {
      // see 36-212 V8.6.0 p. 45
      NPRB      = (rel8->tpc&1)+2;
      // 36-213 sec.7.1.7.2 p.26
      I_mcs     = rel8->mcs_1;
    }
    else {
      NPRB      = dlsch0_harq->nb_rb;
      I_mcs     = get_I_TBS(rel8->mcs_1);
    }
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    AssertFatal(NPRB>0,"DCI 1A: NPRB = 0 (rnti %x, rnti type %d, tpc %d, round %d, resource_block_coding %d, harq process %d)\n",rel8->rnti,rel8->rnti_type,rel8->tpc,dlsch0_harq->round,rel8->resource_block_coding,rel8->harq_process);
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    dlsch0_harq->rvidx         = rel8->redundancy_version_1;
    dlsch0_harq->Nl            = 1;
    dlsch0_harq->mimo_mode     = (fp->nb_antenna_ports_eNB == 1) ? SISO : ALAMOUTI;
    dlsch0_harq->dl_power_off  = 1;
    
    

    dlsch0_harq->mcs             = rel8->mcs_1;
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    dlsch0_harq->Qm              = 2;
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    dlsch0_harq->TBS             = TBStable[I_mcs][NPRB-1];
    dlsch0->harq_ids[subframe]   = rel8->harq_process;
    dlsch0->active               = 1;
    dlsch0->rnti                 = rel8->rnti;
    dlsch0->harq_ids[subframe]   = rel8->harq_process;
    if (dlsch0_harq->round == 0)
      dlsch0_harq->status = ACTIVE;

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    dlsch0->harq_mask            |= (1<<rel8->harq_process);

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    if (rel8->rnti_type == 1) LOG_I(PHY,"DCI 1A: round %d, mcs %d, rballoc %x, rv %d, rnti %x, harq process %d\n",dlsch0_harq->round,rel8->mcs_1,rel8->resource_block_coding,rel8->redundancy_version_1,rel8->rnti,rel8->harq_process);
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    break;
  case NFAPI_DL_DCI_FORMAT_1:

    dci_alloc->format           = format1;
    dlsch0->active              = 1;
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    LOG_D(PHY,"SFN/SF:%04d%d proc:TX:SFN/SF:%04d%d: Programming DLSCH for Format 1 DCI, harq_pid %d\n",frame,subframe,proc->frame_tx,subframe,rel8->harq_process);
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    switch (fp->N_RB_DL) {
    case 6:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                     = sizeof_DCI1_1_5MHz_TDD_t; 
        ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rah       = rel8->resource_allocation_type;
        ((DCI1_1_5MHz_TDD_t *)dci_pdu)->mcs       = rel8->mcs_1;
        ((DCI1_1_5MHz_TDD_t *)dci_pdu)->ndi       = rel8->new_data_indicator_1;
        ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
        ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rv        = rel8->redundancy_version_1;
        ((DCI1_1_5MHz_TDD_t *)dci_pdu)->TPC       = rel8->tpc;
        ((DCI1_1_5MHz_TDD_t *)dci_pdu)->harq_pid  = rel8->harq_process;
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        ((DCI1_1_5MHz_TDD_t *)dci_pdu)->dai       = rel8->downlink_assignment_index;
        ((DCI1_1_5MHz_TDD_t *)dci_pdu)->padding   = 0;
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        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                         = sizeof_DCI1_1_5MHz_FDD_t; 
        ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rah           = rel8->resource_allocation_type;
        ((DCI1_1_5MHz_FDD_t *)dci_pdu)->mcs           = rel8->mcs_1;
        ((DCI1_1_5MHz_FDD_t *)dci_pdu)->ndi       = rel8->new_data_indicator_1;
        ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rballoc       = rel8->resource_block_coding;
        ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rv            = rel8->redundancy_version_1;
        ((DCI1_1_5MHz_FDD_t *)dci_pdu)->TPC           = rel8->tpc;
        ((DCI1_1_5MHz_FDD_t *)dci_pdu)->harq_pid      = rel8->harq_process;
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        ((DCI1_1_5MHz_FDD_t *)dci_pdu)->padding       = 0;
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        //      printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      break;
    case 25:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                      = sizeof_DCI1_5MHz_TDD_t; 
        ((DCI1_5MHz_TDD_t *)dci_pdu)->rah      = rel8->resource_allocation_type;
        ((DCI1_5MHz_TDD_t *)dci_pdu)->mcs      = rel8->mcs_1;
        ((DCI1_5MHz_TDD_t *)dci_pdu)->ndi      = rel8->new_data_indicator_1;
        ((DCI1_5MHz_TDD_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI1_5MHz_TDD_t *)dci_pdu)->rv       = rel8->redundancy_version_1;
        ((DCI1_5MHz_TDD_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI1_5MHz_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
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        ((DCI1_5MHz_TDD_t *)dci_pdu)->dai      = rel8->downlink_assignment_index;
        ((DCI1_5MHz_TDD_t *)dci_pdu)->padding  = 0;
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        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                  = sizeof_DCI1_5MHz_FDD_t; 
        ((DCI1_5MHz_FDD_t *)dci_pdu)->rah      = rel8->resource_allocation_type;
        ((DCI1_5MHz_FDD_t *)dci_pdu)->mcs      = rel8->mcs_1;
        ((DCI1_5MHz_FDD_t *)dci_pdu)->ndi      = rel8->new_data_indicator_1;
        ((DCI1_5MHz_FDD_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI1_5MHz_FDD_t *)dci_pdu)->rv       = rel8->redundancy_version_1;
        ((DCI1_5MHz_FDD_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI1_5MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
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        ((DCI1_5MHz_FDD_t *)dci_pdu)->padding  = 0;
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        //      printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      break;
    case 50:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                       = sizeof_DCI1_10MHz_TDD_t; 
        ((DCI1_10MHz_TDD_t *)dci_pdu)->rah      = rel8->resource_allocation_type;
        ((DCI1_10MHz_TDD_t *)dci_pdu)->mcs      = rel8->mcs_1;
        ((DCI1_10MHz_TDD_t *)dci_pdu)->ndi      = rel8->new_data_indicator_1;
        ((DCI1_10MHz_TDD_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI1_10MHz_TDD_t *)dci_pdu)->rv       = rel8->redundancy_version_1;
        ((DCI1_10MHz_TDD_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI1_10MHz_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
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        ((DCI1_10MHz_TDD_t *)dci_pdu)->dai      = rel8->downlink_assignment_index;
        ((DCI1_10MHz_TDD_t *)dci_pdu)->padding  = 0;
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        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                   = sizeof_DCI1_10MHz_FDD_t; 
        ((DCI1_10MHz_FDD_t *)dci_pdu)->rah      = rel8->resource_allocation_type;
        ((DCI1_10MHz_FDD_t *)dci_pdu)->mcs      = rel8->mcs_1;
        ((DCI1_10MHz_FDD_t *)dci_pdu)->ndi      = rel8->new_data_indicator_1;
        ((DCI1_10MHz_FDD_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI1_10MHz_FDD_t *)dci_pdu)->rv       = rel8->redundancy_version_1;
        ((DCI1_10MHz_FDD_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI1_10MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
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        ((DCI1_10MHz_FDD_t *)dci_pdu)->padding  = 0;
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      }
      break;
    case 100:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                       = sizeof_DCI1_20MHz_TDD_t; 
        ((DCI1_20MHz_TDD_t *)dci_pdu)->rah      = rel8->resource_allocation_type;
        ((DCI1_20MHz_TDD_t *)dci_pdu)->mcs      = rel8->mcs_1;
        ((DCI1_20MHz_TDD_t *)dci_pdu)->ndi      = rel8->new_data_indicator_1;
        ((DCI1_20MHz_TDD_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI1_20MHz_TDD_t *)dci_pdu)->rv       = rel8->redundancy_version_1;
        ((DCI1_20MHz_TDD_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI1_20MHz_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
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        ((DCI1_20MHz_TDD_t *)dci_pdu)->dai      = rel8->downlink_assignment_index;
        ((DCI1_20MHz_TDD_t *)dci_pdu)->padding  = 0;
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        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                   = sizeof_DCI1_20MHz_FDD_t; 
        ((DCI1_20MHz_FDD_t *)dci_pdu)->rah      = rel8->resource_allocation_type;
        ((DCI1_20MHz_FDD_t *)dci_pdu)->mcs      = rel8->mcs_1;
        ((DCI1_20MHz_FDD_t *)dci_pdu)->ndi      = rel8->new_data_indicator_1;
        ((DCI1_20MHz_FDD_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI1_20MHz_FDD_t *)dci_pdu)->rv       = rel8->redundancy_version_1;
        ((DCI1_20MHz_FDD_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI1_20MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
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        ((DCI1_20MHz_FDD_t *)dci_pdu)->padding  = 0;
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      }
      break;
    }

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    AssertFatal(rel8->harq_process<8,"Format 1: harq_pid=%d >= 8\n", rel8->harq_process);

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    dlsch0_harq = dlsch0->harq_processes[rel8->harq_process];
    dlsch0_harq->codeword=0;

    // printf("DCI: Setting subframe_tx for subframe %d\n",subframe);
    dlsch0->subframe_tx[subframe] = 1;

    conv_rballoc(rel8->resource_allocation_type,
                 rel8->resource_block_coding,
		 fp->N_RB_DL,
                 dlsch0_harq->rb_alloc);

    dlsch0_harq->nb_rb = conv_nprb(rel8->resource_allocation_type,
                                   rel8->resource_block_coding,
                                   fp->N_RB_DL);

    NPRB      = dlsch0_harq->nb_rb;


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    AssertFatal(NPRB>0,"NPRB == 0\n");
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    dlsch0_harq->rvidx       = rel8->redundancy_version_1;

    dlsch0_harq->Nl          = 1;
    //    dlsch[0]->layer_index = 0;
    if (beamforming_mode == 0)
      dlsch0_harq->mimo_mode = (fp->nb_antenna_ports_eNB == 1) ? SISO : ALAMOUTI;
    else if (beamforming_mode == 7)
      dlsch0_harq->mimo_mode = TM7;
    else
      LOG_E(PHY,"Invalid beamforming mode %dL\n", beamforming_mode);

    dlsch0_harq->dl_power_off = 1;

    dlsch0->active = 1;



    if (dlsch0_harq->round == 0) {
      dlsch0_harq->status = ACTIVE;
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      //            printf("Setting DLSCH process %d to ACTIVE\n",rel8->harq_process);
      // MCS and TBS don't change across HARQ rounds
      dlsch0_harq->mcs         = rel8->mcs_1;
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      dlsch0_harq->Qm          = get_Qm(rel8->mcs_1);
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      dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][NPRB-1];

    }

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    LOG_D(PHY,"DCI: Set harq_ids[%d] to %d (%p)\n",subframe,rel8->harq_process,dlsch0);
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    dlsch0->harq_ids[subframe] = rel8->harq_process;

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    dlsch0->harq_mask          |= (1<<rel8->harq_process);
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    dlsch0->rnti = rel8->rnti;


    break;
  case NFAPI_DL_DCI_FORMAT_2A:

    dci_alloc->format     = format2A;
    switch (fp->N_RB_DL) {
    case 6:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                         = sizeof_DCI2A_1_5MHz_2A_TDD_t; 
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rah      = rel8->resource_allocation_type;
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->mcs1     = rel8->mcs_1;
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->mcs2     = rel8->mcs_2;
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->ndi1     = rel8->new_data_indicator_1;
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->ndi2     = rel8->new_data_indicator_2;
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rv1      = rel8->redundancy_version_1;
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rv2      = rel8->redundancy_version_2;
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
	((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap  = rel8->transport_block_to_codeword_swap_flag;
        ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->dai      = rel8->downlink_assignment_index;
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        /* there is no padding in this structure, it is exactly 32 bits */
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        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                         = sizeof_DCI2A_1_5MHz_2A_FDD_t; 
        ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rah          = rel8->resource_allocation_type;
        ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->mcs1         = rel8->mcs_1;
        ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->mcs2         = rel8->mcs_2;
        ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->ndi1         = rel8->new_data_indicator_1;
        ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->ndi2         = rel8->new_data_indicator_2;
        ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rballoc      = rel8->resource_block_coding;
        ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rv1          = rel8->redundancy_version_1;
        ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rv2          = rel8->redundancy_version_2;
        ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->TPC          = rel8->tpc;
        ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid     = rel8->harq_process;
	((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap      = rel8->transport_block_to_codeword_swap_flag;
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	((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->padding      = 0;
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        //      printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      break;
    case 25:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                        = sizeof_DCI2A_5MHz_2A_TDD_t; 
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rah       = rel8->resource_allocation_type;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->mcs1      = rel8->mcs_1;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->mcs2      = rel8->mcs_2;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->ndi1      = rel8->new_data_indicator_1;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->ndi2      = rel8->new_data_indicator_2;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv1       = rel8->redundancy_version_1;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv2       = rel8->redundancy_version_2;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->TPC       = rel8->tpc;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->harq_pid  = rel8->harq_process;
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	((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->tb_swap   = rel8->transport_block_to_codeword_swap_flag;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->dai       = rel8->downlink_assignment_index;
        ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->padding   = 0;
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        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                           = sizeof_DCI2A_5MHz_2A_FDD_t; 
        ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rah           = rel8->resource_allocation_type;
        ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->mcs1          = rel8->mcs_1;
        ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->mcs2          = rel8->mcs_2;
        ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->ndi1          = rel8->new_data_indicator_1;
        ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->ndi2          = rel8->new_data_indicator_2;
        ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rballoc       = rel8->resource_block_coding;
        ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rv1           = rel8->redundancy_version_1;
        ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rv2           = rel8->redundancy_version_2;
        ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->TPC           = rel8->tpc;
        ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->harq_pid      = rel8->harq_process;
	((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->tb_swap       = rel8->transport_block_to_codeword_swap_flag;	
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	((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->padding       = 0;
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        //      printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      break;
    case 50:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                        = sizeof_DCI2A_10MHz_2A_TDD_t; 
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rah      = rel8->resource_allocation_type;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->mcs1     = rel8->mcs_1;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->mcs2     = rel8->mcs_2;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->ndi1     = rel8->new_data_indicator_1;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->ndi2     = rel8->new_data_indicator_2;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv1      = rel8->redundancy_version_1;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv2      = rel8->redundancy_version_2;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
1524 1525 1526
	((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->tb_swap  = rel8->transport_block_to_codeword_swap_flag;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->dai      = rel8->downlink_assignment_index;
        ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->padding  = 0;
1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539
        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                        = sizeof_DCI2A_10MHz_2A_FDD_t; 
        ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rah       = rel8->resource_allocation_type;
        ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->mcs1      = rel8->mcs_1;
        ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->mcs2      = rel8->mcs_2;
        ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->ndi1      = rel8->new_data_indicator_1;
        ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->ndi2      = rel8->new_data_indicator_2;
        ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
        ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv1       = rel8->redundancy_version_1;
        ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv2       = rel8->redundancy_version_2;
        ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->TPC       = rel8->tpc;
        ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->harq_pid  = rel8->harq_process;
1540 1541
	((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->tb_swap   = rel8->transport_block_to_codeword_swap_flag;
	((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->padding   = 0;
1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
      }
      break;
    case 100:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                        = sizeof_DCI2A_20MHz_2A_TDD_t; 
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rah       = rel8->resource_allocation_type;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->mcs1      = rel8->mcs_1;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->mcs2      = rel8->mcs_2;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->ndi1      = rel8->new_data_indicator_1;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->ndi2      = rel8->new_data_indicator_2;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv1       = rel8->redundancy_version_1;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv2       = rel8->redundancy_version_2;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->TPC       = rel8->tpc;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->harq_pid  = rel8->harq_process;
1557 1558 1559
	((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->tb_swap   = rel8->transport_block_to_codeword_swap_flag;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->dai       = rel8->downlink_assignment_index;
        ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->padding   = 0;
1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572
        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                           = sizeof_DCI2A_20MHz_2A_FDD_t; 
        ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rah          = rel8->resource_allocation_type;
        ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->mcs1         = rel8->mcs_1;
        ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->mcs2         = rel8->mcs_2;
        ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->ndi1         = rel8->new_data_indicator_1;
        ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->ndi2         = rel8->new_data_indicator_2;
        ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rballoc      = rel8->resource_block_coding;
        ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv1          = rel8->redundancy_version_1;
        ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv2          = rel8->redundancy_version_2;
        ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->TPC          = rel8->tpc;
        ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->harq_pid     = rel8->harq_process;
1573 1574
	((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->tb_swap      = rel8->transport_block_to_codeword_swap_flag;
	((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->padding      = 0;
1575 1576 1577 1578
      }
      break;

    }
1579 1580

    AssertFatal(rel8->harq_process<8,"Format 2_2A: harq_pid=%d >= 8\n", rel8->harq_process);
1581 1582 1583 1584


    // Flip the TB to codeword mapping as described in 5.3.3.1.5 of 36-212 V11.3.0
    // note that we must set tbswap=0 in eNB scheduler if one TB is deactivated
1585

1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612
    // This must be set as in TM4, does not work properly now.
    if (rel8->transport_block_to_codeword_swap_flag == 1) {
      dlsch0 = eNB->dlsch[UE_id][1];
      dlsch1 = eNB->dlsch[UE_id][0];
    }

    dlsch0_harq = dlsch0->harq_processes[rel8->harq_process];
    dlsch1_harq = dlsch1->harq_processes[rel8->harq_process];

    dlsch0->subframe_tx[subframe] = 1;

    dlsch0->harq_ids[subframe] = rel8->harq_process;
    dlsch1->harq_ids[subframe] = rel8->harq_process;
    //    printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);


    conv_rballoc(rel8->resource_allocation_type,
                 rel8->resource_block_coding,
                 fp->N_RB_DL,
                 dlsch0_harq->rb_alloc);

    dlsch1_harq->rb_alloc[0]                         = dlsch0_harq->rb_alloc[0];
    dlsch0_harq->nb_rb                               = conv_nprb(rel8->resource_allocation_type,
								 rel8->resource_block_coding,
								 fp->N_RB_DL);
    dlsch1_harq->nb_rb                               = dlsch0_harq->nb_rb;

1613
    AssertFatal(dlsch0_harq->nb_rb > 0,"nb_rb=0\n");
1614 1615 1616

    dlsch0_harq->mcs       = rel8->mcs_1;
    dlsch1_harq->mcs       = rel8->mcs_2;
1617 1618
    dlsch0_harq->Qm        = get_Qm(rel8->mcs_1);
    dlsch1_harq->Qm        = get_Qm(rel8->mcs_2);
1619 1620 1621 1622 1623 1624 1625 1626
    dlsch0_harq->rvidx     = rel8->redundancy_version_1;
    dlsch1_harq->rvidx     = rel8->redundancy_version_2;

    // assume both TBs are active
    dlsch0_harq->Nl        = 1;
    dlsch1_harq->Nl        = 1;
    dlsch0->active = 1;
    dlsch1->active = 1;
1627 1628
    dlsch0->harq_mask                         |= (1<<rel8->harq_process);
    dlsch1->harq_mask                         |= (1<<rel8->harq_process);
1629 1630 1631 1632

    // check if either TB is disabled (see 36-213 V11.3 Section )
    if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) {
      dlsch0->active = 0;
1633
      dlsch0->harq_mask                         &= ~(1<<rel8->harq_process);
1634 1635 1636 1637
    }

    if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) {
      dlsch1->active = 0;
1638
      dlsch1->harq_mask                         &= ~(1<<rel8->harq_process);
1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776
    }

   // dlsch0_harq->dl_power_off = 0;
   // dlsch1_harq->dl_power_off = 0;


    if (fp->nb_antenna_ports_eNB == 2) {
      dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
      dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch0_harq->nb_rb-1];

      if ((dlsch0->active==1) && (dlsch1->active==1)) {

        dlsch0_harq->mimo_mode = LARGE_CDD;
        dlsch1_harq->mimo_mode = LARGE_CDD;
        dlsch0_harq->dl_power_off = 1;
        dlsch1_harq->dl_power_off = 1;
      } else {
        dlsch0_harq->mimo_mode   = ALAMOUTI;
        dlsch1_harq->mimo_mode   = ALAMOUTI;
      }
    } else if (fp->nb_antenna_ports_eNB == 4) { // 4 antenna case
      if ((dlsch0->active==1) && (dlsch1->active==1)) {
        switch (rel8->precoding_information) {
        case 0: // one layer per transport block
          dlsch0_harq->mimo_mode   = LARGE_CDD;
          dlsch1_harq->mimo_mode   = LARGE_CDD;
          dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
          dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
          dlsch0_harq->dl_power_off = 1;
          dlsch1_harq->dl_power_off = 1;
          break;

        case 1: // one-layers on TB 0, two on TB 1
          dlsch0_harq->mimo_mode   = LARGE_CDD;
          dlsch1_harq->mimo_mode   = LARGE_CDD;
          dlsch1_harq->Nl          = 2;
          dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
          dlsch0_harq->dl_power_off = 1;
          dlsch1_harq->dl_power_off = 1;
          break;

        case 2: // two-layers on TB 0, two on TB 1
          dlsch0_harq->mimo_mode   = LARGE_CDD;
          dlsch1_harq->mimo_mode   = LARGE_CDD;
          dlsch0_harq->Nl          = 2;
          dlsch0_harq->dl_power_off = 1;
          dlsch1_harq->dl_power_off = 1;

          if (fp->N_RB_DL <= 56) {
            dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][(dlsch0_harq->nb_rb<<1)-1];
            dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
          } else {
            LOG_E(PHY,"Add implementation of Table 7.1.7.2.2-1 for two-layer TBS conversion with N_RB_DL > 56\n");
          }

          break;

        case 3: //
          LOG_E(PHY,"Illegal value (3) for TPMI in Format 2A DCI\n");
          break;
        }
      } else if (dlsch0->active == 1) {
        switch (rel8->precoding_information) {
        case 0: // one layer per transport block
          dlsch0_harq->mimo_mode   = ALAMOUTI;
          dlsch1_harq->mimo_mode   = ALAMOUTI;
          dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
          break;

        case 1: // two-layers on TB 0
          dlsch0_harq->mimo_mode   = LARGE_CDD;
          dlsch0_harq->Nl          = 2;
          dlsch0_harq->dl_power_off = 1;
          dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][(dlsch0_harq->nb_rb<<1)-1];
          break;

        case 2: // two-layers on TB 0, two on TB 1
        case 3: //
          LOG_E(PHY,"Illegal value %d for TPMI in Format 2A DCI with one transport block enabled\n",rel8->precoding_information);
          break;
        }
      } else if (dlsch1->active == 1) {
        switch (rel8->precoding_information) {
        case 0: // one layer per transport block
          dlsch0_harq->mimo_mode   = ALAMOUTI;
          dlsch1_harq->mimo_mode   = ALAMOUTI;
          dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
          break;

        case 1: // two-layers on TB 0
          dlsch1_harq->mimo_mode   = LARGE_CDD;
          dlsch1_harq->Nl          = 2;
          dlsch1_harq->dl_power_off = 1;
          dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
          break;

        case 2: // two-layers on TB 0, two on TB 1
        case 3: //
          LOG_E(PHY,"Illegal value %d for TPMI in Format 2A DCI with one transport block enabled\n",rel8->precoding_information);
          break;
        }
      }
    } else {
      LOG_E(PHY,"Illegal number of antennas for eNB %d\n",fp->nb_antenna_ports_eNB);
    }

    // reset HARQ process if this is the first transmission
    if ((dlsch0->active==1) && (dlsch0_harq->round == 0))
      dlsch0_harq->status = ACTIVE;

    if ((dlsch1->active==1) && (dlsch1_harq->round == 0))
      dlsch1_harq->status = ACTIVE;

    dlsch0->rnti = rel8->rnti;
    dlsch1->rnti = rel8->rnti;


    break;
      
  case NFAPI_DL_DCI_FORMAT_2:

    dci_alloc->format     = format2;
    switch (fp->N_RB_DL) {
    case 6:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                       = sizeof_DCI2_1_5MHz_2A_TDD_t; 
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->mcs1     = rel8->mcs_1;
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->mcs2     = rel8->mcs_2;
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->ndi1     = rel8->new_data_indicator_1;
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->ndi2     = rel8->new_data_indicator_2;
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rv1      = rel8->redundancy_version_1;
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rv2      = rel8->redundancy_version_2;
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
	((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap  = rel8->transport_block_to_codeword_swap_flag;
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->dai      = rel8->downlink_assignment_index;
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->tpmi     = rel8->precoding_information;
1777
        ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->padding  = 0;
1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791
        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                         = sizeof_DCI2_1_5MHz_2A_FDD_t; 
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->mcs1         = rel8->mcs_1;
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->mcs2         = rel8->mcs_2;
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->ndi1         = rel8->new_data_indicator_1;
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->ndi2         = rel8->new_data_indicator_2;
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rballoc      = rel8->resource_block_coding;
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rv1          = rel8->redundancy_version_1;
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rv2          = rel8->redundancy_version_2;
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->TPC          = rel8->tpc;
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid     = rel8->harq_process;
	((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap      = rel8->transport_block_to_codeword_swap_flag;
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->tpmi         = rel8->precoding_information;
1792
        ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->padding      = 0;
1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811
        //      printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      break;
    case 25:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                        = sizeof_DCI2_5MHz_2A_TDD_t; 
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rah       = rel8->resource_allocation_type;
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs1      = rel8->mcs_1;
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs2      = rel8->mcs_2;
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->ndi1      = rel8->new_data_indicator_1;
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->ndi2      = rel8->new_data_indicator_2;
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv1       = rel8->redundancy_version_1;
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv2       = rel8->redundancy_version_2;
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->TPC       = rel8->tpc;
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->harq_pid  = rel8->harq_process;
	((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tb_swap   = rel8->transport_block_to_codeword_swap_flag;	
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->dai       = rel8->downlink_assignment_index;	
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tpmi      = rel8->precoding_information;
1812
        ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->padding   = 0;
1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826
        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                           = sizeof_DCI2_5MHz_2A_FDD_t; 
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rah           = rel8->resource_allocation_type;
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs1          = rel8->mcs_1;
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs2          = rel8->mcs_2;
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->ndi1          = rel8->new_data_indicator_1;
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->ndi2          = rel8->new_data_indicator_2;
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rballoc       = rel8->resource_block_coding;
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv1           = rel8->redundancy_version_1;
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv2           = rel8->redundancy_version_2;
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->TPC           = rel8->tpc;
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->harq_pid      = rel8->harq_process;
	((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tb_swap       = rel8->transport_block_to_codeword_swap_flag;
1827 1828
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tpmi          = rel8->precoding_information;
        ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->padding       = 0;
1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847
        //      printf("FDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      break;
    case 50:
      if (fp->frame_type == TDD) {
	dci_alloc->dci_length                        = sizeof_DCI2_10MHz_2A_TDD_t; 
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rah      = rel8->resource_allocation_type;
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->mcs1     = rel8->mcs_1;
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->mcs2     = rel8->mcs_2;
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->ndi1     = rel8->new_data_indicator_1;
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->ndi2     = rel8->new_data_indicator_2;
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rballoc  = rel8->resource_block_coding;
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rv1      = rel8->redundancy_version_1;
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rv2      = rel8->redundancy_version_2;
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->TPC      = rel8->tpc;
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
	((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tb_swap  = rel8->transport_block_to_codeword_swap_flag;	
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->dai      = rel8->downlink_assignment_index;	
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tpmi     = rel8->precoding_information;
1848
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->padding  = 0;
1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861
        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
	dci_alloc->dci_length                        = sizeof_DCI2_10MHz_2A_FDD_t; 
        ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rah       = rel8->resource_allocation_type;
        ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->mcs1      = rel8->mcs_1;
        ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->mcs2      = rel8->mcs_2;
        ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->ndi1      = rel8->new_data_indicator_1;
        ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->ndi2      = rel8->new_data_indicator_2;
        ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
        ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv1       = rel8->redundancy_version_1;
        ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv2       = rel8->redundancy_version_2;
        ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->TPC       = rel8->tpc;
        ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->harq_pid  = rel8->harq_process;
1862
	((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tb_swap   = rel8->transport_block_to_codeword_swap_flag;
1863
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tpmi      = rel8->precoding_information;
1864
        ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->padding   = 0;
1865 1866 1867 1868
      }
      break;
    case 100:
      if (fp->frame_type == TDD) {
1869
	dci_alloc->dci_length                        = sizeof_DCI2_20MHz_2A_TDD_t;
1870 1871 1872 1873 1874 1875 1876 1877 1878 1879
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rah       = rel8->resource_allocation_type;
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs1      = rel8->mcs_1;
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs2      = rel8->mcs_2;
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->ndi1      = rel8->new_data_indicator_1;
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->ndi2      = rel8->new_data_indicator_2;
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rballoc   = rel8->resource_block_coding;
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv1       = rel8->redundancy_version_1;
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv2       = rel8->redundancy_version_2;
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->TPC       = rel8->tpc;
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->harq_pid  = rel8->harq_process;
1880 1881
	((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tb_swap   = rel8->transport_block_to_codeword_swap_flag;
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->dai       = rel8->downlink_assignment_index;
1882
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tpmi      = rel8->precoding_information;
1883
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->padding   = 0;
1884 1885
        //        printf("TDD 1: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      } else {
1886
	dci_alloc->dci_length                           = sizeof_DCI2_20MHz_2A_FDD_t;
1887 1888 1889 1890 1891 1892 1893 1894 1895 1896
        ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rah          = rel8->resource_allocation_type;
        ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs1         = rel8->mcs_1;
        ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs2         = rel8->mcs_2;
        ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->ndi1         = rel8->new_data_indicator_1;
        ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->ndi2         = rel8->new_data_indicator_2;
        ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rballoc      = rel8->resource_block_coding;
        ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv1          = rel8->redundancy_version_1;
        ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv2          = rel8->redundancy_version_2;
        ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->TPC          = rel8->tpc;
        ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->harq_pid     = rel8->harq_process;
1897
	((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tb_swap      = rel8->transport_block_to_codeword_swap_flag;
1898
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tpmi         = rel8->precoding_information;
1899
        ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->padding      = 0;
1900 1901 1902 1903 1904
      }
      break;

    }

1905
    AssertFatal(rel8->harq_process>=8, "Format 2_2A: harq_pid=%d >= 8\n", rel8->harq_process);
1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924


    // Flip the TB to codeword mapping as described in 5.3.3.1.5 of 36-212 V11.3.0
    // note that we must set tbswap=0 in eNB scheduler if one TB is deactivated
    TB0_active = 1;
    TB1_active = 1;

    if ((rel8->redundancy_version_1 == 1) && (rel8->mcs_1 == 0)) {
      TB0_active=0;
    }
    if ((rel8->redundancy_version_2 == 1) && (rel8->mcs_2 == 0)) {
      TB1_active=0;
    }
#ifdef DEBUG_HARQ
    printf("RV0 = %d, RV1 = %d. MCS0 = %d, MCS1=%d\n", rel8->redundancy_version_1, rel8->redundancy_version_2, rel8->mcs_1, rel8->mcs_2);
#endif
    if (TB0_active && TB1_active && rel8->transport_block_to_codeword_swap_flag==0) {
      dlsch0->active = 1;
      dlsch1->active = 1;
1925 1926
      dlsch0->harq_mask                         |= (1<<rel8->harq_process);
      dlsch1->harq_mask                         |= (1<<rel8->harq_process);
1927 1928 1929 1930
      dlsch0_harq = dlsch0->harq_processes[rel8->harq_process];
      dlsch1_harq = dlsch1->harq_processes[rel8->harq_process];
      dlsch0_harq->mcs = rel8->mcs_1;
      dlsch1_harq->mcs = rel8->mcs_2;
1931 1932
      dlsch0_harq->Qm  = get_Qm(rel8->mcs_1);
      dlsch1_harq->Qm  = get_Qm(rel8->mcs_2);
1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947
      dlsch0_harq->rvidx = rel8->redundancy_version_1;
      dlsch1_harq->rvidx = rel8->redundancy_version_2;
      dlsch0_harq->status = ACTIVE;
      dlsch1_harq->status = ACTIVE;
      dlsch0_harq->codeword=0;
      dlsch1_harq->codeword=1;
#ifdef DEBUG_HARQ
      printf("\n ENB: BOTH ACTIVE\n");
#endif
    }
    else if (TB0_active && TB1_active && rel8->transport_block_to_codeword_swap_flag==1) {
      dlsch0 = eNB->dlsch[UE_id][1];
      dlsch1 = eNB->dlsch[UE_id][0];
      dlsch0->active = 1;
      dlsch1->active = 1;
1948 1949 1950 1951

      dlsch0->harq_mask                         |= (1<<rel8->harq_process);
      dlsch1->harq_mask                         |= (1<<rel8->harq_process);

1952 1953 1954
      dlsch1_harq = dlsch1->harq_processes[rel8->harq_process];
      dlsch0_harq->mcs = rel8->mcs_1;
      dlsch1_harq->mcs = rel8->mcs_2;
1955 1956
      dlsch0_harq->Qm  = get_Qm(rel8->mcs_1);
      dlsch1_harq->Qm  = get_Qm(rel8->mcs_2);
1957 1958 1959 1960 1961 1962 1963 1964 1965
      dlsch0_harq->rvidx = rel8->redundancy_version_1;
      dlsch1_harq->rvidx = rel8->redundancy_version_2;
      dlsch0_harq->status = ACTIVE;
      dlsch1_harq->status = ACTIVE;
      dlsch0_harq->codeword=1;
      dlsch1_harq->codeword=0;
    }
    else if (TB0_active && (TB1_active==0)) {
      dlsch0->active = 1;
1966
      dlsch0->harq_mask                         |= (1<<rel8->harq_process);
1967 1968
      dlsch0_harq = dlsch0->harq_processes[rel8->harq_process];
      dlsch0_harq->mcs = rel8->mcs_1;
1969
      dlsch0_harq->Qm  = get_Qm(rel8->mcs_1);
1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980
      dlsch0_harq->rvidx = rel8->redundancy_version_1;
      dlsch0_harq->status = ACTIVE;
      dlsch0_harq->codeword = 0;
      dlsch1=NULL;
      dlsch1_harq = NULL;
#ifdef DEBUG_HARQ
      printf("\n ENB: TB1 is deactivated, retransmit TB0 transmit in TM6\n");
#endif
    }
    else if ((TB0_active==0) && TB1_active) {
      dlsch1->active = 1;
1981
      dlsch1->harq_mask                         |= (1<<rel8->harq_process);
1982 1983
      dlsch1_harq = dlsch1->harq_processes[rel8->harq_process];
      dlsch1_harq->mcs = rel8->mcs_2;
1984
      dlsch1_harq->Qm  = get_Qm(rel8->mcs_2);
1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035
      dlsch1_harq->rvidx = rel8->redundancy_version_2;
      dlsch1_harq->status = ACTIVE;
      dlsch1_harq->codeword = 0;
      dlsch0=NULL;
      dlsch0_harq = NULL;
#ifdef DEBUG_HARQ
      printf("\n ENB: TB0 is deactivated, retransmit TB1 transmit in TM6\n");
#endif
    }

    if (dlsch0 != NULL){
      dlsch0->subframe_tx[subframe] = 1;

      dlsch0->harq_ids[subframe] = rel8->harq_process;
    }

    if (dlsch1_harq != NULL){
      dlsch1->harq_ids[subframe] = rel8->harq_process;
    }


    if (dlsch0 != NULL ){
      conv_rballoc(rel8->resource_allocation_type,
                   rel8->resource_block_coding,
                   fp->N_RB_DL,
                   dlsch0_harq->rb_alloc);

      dlsch0_harq->nb_rb = conv_nprb(rel8->resource_allocation_type, rel8->resource_block_coding, fp->N_RB_DL);

      if (dlsch1 != NULL){
        dlsch1_harq->rb_alloc[0] = dlsch0_harq->rb_alloc[0];
        dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
      }
    } else if ((dlsch0 == NULL ) && (dlsch1 != NULL )){
        conv_rballoc(rel8->resource_allocation_type,
                     rel8->resource_block_coding,
                     fp->N_RB_DL,
                     dlsch1_harq->rb_alloc);

        dlsch1_harq->nb_rb = conv_nprb(rel8->resource_allocation_type, rel8->resource_block_coding, fp->N_RB_DL);
    }


    // assume both TBs are active
    if (dlsch0_harq != NULL)
      dlsch0_harq->Nl        = 1;
    if (dlsch1_harq != NULL)
      dlsch1_harq->Nl        = 1;


    // check if either TB is disabled (see 36-213 V11.3 Section )
2036

2037 2038
    if (fp->nb_antenna_ports_eNB == 2) {
      if ((dlsch0 != NULL) && (dlsch1 != NULL)) {  //two CW active
2039

2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055
        dlsch0_harq->dl_power_off = 1;
        dlsch1_harq->dl_power_off = 1;
        dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
        dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
        switch (rel8->precoding_information) {
        case 0:
          dlsch0_harq->mimo_mode   = DUALSTREAM_UNIFORM_PRECODING1;
          dlsch1_harq->mimo_mode   = DUALSTREAM_UNIFORM_PRECODING1;
          dlsch0_harq->pmi_alloc   = pmi_extend(fp,0,1);
          dlsch1_harq->pmi_alloc   = pmi_extend(fp,0,1);
          break;
        case 1:
          dlsch0_harq->mimo_mode   = DUALSTREAM_UNIFORM_PRECODINGj;
          dlsch1_harq->mimo_mode   = DUALSTREAM_UNIFORM_PRECODINGj;
          dlsch0_harq->pmi_alloc   = pmi_extend(fp,1,1);
          dlsch0_harq->pmi_alloc   = pmi_extend(fp,1,1);
2056

2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131
          break;
        case 2: // PUSCH precoding
          dlsch0_harq->mimo_mode   = DUALSTREAM_PUSCH_PRECODING;
          dlsch0_harq->pmi_alloc   = DL_pmi_single;
          dlsch1_harq->mimo_mode   = DUALSTREAM_PUSCH_PRECODING;
          dlsch1_harq->pmi_alloc   = DL_pmi_single;
          break;
        default:
          break;
        }
      } else if ((dlsch0 != NULL) && (dlsch1 == NULL))  { // only CW 0 active
        dlsch0_harq->dl_power_off = 1;
        dlsch0_harq->TBS= TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
        switch (rel8->precoding_information) {
        case 0 :
          dlsch0_harq->mimo_mode   = ALAMOUTI;
          break;
        case 1:
          dlsch0_harq->mimo_mode   = UNIFORM_PRECODING11;
          dlsch0_harq->pmi_alloc   = pmi_extend(fp,0,0);
          break;
        case 2:
          dlsch0_harq->mimo_mode   = UNIFORM_PRECODING1m1;
          dlsch0_harq->pmi_alloc   = pmi_extend(fp,1,0);
          break;
        case 3:
          dlsch0_harq->mimo_mode   = UNIFORM_PRECODING1j;
          dlsch0_harq->pmi_alloc   = pmi_extend(fp,2,0);
          break;
        case 4:
          dlsch0_harq->mimo_mode   = UNIFORM_PRECODING1mj;
          dlsch0_harq->pmi_alloc   = pmi_extend(fp,3,0);
          break;
        case 5:
          dlsch0_harq->mimo_mode   = PUSCH_PRECODING0;
          dlsch0_harq->pmi_alloc   = DL_pmi_single;
          break;
        case 6:
          dlsch0_harq->mimo_mode   = PUSCH_PRECODING1;
          dlsch0_harq->pmi_alloc   = DL_pmi_single;
          break;
        }
      } else if ((dlsch0 == NULL) && (dlsch1 != NULL))  {
          dlsch1_harq->dl_power_off = 1;
          dlsch1_harq->TBS= TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
          switch (rel8->precoding_information) {
          case 0 :
            dlsch1_harq->mimo_mode   = ALAMOUTI;
            break;
          case 1:
            dlsch1_harq->mimo_mode   = UNIFORM_PRECODING11;
            dlsch1_harq->pmi_alloc   = pmi_extend(fp,0,0);
            break;
          case 2:
            dlsch1_harq->mimo_mode   = UNIFORM_PRECODING1m1;
            dlsch1_harq->pmi_alloc   = pmi_extend(fp,1,0);
            break;
          case 3:
            dlsch1_harq->mimo_mode   = UNIFORM_PRECODING1j;
            dlsch1_harq->pmi_alloc   = pmi_extend(fp,2,0);
            break;
          case 4:
            dlsch1_harq->mimo_mode   = UNIFORM_PRECODING1mj;
            dlsch1_harq->pmi_alloc   = pmi_extend(fp,3,0);
            break;
          case 5:
            dlsch1_harq->mimo_mode   = PUSCH_PRECODING0;
            dlsch1_harq->pmi_alloc   = DL_pmi_single;
            break;
          case 6:
            dlsch1_harq->mimo_mode   = PUSCH_PRECODING1;
            dlsch1_harq->pmi_alloc   = DL_pmi_single;
            break;
          }
        }
2132

2133 2134 2135
    } else if (fp->nb_antenna_ports_eNB == 4) {
      // fill in later
    }
2136

2137 2138 2139
    // reset HARQ process if this is the first transmission
   /* if (dlsch0_harq->round == 0)
      dlsch0_harq->status = ACTIVE;
2140

2141 2142 2143 2144 2145 2146
    if (dlsch1_harq->round == 0)
      dlsch1_harq->status = ACTIVE;*/
    if (dlsch0_harq != NULL)
      dlsch0->rnti = rel8->rnti;
    if (dlsch1 != NULL)
      dlsch1->rnti = rel8->rnti;
2147

2148
    break;
2149 2150
  }

2151
  if (dlsch0_harq) {
2152
    dlsch0_harq->frame    = frame;
2153 2154 2155
    dlsch0_harq->subframe = subframe;
  }
  if (dlsch1_harq) {
2156
    dlsch1_harq->frame    = frame;
2157 2158
    dlsch1_harq->subframe = subframe;
  }
2159

2160
#ifdef DEBUG_DCI
2161

2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174
  if (dlsch0) {
    printf("dlsch0 eNB: dlsch0   %p\n",dlsch0);
    printf("dlsch0 eNB: rnti     %x\n",dlsch0->rnti);
    printf("dlsch0 eNB: NBRB     %d\n",dlsch0_harq->nb_rb);
    printf("dlsch0 eNB: rballoc  %x\n",dlsch0_harq->rb_alloc[0]);
    printf("dlsch0 eNB: harq_pid %d\n",harq_pid);
    printf("dlsch0 eNB: round    %d\n",dlsch0_harq->round);
    printf("dlsch0 eNB: rvidx    %d\n",dlsch0_harq->rvidx);
    printf("dlsch0 eNB: TBS      %d (NPRB %d)\n",dlsch0_harq->TBS,NPRB);
    printf("dlsch0 eNB: mcs      %d\n",dlsch0_harq->mcs);
    printf("dlsch0 eNB: tpmi %d\n",rel8->precoding_information);
    printf("dlsch0 eNB: mimo_mode %d\n",dlsch0_harq->mimo_mode);
  }
2175

2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188
    if (dlsch1) {
    printf("dlsch1 eNB: dlsch1   %p\n",dlsch1);
    printf("dlsch1 eNB: rnti     %x\n",dlsch1->rnti);
    printf("dlsch1 eNB: NBRB     %d\n",dlsch1_harq->nb_rb);
    printf("dlsch1 eNB: rballoc  %x\n",dlsch1_harq->rb_alloc[0]);
    printf("dlsch1 eNB: harq_pid %d\n",harq_pid);
    printf("dlsch1 eNB: round    %d\n",dlsch1_harq->round);
    printf("dlsch1 eNB: rvidx    %d\n",dlsch1_harq->rvidx);
    printf("dlsch1 eNB: TBS      %d (NPRB %d)\n",dlsch1_harq->TBS,NPRB);
    printf("dlsch1 eNB: mcs      %d\n",dlsch1_harq->mcs);
    printf("dlsch1 eNB: tpmi %d\n",rel8->precoding_information);
    printf("dlsch1 eNB: mimo_mode %d\n",dlsch1_harq->mimo_mode);
  }
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#endif
    
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#if T_TRACER
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  if (dlsch0->active)
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    T(T_ENB_PHY_DLSCH_UE_DCI, T_INT(0), T_INT(frame), T_INT(subframe),
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      T_INT(rel8->rnti), T_INT(rel8->dci_format), T_INT(rel8->harq_process),
      T_INT(rel8->mcs_1), T_INT(dlsch0_harq->TBS));
#endif

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}

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void fill_mdci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,mDCI_ALLOC_t *dci_alloc,nfapi_dl_config_mpdcch_pdu *pdu) {
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  LTE_DL_FRAME_PARMS *fp = &eNB->frame_parms;

  uint8_t *dci_pdu = &dci_alloc->dci_pdu[0];
  nfapi_dl_config_mpdcch_pdu_rel13_t *rel13 = &pdu->mpdcch_pdu_rel13;
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  LTE_eNB_DLSCH_t *dlsch0=NULL;
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  LTE_DL_eNB_HARQ_t *dlsch0_harq=NULL;
  int UE_id;
  int subframe = proc->subframe_tx;

  dci_alloc->firstCCE                   = rel13->ecce_index;
  dci_alloc->L                          = rel13->aggregation_level;
  dci_alloc->rnti                       = rel13->rnti;
  dci_alloc->harq_pid                   = rel13->harq_process;
  dci_alloc->narrowband                  = rel13->mpdcch_narrow_band;
  dci_alloc->number_of_prb_pairs        = rel13->number_of_prb_pairs;
  dci_alloc->resource_block_assignment  = rel13->resource_block_assignment;
  dci_alloc->transmission_type          = rel13->mpdcch_tansmission_type;
  dci_alloc->start_symbol               = rel13->start_symbol;
  dci_alloc->ce_mode                    = rel13->ce_mode;
  dci_alloc->dmrs_scrambling_init       = rel13->drms_scrambling_init;
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  dci_alloc->i0                         = rel13->initial_transmission_sf_io;
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  dci_alloc->ra_flag  = 0;
  if (rel13->rnti_type == 2 ) dci_alloc->ra_flag = 1;

  UE_id = find_dlsch(rel13->rnti,eNB,SEARCH_EXIST_OR_FREE);
  AssertFatal(UE_id!=-1,"no free or exiting dlsch_context\n");
  AssertFatal(UE_id<NUMBER_OF_UE_MAX,"returned UE_id %d >= %d(NUMBER_OF_UE_MAX)\n",UE_id,NUMBER_OF_UE_MAX);
  dlsch0 = eNB->dlsch[UE_id][0];
  dlsch0_harq                               = dlsch0->harq_processes[rel13->harq_process];

  AssertFatal(fp->frame_type==FDD,"TDD is not supported yet for eMTC\n");
  AssertFatal(fp->N_RB_DL==25 || fp->N_RB_DL==50 ||fp->N_RB_DL==100,
	      "eMTC only with N_RB_DL = 25,50,100\n");

  switch (rel13->dci_format) {

  case 10:  // Format 6-1A
    dci_alloc->format     = format6_1A;
    dlsch0->active       = 1;
    switch (fp->N_RB_DL) {

    case 25:
      dci_alloc->dci_length                     = sizeof_DCI6_1A_5MHz_t; 
      ((DCI6_1A_5MHz_t *)dci_pdu)->type         = 1;
      ((DCI6_1A_5MHz_t *)dci_pdu)->hopping      = rel13->frequency_hopping_enabled_flag;
      ((DCI6_1A_5MHz_t *)dci_pdu)->rballoc      = rel13->resource_block_coding;
      ((DCI6_1A_5MHz_t *)dci_pdu)->mcs          = rel13->mcs;
      ((DCI6_1A_5MHz_t *)dci_pdu)->rep          = (rel13->pdsch_reptition_levels-1);
      ((DCI6_1A_5MHz_t *)dci_pdu)->harq_pid     = rel13->harq_process;
      ((DCI6_1A_5MHz_t *)dci_pdu)->ndi          = rel13->new_data_indicator;
      ((DCI6_1A_5MHz_t *)dci_pdu)->rv           = rel13->redundancy_version;
      ((DCI6_1A_5MHz_t *)dci_pdu)->TPC          = rel13->tpc;
      ((DCI6_1A_5MHz_t *)dci_pdu)->srs_req      = rel13->srs_request;
      ((DCI6_1A_5MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset;
      ((DCI6_1A_5MHz_t *)dci_pdu)->dci_rep      = rel13->dci_subframe_repetition_number-1;
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      ((DCI6_1A_5MHz_t *)dci_pdu)->padding      = 0;
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      break;
    case 50:
      dci_alloc->dci_length                     = sizeof_DCI6_1A_10MHz_t; 
      ((DCI6_1A_10MHz_t *)dci_pdu)->type         = 1;
      ((DCI6_1A_10MHz_t *)dci_pdu)->hopping      = rel13->frequency_hopping_enabled_flag;
      ((DCI6_1A_10MHz_t *)dci_pdu)->rballoc      = rel13->resource_block_coding;
      ((DCI6_1A_10MHz_t *)dci_pdu)->mcs          = rel13->mcs;
      ((DCI6_1A_10MHz_t *)dci_pdu)->rep          = (rel13->pdsch_reptition_levels-1);
      ((DCI6_1A_10MHz_t *)dci_pdu)->harq_pid     = rel13->harq_process;
      ((DCI6_1A_10MHz_t *)dci_pdu)->ndi          = rel13->new_data_indicator;
      ((DCI6_1A_10MHz_t *)dci_pdu)->rv           = rel13->redundancy_version;
      ((DCI6_1A_10MHz_t *)dci_pdu)->TPC          = rel13->tpc;
      ((DCI6_1A_10MHz_t *)dci_pdu)->srs_req      = rel13->srs_request;
      ((DCI6_1A_10MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset;
      ((DCI6_1A_10MHz_t *)dci_pdu)->dci_rep      = rel13->dci_subframe_repetition_number-1;
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      ((DCI6_1A_10MHz_t *)dci_pdu)->padding      = 0;
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      break;
    case 100:
      dci_alloc->dci_length                     = sizeof_DCI6_1A_20MHz_t; 
      ((DCI6_1A_20MHz_t *)dci_pdu)->type         = 1;
      ((DCI6_1A_20MHz_t *)dci_pdu)->hopping      = rel13->frequency_hopping_enabled_flag;
      ((DCI6_1A_20MHz_t *)dci_pdu)->rballoc      = rel13->resource_block_coding;
      ((DCI6_1A_20MHz_t *)dci_pdu)->mcs          = rel13->mcs;
      ((DCI6_1A_20MHz_t *)dci_pdu)->rep          = (rel13->pdsch_reptition_levels-1);
      ((DCI6_1A_20MHz_t *)dci_pdu)->harq_pid     = rel13->harq_process;
      ((DCI6_1A_20MHz_t *)dci_pdu)->ndi          = rel13->new_data_indicator;
      ((DCI6_1A_20MHz_t *)dci_pdu)->rv           = rel13->redundancy_version;
      ((DCI6_1A_20MHz_t *)dci_pdu)->TPC          = rel13->tpc;
      ((DCI6_1A_20MHz_t *)dci_pdu)->srs_req      = rel13->srs_request;
      ((DCI6_1A_20MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset;
      ((DCI6_1A_20MHz_t *)dci_pdu)->dci_rep      = rel13->dci_subframe_repetition_number-1;
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      ((DCI6_1A_20MHz_t *)dci_pdu)->padding      = 0;
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      break;
    }
    break;
  case 11:  // Format 6-1B
    dci_alloc->format     = format6_1B;
    dlsch0->active       = 1;
    switch (fp->N_RB_DL) {

    case 25:
      dci_alloc->dci_length                     = sizeof_DCI6_1B_5MHz_t; 
      ((DCI6_1B_5MHz_t *)dci_pdu)->type         = 1;
      ((DCI6_1B_5MHz_t *)dci_pdu)->rballoc      = rel13->resource_block_coding;
      ((DCI6_1B_5MHz_t *)dci_pdu)->mcs          = rel13->mcs;
      ((DCI6_1B_5MHz_t *)dci_pdu)->rep          = (rel13->pdsch_reptition_levels-1);
      ((DCI6_1B_5MHz_t *)dci_pdu)->harq_pid     = rel13->harq_process;
      ((DCI6_1B_5MHz_t *)dci_pdu)->ndi          = rel13->new_data_indicator;
      ((DCI6_1B_5MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset;
      ((DCI6_1B_5MHz_t *)dci_pdu)->dci_rep      = rel13->dci_subframe_repetition_number-1;
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      ((DCI6_1B_5MHz_t *)dci_pdu)->padding      = 0;
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      break;
    case 50:
      dci_alloc->dci_length                      = sizeof_DCI6_1B_10MHz_t; 
      ((DCI6_1B_10MHz_t *)dci_pdu)->type         = 1;
      ((DCI6_1B_10MHz_t *)dci_pdu)->rballoc      = rel13->resource_block_coding;
      ((DCI6_1B_10MHz_t *)dci_pdu)->mcs          = rel13->mcs;
      ((DCI6_1B_10MHz_t *)dci_pdu)->rep          = (rel13->pdsch_reptition_levels-1);
      ((DCI6_1B_10MHz_t *)dci_pdu)->harq_pid     = rel13->harq_process;
      ((DCI6_1B_10MHz_t *)dci_pdu)->ndi          = rel13->new_data_indicator;
      ((DCI6_1B_10MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset;
      ((DCI6_1B_10MHz_t *)dci_pdu)->dci_rep      = rel13->dci_subframe_repetition_number-1;
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      ((DCI6_1B_10MHz_t *)dci_pdu)->padding      = 0;
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      break;
    case 100:
      dci_alloc->dci_length                      = sizeof_DCI6_1B_20MHz_t; 
      ((DCI6_1B_20MHz_t *)dci_pdu)->type         = 1;
      ((DCI6_1B_20MHz_t *)dci_pdu)->rballoc      = rel13->resource_block_coding;
      ((DCI6_1B_20MHz_t *)dci_pdu)->mcs          = rel13->mcs;
      ((DCI6_1B_20MHz_t *)dci_pdu)->rep          = (rel13->pdsch_reptition_levels-1);
      ((DCI6_1B_20MHz_t *)dci_pdu)->harq_pid     = rel13->harq_process;
      ((DCI6_1B_20MHz_t *)dci_pdu)->ndi          = rel13->new_data_indicator;
      ((DCI6_1B_20MHz_t *)dci_pdu)->harq_ack_off = rel13->harq_resource_offset;
      ((DCI6_1B_20MHz_t *)dci_pdu)->dci_rep      = rel13->dci_subframe_repetition_number-1;
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      ((DCI6_1B_20MHz_t *)dci_pdu)->padding      = 0;
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      break;
    }
  case 12: // Format 6-2
    dci_alloc->format     = format6_2;
    dlsch0->active       = 1;
    switch (fp->N_RB_DL) {
    case 25:
      dci_alloc->dci_length                 = sizeof_DCI6_2_5MHz_t; 
      if (rel13->paging_direct_indication_differentiation_flag==0) {
	((DCI6_2_di_5MHz_t *)dci_pdu)->type    = 0;
	((DCI6_2_di_5MHz_t *)dci_pdu)->di_info = rel13->direct_indication;
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	((DCI6_2_di_5MHz_t *)dci_pdu)->padding = 0;
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      }
      else {
	((DCI6_2_paging_5MHz_t *)dci_pdu)->type    = 1;
	((DCI6_2_paging_5MHz_t *)dci_pdu)->rballoc = rel13->resource_block_coding;
	((DCI6_2_paging_5MHz_t *)dci_pdu)->mcs     = rel13->mcs;
	((DCI6_2_paging_5MHz_t *)dci_pdu)->rep     = (rel13->pdsch_reptition_levels-1);
	((DCI6_2_paging_5MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1;
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	((DCI6_2_paging_5MHz_t *)dci_pdu)->padding = 0;
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      }

    break;
    case 50:
      dci_alloc->dci_length                 = sizeof_DCI6_2_10MHz_t; 
      if (rel13->paging_direct_indication_differentiation_flag==0) {
	((DCI6_2_di_10MHz_t *)dci_pdu)->type    = 0;
	((DCI6_2_di_10MHz_t *)dci_pdu)->di_info = rel13->direct_indication;
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	((DCI6_2_di_10MHz_t *)dci_pdu)->padding = 0;
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      }
      else {
	((DCI6_2_paging_10MHz_t *)dci_pdu)->type    = 1;
	((DCI6_2_paging_10MHz_t *)dci_pdu)->rballoc = rel13->resource_block_coding;
	((DCI6_2_paging_10MHz_t *)dci_pdu)->mcs     = rel13->mcs;
	((DCI6_2_paging_10MHz_t *)dci_pdu)->rep     = (rel13->pdsch_reptition_levels-1);
	((DCI6_2_paging_10MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1;
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	((DCI6_2_paging_10MHz_t *)dci_pdu)->padding = 0;
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      }

    break;
    case 100:
      dci_alloc->dci_length                 = sizeof_DCI6_2_20MHz_t; 
      if (rel13->paging_direct_indication_differentiation_flag==0) {
	((DCI6_2_di_20MHz_t *)dci_pdu)->type    = 0;
	((DCI6_2_di_20MHz_t *)dci_pdu)->di_info = rel13->direct_indication;
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	((DCI6_2_di_20MHz_t *)dci_pdu)->padding = 0;
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      }
      else {
	((DCI6_2_paging_20MHz_t *)dci_pdu)->type    = 1;
	((DCI6_2_paging_20MHz_t *)dci_pdu)->rballoc = rel13->resource_block_coding;
	((DCI6_2_paging_20MHz_t *)dci_pdu)->mcs     = rel13->mcs;
	((DCI6_2_paging_20MHz_t *)dci_pdu)->rep     = (rel13->pdsch_reptition_levels-1);
	((DCI6_2_paging_20MHz_t *)dci_pdu)->dci_rep = rel13->dci_subframe_repetition_number-1;
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	((DCI6_2_paging_20MHz_t *)dci_pdu)->padding = 0;
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      }

      break;
    }
  }
  AssertFatal(rel13->harq_process<8,
	      "ERROR: Format 6_1A: harq_pid=%d >= 8\n", rel13->harq_process);
  
  dlsch0_harq = dlsch0->harq_processes[rel13->harq_process];
  dlsch0_harq->codeword=0;
  
  // printf("DCI: Setting subframe_tx for subframe %d\n",subframe);
  dlsch0->subframe_tx[subframe] = 1;
  
  conv_eMTC_rballoc(rel13->resource_block_coding,
		    fp->N_RB_DL,
		    dlsch0_harq->rb_alloc);
  
  dlsch0_harq->nb_rb = RIV2nb_rb_LUT6[rel13->resource_block_coding&31]; // this is the 6PRB RIV
  
  
  dlsch0_harq->rvidx       = rel13->redundancy_version;
  
  dlsch0_harq->Nl          = 1;
  //    dlsch[0]->layer_index = 0;
  //  if (beamforming_mode == 0)
  dlsch0_harq->mimo_mode = (fp->nb_antenna_ports_eNB == 1) ? SISO : ALAMOUTI;
    //else if (beamforming_mode == 7)
    //  dlsch0_harq->mimo_mode = TM7;
    //else
    //LOG_E(PHY,"Invalid beamforming mode %dL\n", beamforming_mode);
  
  dlsch0_harq->dl_power_off = 1;
  
  dlsch0->active = 1;
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  dlsch0->harq_mask                         |= (1<<rel13->harq_process);  
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  if (dlsch0_harq->round == 0) {
    dlsch0_harq->status = ACTIVE;
    //            printf("Setting DLSCH process %d to ACTIVE\n",rel8->harq_process);
    // MCS and TBS don't change across HARQ rounds
    dlsch0_harq->mcs         = rel13->mcs;
    dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
    
  }
  
  dlsch0->harq_ids[subframe] = rel13->harq_process;
  
  
  
  dlsch0->rnti = rel13->rnti;







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}

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void fill_dci0(PHY_VARS_eNB *eNB,int frame,int subframe,eNB_rxtx_proc_t *proc,
    DCI_ALLOC_t *dci_alloc,nfapi_hi_dci0_dci_pdu *pdu)
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{
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  LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms;

  uint32_t cqi_req = pdu->dci_pdu_rel8.cqi_csi_request;
  uint32_t dai     = pdu->dci_pdu_rel8.dl_assignment_index;
  uint32_t cshift  = pdu->dci_pdu_rel8.cyclic_shift_2_for_drms;
  uint32_t TPC     = pdu->dci_pdu_rel8.tpc;
  uint32_t mcs     = pdu->dci_pdu_rel8.mcs_1;
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  uint32_t hopping = pdu->dci_pdu_rel8.frequency_hopping_enabled_flag;
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  uint32_t rballoc = computeRIV(frame_parms->N_RB_DL,
				pdu->dci_pdu_rel8.resource_block_start,
				pdu->dci_pdu_rel8.number_of_resource_block);

  uint32_t ndi     = pdu->dci_pdu_rel8.new_data_indication_1;

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#ifdef T_TRACER
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  T(T_ENB_PHY_ULSCH_UE_DCI, T_INT(eNB->Mod_id), T_INT(frame), T_INT(subframe),
    T_INT(pdu->dci_pdu_rel8.rnti), T_INT(((frame*10+subframe+4) % 8) /* TODO: correct harq pid */),
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    T_INT(mcs), T_INT(-1 /* TODO: remove round? */),
    T_INT(pdu->dci_pdu_rel8.resource_block_start),
    T_INT(pdu->dci_pdu_rel8.number_of_resource_block),
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    T_INT(get_TBS_UL(mcs, pdu->dci_pdu_rel8.number_of_resource_block) * 8),
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    T_INT(pdu->dci_pdu_rel8.aggregation_level),
    T_INT(pdu->dci_pdu_rel8.cce_index));
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#endif
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  void *dci_pdu = (void*)dci_alloc->dci_pdu;

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  LOG_D(PHY,"SFN/SF:%04d%d DCI0[rnti %x cqi %d mcs %d hopping %d rballoc %x (%d,%d) ndi %d TPC %d cshift %d]\n",
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        frame,subframe,
        pdu->dci_pdu_rel8.rnti,cqi_req, mcs,hopping,rballoc,
        pdu->dci_pdu_rel8.resource_block_start,
        pdu->dci_pdu_rel8.number_of_resource_block, ndi,TPC,cshift);
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  dci_alloc->format   = format0;
  dci_alloc->firstCCE = pdu->dci_pdu_rel8.cce_index;
  dci_alloc->L        = pdu->dci_pdu_rel8.aggregation_level;
  dci_alloc->rnti     = pdu->dci_pdu_rel8.rnti;
  dci_alloc->ra_flag  = 0;

  switch (frame_parms->N_RB_DL) {
  case 6:
    if (frame_parms->frame_type == TDD) {
      ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->cqi_req = cqi_req;
      ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->dai     = dai;
      ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->cshift  = cshift;
      ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC     = TPC;
      ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs     = mcs;
      ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi     = ndi;
      ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc = rballoc;
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      ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->hopping = hopping;
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      ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->type    = 0;
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      ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->padding = 0;
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      dci_alloc->dci_length                       = sizeof_DCI0_1_5MHz_TDD_1_6_t; 
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    } else {
      ((DCI0_1_5MHz_FDD_t *)dci_pdu)->cqi_req     = cqi_req;
      ((DCI0_1_5MHz_FDD_t *)dci_pdu)->cshift      = cshift;
      ((DCI0_1_5MHz_FDD_t *)dci_pdu)->TPC         = TPC;
      ((DCI0_1_5MHz_FDD_t *)dci_pdu)->mcs         = mcs;
      ((DCI0_1_5MHz_FDD_t *)dci_pdu)->ndi         = ndi;
      ((DCI0_1_5MHz_FDD_t *)dci_pdu)->rballoc     = rballoc;
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      ((DCI0_1_5MHz_FDD_t *)dci_pdu)->hopping     = hopping;
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      ((DCI0_1_5MHz_FDD_t *)dci_pdu)->type        = 0;
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      ((DCI0_1_5MHz_FDD_t *)dci_pdu)->padding     = 0;
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      dci_alloc->dci_length                       = sizeof_DCI0_1_5MHz_FDD_t; 
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    }
    
    break;
    
  case 25:
    if (frame_parms->frame_type == TDD) {
      ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cqi_req = cqi_req;
      ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->dai     = dai;
      ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cshift  = cshift;
      ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->TPC     = TPC;
      ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->mcs     = mcs;
      ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->ndi     = ndi;
      ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->rballoc = rballoc;
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      ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->hopping = hopping;
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      ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->type    = 0;
2535
      ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->padding = 0;
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      dci_alloc->dci_length                     = sizeof_DCI0_5MHz_TDD_1_6_t; 
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    } else {
      ((DCI0_5MHz_FDD_t *)dci_pdu)->cqi_req     = cqi_req;
      ((DCI0_5MHz_FDD_t *)dci_pdu)->cshift      = cshift;
      ((DCI0_5MHz_FDD_t *)dci_pdu)->TPC         = TPC;
      ((DCI0_5MHz_FDD_t *)dci_pdu)->mcs         = mcs;
      ((DCI0_5MHz_FDD_t *)dci_pdu)->ndi         = ndi;
      ((DCI0_5MHz_FDD_t *)dci_pdu)->rballoc     = rballoc;
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      ((DCI0_5MHz_FDD_t *)dci_pdu)->hopping     = hopping;
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      ((DCI0_5MHz_FDD_t *)dci_pdu)->type        = 0;
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      ((DCI0_5MHz_FDD_t *)dci_pdu)->padding     = 0;
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      dci_alloc->dci_length                     = sizeof_DCI0_5MHz_FDD_t; 
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    }
    
    break;
    
  case 50:
    if (frame_parms->frame_type == TDD) {
      ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->cqi_req = cqi_req;
      ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->dai     = dai;
      ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->cshift  = cshift;
      ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->TPC     = TPC;
      ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->mcs     = mcs;
      ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->ndi     = ndi;
      ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->rballoc = rballoc;
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      ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->hopping = hopping;
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      ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->type    = 0;
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      ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->padding = 0;
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      dci_alloc->dci_length                      = sizeof_DCI0_10MHz_TDD_1_6_t; 
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    } else {
      ((DCI0_10MHz_FDD_t *)dci_pdu)->cqi_req     = cqi_req;
      ((DCI0_10MHz_FDD_t *)dci_pdu)->cshift      = cshift;
      ((DCI0_10MHz_FDD_t *)dci_pdu)->TPC         = TPC;
      ((DCI0_10MHz_FDD_t *)dci_pdu)->mcs         = mcs;
      ((DCI0_10MHz_FDD_t *)dci_pdu)->ndi         = ndi;
      ((DCI0_10MHz_FDD_t *)dci_pdu)->rballoc     = rballoc;
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      ((DCI0_10MHz_FDD_t *)dci_pdu)->hopping     = hopping;
      ((DCI0_10MHz_FDD_t *)dci_pdu)->type        = 0;
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      ((DCI0_10MHz_FDD_t *)dci_pdu)->padding     = 0;
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      dci_alloc->dci_length                      = sizeof_DCI0_10MHz_FDD_t; 
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    }
    
    break;
    
  case 100:
    if (frame_parms->frame_type == TDD) {
      ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->cqi_req = cqi_req;
      ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->dai     = dai;
      ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->cshift  = cshift;
      ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->TPC     = TPC;
      ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->mcs     = mcs;
      ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->ndi     = ndi;
      ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->rballoc = rballoc;
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      ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->hopping = hopping;
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      ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->type    = 0;
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      ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->padding = 0;

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      dci_alloc->dci_length                      = sizeof_DCI0_20MHz_TDD_1_6_t; 
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    } else {
      ((DCI0_20MHz_FDD_t *)dci_pdu)->cqi_req     = cqi_req;
      ((DCI0_20MHz_FDD_t *)dci_pdu)->cshift      = cshift;
      ((DCI0_20MHz_FDD_t *)dci_pdu)->TPC         = TPC;
      ((DCI0_20MHz_FDD_t *)dci_pdu)->mcs         = mcs;
      ((DCI0_20MHz_FDD_t *)dci_pdu)->ndi         = ndi;
      ((DCI0_20MHz_FDD_t *)dci_pdu)->rballoc     = rballoc;
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      ((DCI0_20MHz_FDD_t *)dci_pdu)->hopping     = hopping;
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      ((DCI0_20MHz_FDD_t *)dci_pdu)->type        = 0;
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      ((DCI0_20MHz_FDD_t *)dci_pdu)->padding     = 0;
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      dci_alloc->dci_length                      = sizeof_DCI0_20MHz_FDD_t; 
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    }
    
      //printf("eNB: rb_alloc (20 MHz dci) %d\n",rballoc);
      break;
      
  default:
    LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
    DevParam (frame_parms->N_RB_DL, 0, 0);
    break;
  }
}

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void fill_ulsch(PHY_VARS_eNB *eNB,nfapi_ul_config_ulsch_pdu *ulsch_pdu,int frame,int subframe)
{
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  uint8_t harq_pid;
  uint8_t UE_id;
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  boolean_t new_ulsch = (find_ulsch(ulsch_pdu->ulsch_pdu_rel8.rnti,eNB,SEARCH_EXIST)==-1) ? TRUE : FALSE;

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  AssertFatal((UE_id=find_ulsch(ulsch_pdu->ulsch_pdu_rel8.rnti,eNB,SEARCH_EXIST_OR_FREE))>=0,
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	      "No existing/free UE ULSCH for rnti %x\n",ulsch_pdu->ulsch_pdu_rel8.rnti);

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  LTE_eNB_ULSCH_t *ulsch=eNB->ulsch[UE_id];
  LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms;

  int use_srs = 0;

  harq_pid = ulsch_pdu->ulsch_pdu_rel8.harq_process_number;

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  ulsch->harq_mask |= 1 << harq_pid;
2634 2635 2636

  ulsch->harq_processes[harq_pid]->frame                                 = frame;
  ulsch->harq_processes[harq_pid]->subframe                              = subframe;
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  ulsch->harq_processes[harq_pid]->handled                               = 0;
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  ulsch->harq_processes[harq_pid]->first_rb                              = ulsch_pdu->ulsch_pdu_rel8.resource_block_start;
  ulsch->harq_processes[harq_pid]->nb_rb                                 = ulsch_pdu->ulsch_pdu_rel8.number_of_resource_blocks;

  AssertFatal(ulsch->harq_processes[harq_pid]->nb_rb>0,"nb_rb = 0\n");

  ulsch->harq_processes[harq_pid]->dci_alloc                             = 1;
  ulsch->harq_processes[harq_pid]->rar_alloc                             = 0;
  ulsch->harq_processes[harq_pid]->n_DMRS                                = ulsch_pdu->ulsch_pdu_rel8.cyclic_shift_2_for_drms;
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  ulsch->harq_processes[harq_pid]->Nsymb_pusch                           = 12-(frame_parms->Ncp<<1)-(use_srs==0?0:1);
  ulsch->harq_processes[harq_pid]->srs_active                            = use_srs;
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  //Mapping of cyclic shift field in DCI format0 to n_DMRS2 (3GPP 36.211, Table 5.5.2.1.1-1)
  if(ulsch->harq_processes[harq_pid]->n_DMRS == 0)
    ulsch->harq_processes[harq_pid]->n_DMRS2 = 0;
  else if(ulsch->harq_processes[harq_pid]->n_DMRS == 1)
    ulsch->harq_processes[harq_pid]->n_DMRS2 = 6;
  else if(ulsch->harq_processes[harq_pid]->n_DMRS == 2)
    ulsch->harq_processes[harq_pid]->n_DMRS2 = 3;
  else if(ulsch->harq_processes[harq_pid]->n_DMRS == 3)
    ulsch->harq_processes[harq_pid]->n_DMRS2 = 4;
  else if(ulsch->harq_processes[harq_pid]->n_DMRS == 4)
    ulsch->harq_processes[harq_pid]->n_DMRS2 = 2;
  else if(ulsch->harq_processes[harq_pid]->n_DMRS == 5)
    ulsch->harq_processes[harq_pid]->n_DMRS2 = 8;
  else if(ulsch->harq_processes[harq_pid]->n_DMRS == 6)
    ulsch->harq_processes[harq_pid]->n_DMRS2 = 10;
  else if(ulsch->harq_processes[harq_pid]->n_DMRS == 7)
    ulsch->harq_processes[harq_pid]->n_DMRS2 = 9;
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  LOG_D(PHY,"[eNB %d][PUSCH %d] Frame %d, Subframe %d Programming PUSCH with n_DMRS2 %d (cshift %d) ulsch:ndi:%d ulsch_pdu:ndi:%d new_ulsch:%d status:%d ulsch_pdu:rvidx:%d\n",
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	eNB->Mod_id,harq_pid,frame,subframe,
        ulsch->harq_processes[harq_pid]->n_DMRS2,
        ulsch->harq_processes[harq_pid]->n_DMRS,
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	ulsch->harq_processes[harq_pid]->ndi, ulsch_pdu->ulsch_pdu_rel8.new_data_indication, new_ulsch, ulsch->harq_processes[harq_pid]->status,
	ulsch_pdu->ulsch_pdu_rel8.redundancy_version);
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  ulsch->harq_processes[harq_pid]->rvidx = ulsch_pdu->ulsch_pdu_rel8.redundancy_version;
  ulsch->harq_processes[harq_pid]->Qm    = ulsch_pdu->ulsch_pdu_rel8.modulation_type;
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  // Set O_ACK to 0 by default, will be set of DLSCH is scheduled and needs to be 
2679
  ulsch->harq_processes[harq_pid]->O_ACK         = 0;
2680

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  if ((ulsch->harq_processes[harq_pid]->status == SCH_IDLE) ||
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      (ulsch->harq_processes[harq_pid]->ndi    != ulsch_pdu->ulsch_pdu_rel8.new_data_indication) ||
	  (new_ulsch == TRUE)){
2684
    ulsch->harq_processes[harq_pid]->status        = ACTIVE;
2685
    
2686
    ulsch->harq_processes[harq_pid]->TBS           = ulsch_pdu->ulsch_pdu_rel8.size<<3;
2687
    
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    ulsch->harq_processes[harq_pid]->Msc_initial   = 12*ulsch_pdu->ulsch_pdu_rel8.number_of_resource_blocks;
2689
    ulsch->harq_processes[harq_pid]->Nsymb_initial = ulsch->harq_processes[harq_pid]->Nsymb_pusch;
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    ulsch->harq_processes[harq_pid]->round         = 0;
    ulsch->harq_processes[harq_pid]->ndi           = ulsch_pdu->ulsch_pdu_rel8.new_data_indication;
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    // note here, the CQI bits need to be kept constant as in initial transmission
    // set to 0 in initial transmission, and don't touch them during retransmissions
    // will be set if MAC has activated ULSCH_CQI_RI_PDU or ULSCH_CQI_HARQ_RI_PDU
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    ulsch->harq_processes[harq_pid]->Or1           = 0;
    ulsch->harq_processes[harq_pid]->Or2           = 0;
2697
  } 
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  else  ulsch->harq_processes[harq_pid]->round++;

2700
  ulsch->rnti = ulsch_pdu->ulsch_pdu_rel8.rnti;
2701
  LOG_D(PHY,"Filling ULSCH %x (UE_id %d) (new_ulsch %d) for Frame %d, Subframe %d : harq_pid %d, status %d, handled %d, first_rb %d, nb_rb %d, rvidx %d, Qm %d, TBS %d, round %d \n",
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	ulsch->rnti,
        UE_id,
        new_ulsch,
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	frame,
	subframe,
	harq_pid,
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	ulsch->harq_processes[harq_pid]->status,
	ulsch->harq_processes[harq_pid]->handled,
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	ulsch->harq_processes[harq_pid]->first_rb,
	ulsch->harq_processes[harq_pid]->nb_rb,
	ulsch->harq_processes[harq_pid]->rvidx,
	ulsch->harq_processes[harq_pid]->Qm,
	ulsch->harq_processes[harq_pid]->TBS,
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	ulsch->harq_processes[harq_pid]->round);  
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}

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int dump_dci(LTE_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci)
{
2720 2721 2722 2723
  switch (dci->format) {

  case format0:   // This is an UL SCH allocation so nothing here, inform MAC
    if ((frame_parms->frame_type == TDD) &&
2724
        (frame_parms->tdd_config>0))
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      switch(frame_parms->N_RB_DL) {
      case 6:
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        LOG_D(PHY,"DCI format0 (TDD, 1.5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu[0])[0],
              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
              ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
        break;

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      case 25:
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        LOG_D(PHY,"DCI format0 (TDD1-6, 5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu[0])[0],
              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
              ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
        break;

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      case 50:
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        LOG_D(PHY,"DCI format0 (TDD1-6, 10MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu[0])[0],
              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
              ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
        break;

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      case 100:
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        LOG_D(PHY,"DCI format0 (TDD1-6, 20MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu[0])[0],
              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
              ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
        break;

2782
      default:
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        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
        DevParam (frame_parms->N_RB_DL, 0, 0);
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        break;
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      }
    else if (frame_parms->frame_type == FDD)
      switch(frame_parms->N_RB_DL) {
      case 6:
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        LOG_D(PHY,"DCI format0 (FDD, 1.5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu[0])[0],
              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
              ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
        break;

2802
      case 25:
2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814
        LOG_D(PHY,"DCI format0 (FDD, 5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu[0])[0],
              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
              ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
        break;

2815
      case 50:
2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827
        LOG_D(PHY,"DCI format0 (FDD, 10MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu[0])[0],
              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
              ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
        break;

2828
      case 100:
2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840
        LOG_D(PHY,"DCI format0 (FDD, 20MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu[0])[0],
              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
              ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
        break;

2841
      default:
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2842 2843
        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
        DevParam (frame_parms->N_RB_DL, 0, 0);
2844
        break;
2845 2846 2847
      }
    else
      LOG_E(PHY,"Don't know how to handle TDD format 0 yet\n");
2848

2849 2850 2851 2852
    break;

  case format1:
    if ((frame_parms->frame_type == TDD) &&
2853
        (frame_parms->tdd_config>0))
2854 2855 2856

      switch(frame_parms->N_RB_DL) {
      case 6:
2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869
        LOG_D(PHY,"DCI format1 (TDD 1.5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu)[0],
              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->rah,
              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->rv,
              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
              ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->dai);
        break;

2870
      case 25:
2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883
        LOG_D(PHY,"DCI format1 (TDD 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu)[0],
              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->rah,
              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->rv,
              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
              ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->dai);
        break;

2884
      case 50:
2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897
        LOG_D(PHY,"DCI format1 (TDD 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu)[0],
              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->rah,
              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->rv,
              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
              ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->dai);
        break;

2898
      case 100:
2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911
        LOG_D(PHY,"DCI format1 (TDD 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu)[0],
              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->rah,
              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->rv,
              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
              ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->dai);
        break;

2912
      default:
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2913 2914
        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
        DevParam (frame_parms->N_RB_DL, 0, 0);
2915
        break;
2916 2917 2918 2919
      }
    else if (frame_parms->frame_type == FDD) {
      switch(frame_parms->N_RB_DL) {
      case 6:
2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931
        LOG_D(PHY,"DCI format1 (FDD, 1.5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu)[0],
              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rah,
              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rv,
              ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
        break;

2932
      case 25:
2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944
        LOG_D(PHY,"DCI format1 (FDD, 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu)[0],
              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->rah,
              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->rv,
              ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
        break;

2945
      case 50:
2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957
        LOG_D(PHY,"DCI format1 (FDD, 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu)[0],
              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->rah,
              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->rv,
              ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
        break;

2958
      case 100:
2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970
        LOG_D(PHY,"DCI format1 (FDD, 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
              dci->rnti,
              ((uint32_t*)&dci->dci_pdu)[0],
              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->rah,
              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->rv,
              ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
        break;

2971
      default:
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2972 2973
        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
        DevParam (frame_parms->N_RB_DL, 0, 0);
2974
        break;
2975 2976 2977
      }
    }

2978
    else
2979
      LOG_E(PHY,"Don't know how to handle TDD format 0 yet\n");
2980

2981
    break;
2982

2983 2984
  case format1A:  // This is DLSCH allocation for control traffic
    if ((frame_parms->frame_type == TDD) &&
2985
        (frame_parms->tdd_config>0)) {
2986 2987
      switch (frame_parms->N_RB_DL) {
      case 6:
2988 2989 2990 2991 2992 2993 2994 2995 2996
        LOG_D(PHY,"DCI format1A (TDD1-6, 1_5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
        LOG_D(PHY,"MCS %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
        LOG_D(PHY,"NDI %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
        LOG_D(PHY,"RV %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
        LOG_D(PHY,"TPC %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
        LOG_D(PHY,"DAI %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
2997 2998
        break;

2999
      case 25:
3000 3001 3002 3003 3004 3005 3006 3007 3008
        LOG_D(PHY,"DCI format1A (TDD1-6, 5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
        LOG_D(PHY,"RB_ALLOC %d (NB_RB %d)\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
        LOG_D(PHY,"MCS %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
        LOG_D(PHY,"NDI %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
        LOG_D(PHY,"RV %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
        LOG_D(PHY,"TPC %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
        LOG_D(PHY,"DAI %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
3009 3010
        break;

3011
      case 50:
3012 3013 3014 3015 3016 3017 3018 3019 3020
        LOG_D(PHY,"DCI format1A (TDD1-6, 10MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT50[((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
        LOG_D(PHY,"MCS %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
        LOG_D(PHY,"NDI %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
        LOG_D(PHY,"RV %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
        LOG_D(PHY,"TPC %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
        LOG_D(PHY,"DAI %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
3021 3022
        break;

3023
      case 100:
3024 3025 3026 3027 3028 3029 3030 3031 3032
        LOG_D(PHY,"DCI format1A (TDD1-6, 20MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT100[((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
        LOG_D(PHY,"MCS %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
        LOG_D(PHY,"NDI %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
        LOG_D(PHY,"RV %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
        LOG_D(PHY,"TPC %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
        LOG_D(PHY,"DAI %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
3033 3034
        break;

3035
      default:
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3036 3037
        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
        DevParam (frame_parms->N_RB_DL, 0, 0);
3038
        break;
3039
      }
3040 3041

    } else if (frame_parms->frame_type == FDD) {
3042 3043
      switch (frame_parms->N_RB_DL) {
      case 6:
3044 3045 3046 3047 3048 3049 3050 3051
        LOG_D(PHY,"DCI format1A(FDD, 1.5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
        LOG_D(PHY,"MCS %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
        LOG_D(PHY,"NDI %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
        LOG_D(PHY,"RV %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rv);
        LOG_D(PHY,"TPC %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
3052 3053
        break;

3054
      case 25:
3055 3056 3057 3058 3059 3060 3061 3062
        LOG_D(PHY,"DCI format1A(FDD, 5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
        LOG_D(PHY,"MCS %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
        LOG_D(PHY,"NDI %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
        LOG_D(PHY,"RV %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->rv);
        LOG_D(PHY,"TPC %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
3063 3064
        break;

3065
      case 50:
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3066 3067 3068 3069 3070 3071 3072 3073
        LOG_D(PHY,"DCI format1A(FDD, 10MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT50[((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
        LOG_D(PHY,"MCS %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
        LOG_D(PHY,"NDI %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
        LOG_D(PHY,"RV %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->rv);
        LOG_D(PHY,"TPC %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
3074 3075
        break;

3076
      case 100:
3077 3078 3079 3080 3081 3082 3083 3084
        LOG_D(PHY,"DCI format1A(FDD, 20MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
        LOG_D(PHY,"VRB_TYPE %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
        LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT100[((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
        LOG_D(PHY,"MCS %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
        LOG_D(PHY,"HARQ_PID %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
        LOG_D(PHY,"NDI %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
        LOG_D(PHY,"RV %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->rv);
        LOG_D(PHY,"TPC %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
3085 3086
        break;

3087
      default:
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3088 3089
        LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
        DevParam (frame_parms->N_RB_DL, 0, 0);
3090
        break;
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      }
    }
3093

3094
    break;
3095

3096 3097 3098 3099 3100
  case format1C:  // This is DLSCH allocation for control traffic
    switch (frame_parms->N_RB_DL) {
    case 6:
      LOG_D(PHY,"DCI format1C (1.5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
      LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",
3101
      ((DCI1C_1_5MHz_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT6[conv_1C_RIV(((DCI1C_1_5MHz_t *)&dci->dci_pdu[0])->rballoc,6)]);
3102 3103
      LOG_D(PHY,"MCS %d\n",((DCI1C_1_5MHz_t *)&dci->dci_pdu[0])->mcs);
      break;
3104

3105 3106 3107 3108 3109
    case 25:
      LOG_D(PHY,"DCI format1C (5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
      LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1C_5MHz_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[conv_1C_RIV(((DCI1C_5MHz_t *)&dci->dci_pdu[0])->rballoc,25)]);
      LOG_D(PHY,"MCS %d\n",((DCI1C_5MHz_t *)&dci->dci_pdu[0])->mcs);
      break;
3110

3111 3112 3113 3114 3115 3116
    case 50:
      LOG_D(PHY,"DCI format1C (10MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
      LOG_D(PHY,"Ngap %d\n",((DCI1C_10MHz_t *)&dci->dci_pdu[0])->Ngap);
      LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1C_10MHz_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT50[conv_1C_RIV(((DCI1C_10MHz_t *)&dci->dci_pdu[0])->rballoc,50)]);
      LOG_D(PHY,"MCS %d\n",((DCI1C_10MHz_t *)&dci->dci_pdu[0])->mcs);
      break;
3117

3118 3119 3120 3121 3122 3123
    case 100:
      LOG_D(PHY,"DCI format1C (20MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
      LOG_D(PHY,"Ngap %d\n",((DCI1C_20MHz_t *)&dci->dci_pdu[0])->Ngap);
      LOG_D(PHY,"RB_ALLOC %x (NB_RB %d)\n",((DCI1C_20MHz_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT50[conv_1C_RIV(((DCI1C_20MHz_t *)&dci->dci_pdu[0])->rballoc,100)]);
      LOG_D(PHY,"MCS %d\n",((DCI1C_20MHz_t *)&dci->dci_pdu[0])->mcs);
      break;
3124 3125


3126 3127 3128 3129 3130
    default:
      LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
        DevParam (frame_parms->N_RB_DL, 0, 0);
        break;
    }
3131

3132 3133

    break;
3134

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  case format2:
3136

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    if ((frame_parms->frame_type == TDD) &&
3138
        (frame_parms->tdd_config>0)) {
3139
      if (frame_parms->nb_antenna_ports_eNB == 2) {
3140 3141
        switch(frame_parms->N_RB_DL) {
        case 6:
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          LOG_D(PHY,"DCI format2 2 antennas (TDD 1.5 MHz), rnti %x (%x): rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tpmi
               );
          break;

        case 25:
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          LOG_D(PHY,"DCI format2 2 antennas (TDD 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tpmi);
          break;

        case 50:
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          LOG_D(PHY,"DCI format2 2 antennas (TDD 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->tpmi);
          break;

        case 100:
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          LOG_D(PHY,"DCI format2 2 antennas (TDD 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->tpmi);
          break;

        default:
          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
          DevParam (frame_parms->N_RB_DL, 0, 0);
          break;
        }
3222
      } else if (frame_parms->nb_antenna_ports_eNB == 4) {
3223 3224
        switch(frame_parms->N_RB_DL) {
        case 6:
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          LOG_D(PHY,"DCI format2 2 antennas (TDD 1.5 MHz), rnti %x (%x): rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi
               );
          break;

        case 25:
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          LOG_D(PHY,"DCI format2 2 antennas (TDD 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
          break;

        case 50:
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          LOG_D(PHY,"DCI format2 2 antennas (TDD 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
          break;

        case 100:
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          LOG_D(PHY,"DCI format2 2 antennas (TDD 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, TPC %d, dai %d, tb_swap %d, tpmi %d\n",
3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
          break;

        default:
          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
          DevParam (frame_parms->N_RB_DL, 0, 0);
          break;
        }
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      }
3306
    } else if (frame_parms->frame_type == FDD) {
3307
      if (frame_parms->nb_antenna_ports_eNB == 2) {
3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326
        switch(frame_parms->N_RB_DL) {
        case 6:
          LOG_D(PHY,"DCI format2 2 antennas (FDD, 1.5 MHz), rnti %x (%x):  rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 25:
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          LOG_D(PHY,"DCI format2 2 antennas (FDD, 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, swap %d, TPMI %d, TPC %d\n",

3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 50:
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3347
          LOG_D(PHY,"DCI format2 2 antennas (FDD, 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, tb_swap %d, tpmi %d, TPC %d\n",
3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 100:
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          LOG_D(PHY,"DCI format2 2 antennas (FDD, 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, tb_swap %d, tpmi %d, TPC %d\n",
3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        default:
          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
          DevParam (frame_parms->N_RB_DL, 0, 0);
          break;
        }
3387
      } else if (frame_parms->nb_antenna_ports_eNB == 4) {
3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407
        switch(frame_parms->N_RB_DL) {

        case 6:
          LOG_D(PHY,"DCI format2 4 antennas (FDD, 1.5 MHz), rnti %x (%x): rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 25:
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          LOG_D(PHY,"DCI format2 4 antennas (FDD, 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, tb_swap %d, tpmi %d, TPC %d\n",
3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 50:
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          LOG_D(PHY,"DCI format2 4 antennas (FDD, 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, tb_swap %d, tpmi %d, TPC %d\n",
3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 100:
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          LOG_D(PHY,"DCI format2 4 antennas (FDD, 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d|%d, harq_pid %d, ndi %d|%d, RV %d|%d, tb_swap %d, tpmi %d, TPC %d\n",
3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        default:
          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
          DevParam (frame_parms->N_RB_DL, 0, 0);
          break;
        }
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3466 3467
      }
    }
3468

3469
    else
3470
      LOG_E(PHY,"Don't know how to handle TDD format 0 yet\n");
3471

3472
    break;
3473

3474 3475 3476
  case format2A:

    if ((frame_parms->frame_type == TDD) &&
3477
        (frame_parms->tdd_config>0)) {
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      if (frame_parms->nb_antenna_ports_eNB == 2) {
3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498
        switch(frame_parms->N_RB_DL) {
        case 6:
          LOG_D(PHY,"DCI format2A 2 antennas (FDD 1.5 MHz), rnti %x (%x): rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d\n",
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2A_1_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap
               );
          break;

        case 25:
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          LOG_D(PHY,"DCI format2A 2 antennas (FDD 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d\n",
3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2A_5MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap);
          break;

        case 50:
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          LOG_D(PHY,"DCI format2A 2 antennas (FDD 10 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d\n",
3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2A_10MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap);
          break;

        case 100:
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          LOG_D(PHY,"DCI format2A 2 antennas (FDD 20 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d\n",
3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2A_20MHz_2A_TDD_t *)&dci->dci_pdu[0])->tb_swap);
          break;

        default:
          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
          DevParam (frame_parms->N_RB_DL, 0, 0);
          break;
        }
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      } else if (frame_parms->nb_antenna_ports_eNB == 4) {
3558 3559
        switch(frame_parms->N_RB_DL) {
        case 6:
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          LOG_D(PHY,"DCI format2A 4 antennas (TDD 1.5 MHz), rnti %x (%"PRIu64"): rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_1_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi
               );
          break;

        case 25:
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3579
          LOG_D(PHY,"DCI format2A 4 antennas (TDD 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_5MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
          break;

        case 50:
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3598
          LOG_D(PHY,"DCI format2A 4 antennas (TDD 10 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_10MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
          break;

        case 100:
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3617
          LOG_D(PHY,"DCI format2A 4 antennas (TDD 20 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, TPC %d, dai %d, tbswap %d, tpmi %d\n",
3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->TPC,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->dai,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_20MHz_4A_TDD_t *)&dci->dci_pdu[0])->tpmi);
          break;

        default:
          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
          DevParam (frame_parms->N_RB_DL, 0, 0);
          break;
        }
3640
      }
3641
    } else if (frame_parms->frame_type == FDD) {
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3642
      if (frame_parms->nb_antenna_ports_eNB == 2) {
3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660
        switch(frame_parms->N_RB_DL) {
        case 6:
          LOG_D(PHY,"DCI format2A 2 antennas (FDD, 1.5 MHz), rnti %x (%x):  rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, TPC %d\n",
                dci->rnti,
                ((uint32_t*)&dci->dci_pdu)[0],
                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_1_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 25:
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3661
          LOG_D(PHY,"DCI format2A 2 antennas (FDD, 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, TPC %d\n",
3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_5MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 50:
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3678
          LOG_D(PHY,"DCI format2A 2 antennas (FDD, 10 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, TPC %d\n",
3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_10MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 100:
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3695
          LOG_D(PHY,"DCI format2A 2 antennas (FDD, 20 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, TPC %d\n",
3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_20MHz_2A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        default:
          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
          DevParam (frame_parms->N_RB_DL, 0, 0);
          break;
        }
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3716
      } else if (frame_parms->nb_antenna_ports_eNB == 4) {
3717 3718 3719
        switch(frame_parms->N_RB_DL) {

        case 6:
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3720
          LOG_D(PHY,"DCI format2A 4 antennas (FDD, 1.5 MHz), rnti %x (%"PRIu64"): rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2A_1_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 25:
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3737
          LOG_D(PHY,"DCI format2A 4 antennas (FDD, 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2A_5MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 50:
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3755
          LOG_D(PHY,"DCI format2A 4 antennas (FDD, 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2A_10MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        case 100:
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3773
          LOG_D(PHY,"DCI format2A 4 antennas (FDD, 5 MHz), rnti %x (%"PRIu64"): rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, harq_pid %d, ndi1 %d, ndi2 %d, RV1 %d, RV2 %d, tb_swap %d, tpmi %d, TPC %d\n",
3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794
                dci->rnti,
                ((uint64_t*)&dci->dci_pdu)[0],
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rah,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rballoc,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs1,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->mcs2,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->harq_pid,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi1,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->ndi2,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv1,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->rv2,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->tb_swap,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->tpmi,
                ((DCI2A_20MHz_4A_FDD_t *)&dci->dci_pdu[0])->TPC);
          break;

        default:
          LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
          DevParam (frame_parms->N_RB_DL, 0, 0);
          break;
        }
3795 3796 3797
      }
    }

3798
    else
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3799
      LOG_E(PHY,"Don't know how to handle TDD format 0 yet\n");
3800

3801
    break;
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3802

3803 3804
  case format1E_2A_M10PRB:

3805
    LOG_D(PHY,"DCI format1E_2A_M10PRB, rnti %x (%8x): harq_pid %d, rah %d, rb_alloc %x, mcs %d, rv %d, tpmi %d, ndi %d, dl_power_offset %d\n",
3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817
          dci->rnti,
          ((uint32_t *)&dci->dci_pdu)[0],
          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->harq_pid,
          //((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->tb_swap,
          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rah,
          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rballoc,
          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->mcs,
          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rv,
          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->tpmi,
          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->ndi,
          ((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->dl_power_off
         );
3818 3819

    break;
3820

3821 3822 3823 3824
  default:
    LOG_E(PHY,"dci_tools.c: dump_dci, unknown format %d\n",dci->format);
    return(-1);
  }
3825

3826 3827 3828
  return(0);
}

3829
void extract_dci1A_info(uint8_t N_RB_DL, lte_frame_type_t frame_type, void *dci_pdu, DCI_INFO_EXTRACTED_t *pdci_info_extarcted)
3830
{
3831 3832 3833 3834 3835 3836 3837
    uint8_t harq_pid=0;
    uint32_t rballoc=0;
    uint8_t vrb_type=0;
    uint8_t mcs=0;
    uint8_t rv=0;
    uint8_t ndi=0;
    uint8_t TPC=0;
3838

3839
    uint8_t dai=0;
3840

3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863
    switch (N_RB_DL) {
    case 6:
        if (frame_type == TDD) {
            vrb_type = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
            mcs      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
            rballoc  = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
            rv       = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv;
            ndi      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
            TPC      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
            harq_pid = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
            dai      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->dai;
            //  printf("TDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
        } else {
            vrb_type = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->vrb_type;
            mcs      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs;
            rballoc  = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc;
            rv       = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv;
            ndi      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->ndi;
            TPC      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC;
            harq_pid  = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
            //printf("FDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
        }
        break;
3864

3865
    case 25:
3866

3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886
        if (frame_type == TDD) {
            vrb_type = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
            mcs      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
            rballoc  = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
            rv       = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv;
            ndi      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
            TPC      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
            harq_pid = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
            dai      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->dai;
            //printf("TDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
        } else {
            vrb_type = ((DCI1A_5MHz_FDD_t *)dci_pdu)->vrb_type;
            mcs      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs;
            rballoc  = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc;
            rv       = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv;
            ndi      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->ndi;
            TPC      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC;
            harq_pid  = ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid;
            //printf("FDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
        }
3887

3888
        break;
3889

3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909
    case 50:
        if (frame_type == TDD) {
            vrb_type = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
            mcs      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
            rballoc  = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
            rv       = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv;
            ndi      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->ndi;
            TPC      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC;
            harq_pid = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
            dai      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->dai;
            //  printf("TDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
        } else {
            vrb_type = ((DCI1A_10MHz_FDD_t *)dci_pdu)->vrb_type;
            mcs      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->mcs;
            rballoc  = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rballoc;
            rv       = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv;
            ndi      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->ndi;
            TPC      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC;
            harq_pid  = ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid;
            //printf("FDD 1A: mcs %d, vrb_type %d, rballoc %x,ndi %d, rv %d, TPC %d\n",mcs,vrb_type,rballoc,ndi,rv,TPC);
3910
        }
3911
        break;
3912

3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935
    case 100:
        if (frame_type == TDD) {
            vrb_type = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
            mcs      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
            rballoc  = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
            rv       = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rv;
            ndi      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->ndi;
            TPC      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC;
            harq_pid = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
            dai      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->dai;
            //  printf("TDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
        } else {
            vrb_type = ((DCI1A_20MHz_FDD_t *)dci_pdu)->vrb_type;
            mcs      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->mcs;
            rballoc  = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rballoc;
            rv       = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv;
            ndi      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->ndi;
            TPC      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC;
            harq_pid = ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid;
            //printf("FDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
        }
        break;
    }
3936

3937 3938 3939 3940 3941 3942 3943 3944 3945
    pdci_info_extarcted->vrb_type = vrb_type;
    pdci_info_extarcted->mcs1     = mcs;
    pdci_info_extarcted->rballoc  = rballoc;
    pdci_info_extarcted->rv1      = rv;
    pdci_info_extarcted->ndi1     = ndi;
    pdci_info_extarcted->TPC      = TPC;
    pdci_info_extarcted->harq_pid = harq_pid;
    pdci_info_extarcted->dai      = dai;
}
3946

3947 3948
void extract_dci1C_info(uint8_t N_RB_DL, lte_frame_type_t frame_type, void *dci_pdu, DCI_INFO_EXTRACTED_t *pdci_info_extarcted)
{
3949

3950 3951
    uint32_t rballoc=0;
    uint8_t mcs=0;
3952

3953 3954 3955 3956
    switch (N_RB_DL) {
        case 6:
          mcs             = ((DCI1C_5MHz_t *)dci_pdu)->mcs;
          rballoc         = conv_1C_RIV(((DCI1C_5MHz_t *)dci_pdu)->rballoc,6);
3957

3958
          break;
3959

3960 3961 3962
        case 25:
            mcs             = ((DCI1C_5MHz_t *)dci_pdu)->mcs;
            rballoc         = conv_1C_RIV(((DCI1C_5MHz_t *)dci_pdu)->rballoc,6);
3963

3964
          break;
3965

3966 3967 3968
        case 50:
            mcs             = ((DCI1C_10MHz_t *)dci_pdu)->mcs;
            rballoc         = conv_1C_RIV(((DCI1C_10MHz_t *)dci_pdu)->rballoc,6);
3969

3970
          break;
3971

3972 3973 3974 3975
        case 100:
            mcs             = ((DCI1C_20MHz_t *)dci_pdu)->mcs;
            rballoc         = conv_1C_RIV(((DCI1C_20MHz_t *)dci_pdu)->rballoc,6);
          break;
3976

3977 3978 3979
        default:
          AssertFatal(0,"Format 1C: Unknown N_RB_DL %d\n",N_RB_DL);
          break;
3980 3981
        }

3982 3983 3984
    pdci_info_extarcted->mcs1     = mcs;
    pdci_info_extarcted->rballoc  = rballoc;
}
3985

3986 3987
void extract_dci1_info(uint8_t N_RB_DL, lte_frame_type_t frame_type, void *dci_pdu, DCI_INFO_EXTRACTED_t *pdci_info_extarcted)
{
3988

3989 3990 3991 3992 3993 3994 3995
    uint32_t rballoc=0;
    uint8_t mcs=0;
    uint8_t rah=0;
    uint8_t rv=0;
    uint8_t TPC=0;
    uint8_t ndi=0;
    uint8_t harq_pid=0;
3996

3997 3998
    switch (N_RB_DL) {
    case 6:
3999
        if (frame_type == TDD) {
4000 4001 4002 4003 4004 4005 4006
            mcs       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->mcs;
            rballoc   = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rballoc;
            rah       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rah;
            rv        = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rv;
            TPC       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->TPC;
            ndi       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->ndi;
            harq_pid  = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
4007
        } else {
4008 4009 4010 4011 4012 4013 4014
            mcs      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->mcs;
            rah      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rah;
            rballoc  = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rballoc;
            rv       = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rv;
            TPC       = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->TPC;
            ndi      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->ndi;
            harq_pid = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
4015 4016
        }

4017
        break;
4018

4019
    case 25:
4020
        if (frame_type == TDD) {
4021 4022 4023 4024 4025 4026 4027
            mcs       = ((DCI1_5MHz_TDD_t *)dci_pdu)->mcs;
            rballoc   = ((DCI1_5MHz_TDD_t *)dci_pdu)->rballoc;
            rah       = ((DCI1_5MHz_TDD_t *)dci_pdu)->rah;
            rv        = ((DCI1_5MHz_TDD_t *)dci_pdu)->rv;
            TPC       = ((DCI1_5MHz_TDD_t *)dci_pdu)->TPC;
            ndi       = ((DCI1_5MHz_TDD_t *)dci_pdu)->ndi;
            harq_pid  = ((DCI1_5MHz_TDD_t *)dci_pdu)->harq_pid;
4028
        } else {
4029 4030 4031 4032 4033 4034 4035
            mcs      = ((DCI1_5MHz_FDD_t *)dci_pdu)->mcs;
            rah      = ((DCI1_5MHz_FDD_t *)dci_pdu)->rah;
            rballoc  = ((DCI1_5MHz_FDD_t *)dci_pdu)->rballoc;
            rv       = ((DCI1_5MHz_FDD_t *)dci_pdu)->rv;
            TPC      = ((DCI1_5MHz_FDD_t *)dci_pdu)->TPC;
            ndi      = ((DCI1_5MHz_FDD_t *)dci_pdu)->ndi;
            harq_pid = ((DCI1_5MHz_FDD_t *)dci_pdu)->harq_pid;
4036 4037
        }

4038
        break;
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Raymond Knopp committed
4039

4040
    case 50:
4041
        if (frame_type == TDD) {
4042 4043 4044 4045 4046 4047 4048
            mcs       = ((DCI1_10MHz_TDD_t *)dci_pdu)->mcs;
            rballoc   = ((DCI1_10MHz_TDD_t *)dci_pdu)->rballoc;
            rah       = ((DCI1_10MHz_TDD_t *)dci_pdu)->rah;
            rv        = ((DCI1_10MHz_TDD_t *)dci_pdu)->rv;
            TPC       = ((DCI1_10MHz_TDD_t *)dci_pdu)->TPC;
            ndi       = ((DCI1_10MHz_TDD_t *)dci_pdu)->ndi;
            harq_pid  = ((DCI1_10MHz_TDD_t *)dci_pdu)->harq_pid;
4049
        } else {
4050 4051 4052 4053 4054 4055 4056
            mcs      = ((DCI1_10MHz_FDD_t *)dci_pdu)->mcs;
            rah      = ((DCI1_10MHz_FDD_t *)dci_pdu)->rah;
            rballoc  = ((DCI1_10MHz_FDD_t *)dci_pdu)->rballoc;
            rv       = ((DCI1_10MHz_FDD_t *)dci_pdu)->rv;
            TPC      = ((DCI1_10MHz_FDD_t *)dci_pdu)->TPC;
            ndi      = ((DCI1_10MHz_FDD_t *)dci_pdu)->ndi;
            harq_pid = ((DCI1_10MHz_FDD_t *)dci_pdu)->harq_pid;
4057 4058
        }

4059
        break;
4060

4061
    case 100:
4062
        if (frame_type == TDD) {
4063 4064 4065 4066 4067 4068 4069
            mcs       = ((DCI1_20MHz_TDD_t *)dci_pdu)->mcs;
            rballoc   = ((DCI1_20MHz_TDD_t *)dci_pdu)->rballoc;
            rah       = ((DCI1_20MHz_TDD_t *)dci_pdu)->rah;
            rv        = ((DCI1_20MHz_TDD_t *)dci_pdu)->rv;
            TPC        = ((DCI1_20MHz_TDD_t *)dci_pdu)->TPC;
            ndi       = ((DCI1_20MHz_TDD_t *)dci_pdu)->ndi;
            harq_pid  = ((DCI1_20MHz_TDD_t *)dci_pdu)->harq_pid;
4070
        } else {
4071 4072 4073 4074 4075 4076 4077
            mcs      = ((DCI1_20MHz_FDD_t *)dci_pdu)->mcs;
            rah      = ((DCI1_20MHz_FDD_t *)dci_pdu)->rah;
            rballoc  = ((DCI1_20MHz_FDD_t *)dci_pdu)->rballoc;
            rv       = ((DCI1_20MHz_FDD_t *)dci_pdu)->rv;
            TPC      = ((DCI1_20MHz_FDD_t *)dci_pdu)->TPC;
            ndi      = ((DCI1_20MHz_FDD_t *)dci_pdu)->ndi;
            harq_pid = ((DCI1_20MHz_FDD_t *)dci_pdu)->harq_pid;
4078 4079
        }

4080
        break;
4081
    }
4082

4083 4084 4085 4086 4087 4088 4089
    pdci_info_extarcted->mcs1     = mcs;
    pdci_info_extarcted->rah      = rah;
    pdci_info_extarcted->rballoc  = rballoc;
    pdci_info_extarcted->rv1      = rv;
    pdci_info_extarcted->TPC      = TPC;
    pdci_info_extarcted->ndi1     = ndi;
    pdci_info_extarcted->harq_pid = harq_pid;
4090

4091
}
4092

4093 4094
void extract_dci2_info(uint8_t N_RB_DL, lte_frame_type_t frame_type, uint8_t nb_antenna_ports_eNB, void *dci_pdu, DCI_INFO_EXTRACTED_t *pdci_info_extarcted)
{
4095

4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109
    uint32_t rballoc=0;
    uint8_t rah=0;
    uint8_t mcs1=0;
    uint8_t mcs2=0;
    uint8_t rv1=0;
    uint8_t rv2=0;
    uint8_t ndi1=0;
    uint8_t ndi2=0;
    uint8_t tbswap=0;
    uint8_t tpmi=0;
    uint8_t harq_pid=0;
    uint8_t TPC=0;

    switch (N_RB_DL) {
4110

4111
    case 6:
4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170
        if (nb_antenna_ports_eNB == 2) {
            if (frame_type == TDD) {
                rah       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->ndi2;
            } else {
                rah       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->ndi2;
            }
        } else if (nb_antenna_ports_eNB == 4) {
            if (frame_type == TDD) {
                rah       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->ndi2;
            } else {
                rah       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->ndi2;
            }
        } else {
            LOG_E(PHY,"UE: Format2 DCI: unsupported number of TX antennas %d\n",nb_antenna_ports_eNB);
        }
4171

4172
        break;
4173

4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233
    case 25:
        if (nb_antenna_ports_eNB == 2) {
            if (frame_type == TDD) {
                rah       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->ndi2;
            } else {
                rah       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->ndi2;
            }
        } else if (nb_antenna_ports_eNB == 4) {
            if (frame_type == TDD) {
                rah       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->ndi2;
            } else {
                rah       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->ndi2;
            }
        } else {
            LOG_E(PHY,"UE: Format2 DCI: unsupported number of TX antennas %d\n",nb_antenna_ports_eNB);
        }
4234

4235
        break;
4236

4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296
    case 50:
        if (nb_antenna_ports_eNB == 2) {
            if (frame_type == TDD) {
                rah       = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->ndi2;
            } else {
                rah       = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->ndi2;
            }
        } else if (nb_antenna_ports_eNB == 4) {
            if (frame_type == TDD) {
                rah       = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->ndi2;
            } else {
                rah       = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->ndi2;
            }
        } else {
            LOG_E(PHY,"UE: Format2A DCI: unsupported number of TX antennas %d\n",nb_antenna_ports_eNB);
        }
4297

4298
        break;
4299

4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358
    case 100:
        if (nb_antenna_ports_eNB == 2) {
            if (frame_type == TDD) {
                rah       = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->ndi2;
            } else {
                rah       = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->ndi2;
            }
        } else if (nb_antenna_ports_eNB == 4) {
            if (frame_type == TDD) {
                rah       = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->ndi2;
            } else {
                rah       = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rah;
                mcs1      = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->mcs1;
                mcs2      = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->mcs2;
                rballoc   = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rballoc;
                rv1       = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rv1;
                rv2       = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rv2;
                harq_pid  = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->harq_pid;
                tbswap    = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->tb_swap;
                tpmi      = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->tpmi;
                TPC       = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->TPC;
                ndi1      = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->ndi1;
                ndi2      = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->ndi2;
            }
        } else {
            LOG_E(PHY,"UE: Format2A DCI: unsupported number of TX antennas %d\n",nb_antenna_ports_eNB);
4359
        }
4360

4361
        break;
4362
    }
4363

4364 4365
    pdci_info_extarcted->rah      = rah;
    pdci_info_extarcted->mcs1     = mcs1;
4366
    pdci_info_extarcted->mcs2     = mcs2;
4367 4368 4369 4370 4371 4372 4373 4374 4375
    pdci_info_extarcted->rv1      = rv1;
    pdci_info_extarcted->rv2      = rv2;
    pdci_info_extarcted->harq_pid = harq_pid;
    pdci_info_extarcted->rballoc  = rballoc;
    pdci_info_extarcted->tb_swap  = tbswap;
    pdci_info_extarcted->tpmi     = tpmi;
    pdci_info_extarcted->TPC      = TPC;
    pdci_info_extarcted->ndi1     = ndi1;
    pdci_info_extarcted->ndi2     = ndi2;
4376

4377
}
4378

4379 4380
void extract_dci2A_info(uint8_t N_RB_DL, lte_frame_type_t frame_type, uint8_t nb_antenna_ports_eNB, void *dci_pdu, DCI_INFO_EXTRACTED_t *pdci_info_extarcted)
{
4381

4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396
    uint32_t rballoc=0;
    uint8_t rah=0;
    uint8_t mcs1=0;
    uint8_t mcs2=0;
    uint8_t rv1=0;
    uint8_t rv2=0;
    uint8_t ndi1=0;
    uint8_t ndi2=0;
    uint8_t tbswap=0;
    uint8_t tpmi=0;
    uint8_t harq_pid=0;
    uint8_t TPC=0;

    AssertFatal( (nb_antenna_ports_eNB == 2) || (nb_antenna_ports_eNB == 4), "unsupported nb_antenna_ports_eNB %d\n", nb_antenna_ports_eNB);
    switch (N_RB_DL) {
4397 4398

    case 6:
4399
      if (nb_antenna_ports_eNB == 2) {
4400 4401 4402 4403 4404 4405 4406 4407 4408 4409
        if (frame_type == TDD) {
          mcs1      = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
          rv1       = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
4410
          TPC       = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->TPC;
4411 4412 4413 4414 4415 4416 4417 4418 4419 4420
        } else {
          mcs1      = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
          rv1       = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
4421
          TPC       = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->TPC;
4422
        }
4423
      } else if (nb_antenna_ports_eNB == 4) {
4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434
        if (frame_type == TDD) {
          mcs1      = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
          rv1       = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
          tpmi      = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
4435
          TPC       = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->TPC;
4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446
        } else {
          mcs1      = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
          rv1       = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
          tpmi      = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
4447
          TPC       = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->TPC;
4448
        }
4449
      }
4450

4451
      break;
4452

4453
    case 25:
4454
      if (nb_antenna_ports_eNB == 2) {
4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465
        if (frame_type == TDD) {
          mcs1      = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
4466
          TPC       = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->TPC;
4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477
        } else {
          mcs1      = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
4478
          TPC       = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->TPC;
4479
        }
4480
      } else if (nb_antenna_ports_eNB == 4) {
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        if (frame_type == TDD) {
          mcs1      = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
          tpmi      = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
4493
          TPC       = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->TPC;
4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505
        } else {
          mcs1      = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
          tpmi      = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
4506
          TPC       = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->TPC;
4507
        }
4508 4509
      }
      break;
4510

4511
    case 50:
4512
      if (nb_antenna_ports_eNB == 2) {
4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523
        if (frame_type == TDD) {
          mcs1      = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->tb_swap;
4524
          TPC       = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->TPC;
4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535
        } else {
          mcs1      = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->tb_swap;
4536
          TPC       = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->TPC;
4537
        }
4538
      } else if (nb_antenna_ports_eNB == 4) {
4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550
        if (frame_type == TDD) {
          mcs1      = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->tb_swap;
          tpmi      = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->tpmi;
4551
          TPC       = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->TPC;
4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563
        } else {
          mcs1      = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->tb_swap;
          tpmi      = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->tpmi;
4564 4565
          TPC       = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->TPC;
        }
4566
      }
4567

4568 4569 4570
      break;

    case 100:
4571
      if (nb_antenna_ports_eNB == 2) {
4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582
        if (frame_type == TDD) {
          mcs1      = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->tb_swap;
4583
          TPC       = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->TPC;
4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594
        } else {
          mcs1      = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->tb_swap;
4595
          TPC       = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->TPC;
4596
        }
4597
      } else if (nb_antenna_ports_eNB == 4) {
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        if (frame_type == TDD) {
          mcs1      = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->tb_swap;
          tpmi      = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->tpmi;
4610
          TPC       = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->TPC;
4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622
        } else {
          mcs1      = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->mcs1;
          mcs2      = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->mcs2;
          rballoc   = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rballoc;
          rah       = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rah;
          rv1       = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rv1;
          rv2       = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rv2;
          ndi1      = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->ndi1;
          ndi2      = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->ndi2;
          harq_pid  = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->harq_pid;
          tbswap    = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->tb_swap;
          tpmi    = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->tpmi;
4623
          TPC     = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->TPC;
4624
        }
4625
      }
4626

4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650
      break;
    }

    pdci_info_extarcted->mcs1     = mcs1;
    pdci_info_extarcted->mcs2     = mcs2;
    pdci_info_extarcted->rballoc  = rballoc;
    pdci_info_extarcted->rah      = rah;
    pdci_info_extarcted->rv1      = rv1;
    pdci_info_extarcted->rv2      = rv2;
    pdci_info_extarcted->ndi1     = ndi1;
    pdci_info_extarcted->ndi2     = ndi2;
    pdci_info_extarcted->harq_pid = harq_pid;
    pdci_info_extarcted->tb_swap  = tbswap;
    pdci_info_extarcted->TPC      = TPC;
    pdci_info_extarcted->tpmi     = tpmi;
}

int check_dci_format1_1a_coherency(DCI_format_t dci_format,
        uint8_t N_RB_DL,
        uint16_t rnti,
        uint16_t tc_rnti,
        uint16_t si_rnti,
        uint16_t ra_rnti,
        uint16_t p_rnti,
4651 4652
        uint32_t frame,
        uint8_t  subframe,
4653 4654 4655 4656 4657 4658 4659 4660
        DCI_INFO_EXTRACTED_t *pdci_info_extarcted,
        LTE_DL_UE_HARQ_t *pdlsch0_harq)
{
    uint8_t  harq_pid  = pdci_info_extarcted->harq_pid;
    uint32_t rballoc   = pdci_info_extarcted->rballoc;
    uint8_t  mcs1      = pdci_info_extarcted->mcs1;
    uint8_t  TPC       = pdci_info_extarcted->TPC;
    uint8_t  rah       = pdci_info_extarcted->rah;
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hbilel committed
4661 4662 4663 4664
#ifdef DEBUG_DCI
    uint8_t  rv1       = pdci_info_extarcted->rv1;
    uint8_t  ndi1      = pdci_info_extarcted->ndi1;
#endif
4665 4666

    uint8_t  NPRB    = 0;
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    long long int RIV_max = 0;

#ifdef DEBUG_DCI
4670
    LOG_I(PHY,"[DCI-FORMAT-1-1A] AbsSubframe %d.%d dci_format %d\n", frame, subframe, dci_format);
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    LOG_I(PHY,"[DCI-FORMAT-1-1A] rnti       %x\n",  rnti);
    LOG_I(PHY,"[DCI-FORMAT-1-1A] harq_pid   %d\n", harq_pid);
    LOG_I(PHY,"[DCI-FORMAT-1-1A] rah        %d\n", rah);
    LOG_I(PHY,"[DCI-FORMAT-1-1A] rballoc    %x\n", rballoc);
    LOG_I(PHY,"[DCI-FORMAT-1-1A] mcs1       %d\n", mcs1);
    LOG_I(PHY,"[DCI-FORMAT-1-1A] rv1        %d\n", rv1);
    LOG_I(PHY,"[DCI-FORMAT-1-1A] ndi1       %d\n", ndi1);
    LOG_I(PHY,"[DCI-FORMAT-1-1A] TPC        %d\n", TPC);
#endif
4680 4681 4682 4683 4684 4685 4686 4687


    // I- check dci content minimum coherency
    if( ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti)) && harq_pid > 0)
    {
        return(0);
    }

4688
    if(harq_pid>=8)
4689
    {
4690
      //        LOG_I(PHY,"bad harq id \n");
4691 4692 4693 4694 4695
        return(0);
    }

    if(dci_format == format1 && ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti)) )
    {
4696
      //        LOG_I(PHY,"bad dci format \n");
4697 4698 4699 4700 4701 4702 4703 4704
        return(0);
    }


    if( mcs1 > 28)
    {
        if(pdlsch0_harq->round == 0)
        {
4705
	  //            LOG_I(PHY,"bad dci mcs + round \n");
4706 4707 4708 4709 4710
            return(0);
        }

        if((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti))
        {
4711
	  //            LOG_I(PHY,"bad dci mcs + rnti  \n");
4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738
            return(0);
        }
    }

    if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti))
    {
        NPRB = (TPC&1) + 2;
        switch (N_RB_DL) {
        case 6:
            RIV_max  = RIV_max6;
            break;
        case 25:
            RIV_max  = RIV_max25;
            break;
        case 50:
            RIV_max  = RIV_max50;
            break;
        case 100:
            RIV_max  = RIV_max100;
            break;
        }
    }
    else
    {
        switch (N_RB_DL) {
        case 6:
            NPRB     = RIV2nb_rb_LUT6[rballoc];//NPRB;
4739 4740 4741 4742
            if(rah)
              RIV_max  = RIV_max6;
            else
              RIV_max  = 0x3F;
4743 4744 4745
            break;
        case 25:
            NPRB     = RIV2nb_rb_LUT25[rballoc];//NPRB;
4746 4747 4748 4749
            if(rah)
              RIV_max  = RIV_max25;
            else
              RIV_max  = 0x1FFF;
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            break;
        case 50:
            NPRB     = RIV2nb_rb_LUT50[rballoc];//NPRB;
4753 4754 4755 4756
            if(rah)
              RIV_max  = RIV_max50;
            else
              RIV_max  = 0x1FFFF;
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            break;
        case 100:
            NPRB     = RIV2nb_rb_LUT100[rballoc];//NPRB;
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            if(rah)
              RIV_max  = RIV_max100;
            else
              RIV_max  =  0x1FFFFFF;
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            break;
        }
    }


    if(dci_format == format1)
    {
        NPRB = conv_nprb(rah, rballoc, N_RB_DL);
    }


    if(rballoc > RIV_max)
    {
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      //        LOG_I(PHY,"bad dci rballoc rballoc %d  RIV_max %lld \n",rballoc, RIV_max);
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        // DCI false detection
        return(0);
    }

    if(NPRB == 0)
    {
        // DCI false detection
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      //        LOG_I(PHY,"bad NPRB = 0 \n");
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        return(0);
    }

    // this a retransmission
    if(pdlsch0_harq->round>0)
    {
        // compare old TBS to new TBS
        if((mcs1<29) && (pdlsch0_harq->TBS != TBStable[get_I_TBS(mcs1)][NPRB-1]))
        {
            // this is an eNB issue
            // retransmisison but old and new TBS are different !!!
            // work around, consider it as a new transmission
            LOG_E(PHY,"Format1A Retransmission but TBS are different: consider it as new transmission !!! \n");
            pdlsch0_harq->round = 0;
            //return(0); // ?? to cross check
        }
    }

    return(1);
}

int check_dci_format1c_coherency(uint8_t N_RB_DL,
                                 DCI_INFO_EXTRACTED_t *pdci_info_extarcted,
                                 uint16_t rnti,
                                 uint16_t si_rnti,
                                 uint16_t ra_rnti,
                                 uint16_t p_rnti,
                                 LTE_DL_UE_HARQ_t *pdlsch0_harq)
{
    uint32_t rballoc = pdci_info_extarcted->rballoc;

    uint8_t  NPRB    = 0;
    uint32_t RIV_max = 0;

    // I- check dci content minimum coherency

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    if((rnti!=si_rnti) && (rnti!=p_rnti) && (rnti!=ra_rnti))
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      return(0);

    switch (N_RB_DL) {
    case 6:
      NPRB     = RIV2nb_rb_LUT6[rballoc];//NPRB;
      RIV_max  = RIV_max6;
    break;
    case 25:
      NPRB     = RIV2nb_rb_LUT25[rballoc];//NPRB;
      RIV_max  = RIV_max25;
    break;
    case 50:
      NPRB     = RIV2nb_rb_LUT50[rballoc];//NPRB;
      RIV_max  = RIV_max50;
    break;
    case 100:
      NPRB     = RIV2nb_rb_LUT100[rballoc];//NPRB;
      RIV_max  = RIV_max100;
    break;
    }

   if(rballoc > RIV_max)
   {
      // DCI false detection
      return(0);
   }

   if(NPRB == 0)
   {
      // DCI false detection
      return(0);
   }

   return(1);
}

int check_dci_format2_2a_coherency(DCI_format_t dci_format,
                                   uint8_t N_RB_DL,
                                   DCI_INFO_EXTRACTED_t *pdci_info_extarcted,
                                   uint16_t rnti,
                                   uint16_t si_rnti,
                                   uint16_t ra_rnti,
                                   uint16_t p_rnti,
                                   LTE_DL_UE_HARQ_t *pdlsch0_harq,
                                   LTE_DL_UE_HARQ_t *pdlsch1_harq)
{
    uint8_t  rah  = pdci_info_extarcted->rah;
    uint8_t  mcs1 = pdci_info_extarcted->mcs1;
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    uint8_t  mcs2 = pdci_info_extarcted->mcs2;
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    uint8_t  rv1  = pdci_info_extarcted->rv1;
    uint8_t  rv2  = pdci_info_extarcted->rv2;
    uint8_t  harq_pid = pdci_info_extarcted->harq_pid;
    uint32_t rballoc  = pdci_info_extarcted->rballoc;
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#ifdef DEBUG_DCI
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    uint8_t  ndi1     = pdci_info_extarcted->ndi1;
    uint8_t  ndi2     = pdci_info_extarcted->ndi2;
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#endif
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    uint8_t  NPRB    = 0;
    long long RIV_max = 0;

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#ifdef DEBUG_DCI
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    LOG_I(PHY, "extarcted dci - dci_format %d \n", dci_format);
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    LOG_I(PHY, "extarcted dci - rnti       %d \n", rnti);
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    LOG_I(PHY, "extarcted dci - rah        %d \n", rah);
    LOG_I(PHY, "extarcted dci - mcs1       %d \n", mcs1);
    LOG_I(PHY, "extarcted dci - mcs2       %d \n", mcs2);
    LOG_I(PHY, "extarcted dci - rv1        %d \n", rv1);
    LOG_I(PHY, "extarcted dci - rv2        %d \n", rv2);
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    //LOG_I(PHY, "extarcted dci - ndi1       %d \n", ndi1);
    //LOG_I(PHY, "extarcted dci - ndi2       %d \n", ndi2);
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    LOG_I(PHY, "extarcted dci - rballoc    %x \n", rballoc);
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    LOG_I(PHY, "extarcted dci - harq pid   %d \n", harq_pid);
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    LOG_I(PHY, "extarcted dci - round0     %d \n", pdlsch0_harq->round);
    LOG_I(PHY, "extarcted dci - round1     %d \n", pdlsch1_harq->round);
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#endif
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    // I- check dci content minimum coherency
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    if(harq_pid>=8)
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    {
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      //        LOG_I(PHY,"bad harq pid\n");
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      return(0);
    }

    if( (rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti) )
    {
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      //        LOG_I(PHY,"bad rnti\n");
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        return(0);
    }


    if( mcs1 > 28)
    {
      if(pdlsch0_harq->round == 0)
      {
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	//          LOG_I(PHY,"bad mcs1\n");
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        return(0);
      }
    }

    if( mcs2 > 28)
    {
      if(pdlsch1_harq->round == 0)
      {
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	//          LOG_I(PHY,"bad mcs2\n");
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          return(0);
      }
    }


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    if((pdlsch0_harq->round == 0) && (rv1 > 0) && (mcs1 != 0))
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    {
      // DCI false detection
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      //        LOG_I(PHY,"bad rv1\n");
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      return(0);
    }

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    if((pdlsch1_harq->round == 0) && (rv2 > 0) && (mcs2 != 0))
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    {
      // DCI false detection
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      //        LOG_I(PHY,"bad rv2\n");
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      return(0);
    }


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    switch (N_RB_DL) {
    case 6:
        if (rah == 0)
        {
            //RBG = 1;
            RIV_max = 0x3F;
        }
        else
        {
            RIV_max  = RIV_max6;
        }
        break;
    case 25:
        if (rah == 0)
        {
            //RBG = 2;
            RIV_max = 0x1FFF;
        }
        else
        {
            RIV_max  = RIV_max25;
        }
        break;
    case 50:
        if (rah == 0)
        {
            //RBG = 3;
            RIV_max = 0x1FFFF;
        }
        else
        {
            RIV_max  = RIV_max50;
        }
        break;
    case 100:
        if (rah == 0)
        {
            //RBG = 4;
            RIV_max  = 0x1FFFFFF;
        }
        else
        {
            RIV_max  = RIV_max100;
        }
        break;
    }

    NPRB = conv_nprb(rah,
                     rballoc,
                     N_RB_DL);



   if( (rballoc > RIV_max) && (rah == 1) )
   {
      // DCI false detection
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     //       LOG_I(PHY,"bad rballoc %d RIV_max %lld\n", rballoc, RIV_max);
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      return(0);
   }

   if(NPRB == 0)
   {
      // DCI false detection
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     //       LOG_I(PHY,"bad NPRB\n");
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      return(0);
   }

   return(1);
}

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void compute_llr_offset(LTE_DL_FRAME_PARMS *frame_parms,
                        LTE_UE_PDCCH *pdcch_vars,
                        LTE_UE_PDSCH *pdsch_vars,
                        LTE_DL_UE_HARQ_t *dlsch0_harq,
                        uint8_t nb_rb_alloc,
                        uint8_t subframe)
{
    uint32_t pbch_pss_sss_re;
    uint32_t crs_re;
    uint32_t granted_re;
    uint32_t data_re;
    uint32_t llr_offset;
    uint8_t symbol;
    uint8_t symbol_mod;

    pdsch_vars->llr_offset[pdcch_vars->num_pdcch_symbols] = 0;

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    LOG_I(PHY,"compute_llr_offset:  nb RB %d - Qm %d \n", nb_rb_alloc, dlsch0_harq->Qm);
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    //dlsch0_harq->rb_alloc_even;
    //dlsch0_harq->rb_alloc_odd;

    for(symbol=pdcch_vars->num_pdcch_symbols; symbol<frame_parms->symbols_per_tti; symbol++)
    {
        symbol_mod = (symbol >= (7-frame_parms->Ncp))? (symbol-(7-frame_parms->Ncp)) : symbol;
        if((symbol_mod == 0) || symbol_mod == (4-frame_parms->Ncp))
        {
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	  if (frame_parms->nb_antennas_tx == 2) 
	    crs_re = 4;
	  else
	    crs_re = 2;
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        }
        else
        {
            crs_re = 0;
        }

        granted_re = nb_rb_alloc * (12-crs_re);
        pbch_pss_sss_re = adjust_G2(frame_parms,dlsch0_harq->rb_alloc_even,dlsch0_harq->Qm,subframe,symbol);
        pbch_pss_sss_re = (double)pbch_pss_sss_re * ((double)(12-crs_re)/12);
        data_re = granted_re - pbch_pss_sss_re;
        llr_offset = data_re * dlsch0_harq->Qm * 2;

        pdsch_vars->llr_length[symbol]   = data_re;
        if(symbol < (frame_parms->symbols_per_tti-1))
          pdsch_vars->llr_offset[symbol+1] = pdsch_vars->llr_offset[symbol] + llr_offset;

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	LOG_I(PHY,"Granted Re subframe %d / symbol %d => %d (%d RBs)\n", subframe, symbol_mod, granted_re,dlsch0_harq->nb_rb);
	LOG_I(PHY,"Pbch/PSS/SSS Re subframe %d / symbol %d => %d \n", subframe, symbol_mod, pbch_pss_sss_re);
	LOG_I(PHY,"CRS Re Per PRB subframe %d / symbol %d => %d \n", subframe, symbol_mod, crs_re);
	LOG_I(PHY,"Data Re subframe %d / symbol %d => %d \n", subframe, symbol_mod, data_re);
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        LOG_I(PHY,"Data Re subframe %d-symbol %d => llr length %d, llr offset %d \n", subframe, symbol,
              pdsch_vars->llr_length[symbol], pdsch_vars->llr_offset[symbol]);
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    }
}
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void prepare_dl_decoding_format1_1A(DCI_format_t dci_format,
                                    uint8_t N_RB_DL,
                                    DCI_INFO_EXTRACTED_t *pdci_info_extarcted,
                                    LTE_DL_FRAME_PARMS *frame_parms,
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                                    LTE_UE_PDCCH *pdcch_vars,
                                    LTE_UE_PDSCH *pdsch_vars,
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                                    uint8_t  subframe,
                                    uint16_t rnti,
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									uint16_t tc_rnti,
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                                    uint16_t si_rnti,
                                    uint16_t ra_rnti,
                                    uint16_t p_rnti,
                                    LTE_DL_UE_HARQ_t *pdlsch0_harq,
                                    LTE_UE_DLSCH_t *pdlsch0)
{

    uint8_t  harq_pid  = pdci_info_extarcted->harq_pid;
    uint8_t  vrb_type  = pdci_info_extarcted->vrb_type;
    uint32_t rballoc   = pdci_info_extarcted->rballoc;
    uint8_t  mcs1      = pdci_info_extarcted->mcs1;
    uint8_t  rv1       = pdci_info_extarcted->rv1;
    uint8_t  ndi1      = pdci_info_extarcted->ndi1;
    uint8_t  TPC       = pdci_info_extarcted->TPC;
    uint8_t  rah       = pdci_info_extarcted->rah;
    uint8_t  dai       = pdci_info_extarcted->dai;

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    uint8_t  NPRB      = 0;
    uint8_t  NPRB4TBS  = 0;
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    if(dci_format == format1A)
    {
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      switch (N_RB_DL) {
      case 6:
	NPRB     = RIV2nb_rb_LUT6[rballoc];
	break;
      case 25:
	NPRB     = RIV2nb_rb_LUT25[rballoc];
	break;
      case 50:
	NPRB     = RIV2nb_rb_LUT50[rballoc];
	break;
      case 100:
	NPRB     = RIV2nb_rb_LUT100[rballoc];
	break;
      }
      if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti))
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        {
5125
	  NPRB4TBS = (TPC&1) + 2;
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        }
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      else
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        {
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	  NPRB4TBS = NPRB;
	  /*
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            switch (N_RB_DL) {
            case 6:
                NPRB     = RIV2nb_rb_LUT6[rballoc];//NPRB;
                break;
            case 25:
                NPRB     = RIV2nb_rb_LUT25[rballoc];//NPRB;
                break;
            case 50:
                NPRB     = RIV2nb_rb_LUT50[rballoc];//NPRB;
                break;
            case 100:
                NPRB     = RIV2nb_rb_LUT100[rballoc];//NPRB;
                break;
            }
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	  */
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        }
    }
    else // format1
    {
        NPRB = conv_nprb(rah, rballoc, N_RB_DL);
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	NPRB4TBS=NPRB;
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    }

    pdlsch0->current_harq_pid = harq_pid;
    pdlsch0->active           = 1;
    pdlsch0->rnti             = rnti;
    if(dci_format == format1A)
        pdlsch0->harq_ack[subframe].vDAI_DL = dai+1;

    if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti))
    {
        pdlsch0_harq->round    = 0;
        pdlsch0_harq->status   = ACTIVE;
    }
    else //CRNTI
    {
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    	if (rnti == tc_rnti) {
			//fix for standalone Contention Resolution Id
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	  pdlsch0_harq->DCINdi = (uint8_t)-1;
	  LOG_D(PHY,"UE (%x/%d): Format1A DCI: C-RNTI is temporary. Set NDI = %d and to be ignored\n",
		rnti,harq_pid,pdlsch0_harq->DCINdi);
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    	}

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        // NDI has been toggled or this is the first transmission
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        if ((ndi1!=pdlsch0_harq->DCINdi) || (pdlsch0_harq->first_tx==1))
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        {
            pdlsch0_harq->round    = 0;
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            pdlsch0_harq->first_tx = 0;
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            pdlsch0_harq->status   = ACTIVE;

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        }else if (rv1  != 0 )
            //NDI has not been toggled but rv was increased by eNB: retransmission
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        {
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            if (pdlsch0_harq->status == SCH_IDLE)
                //packet was actually decoded in previous transmission (ACK was missed by eNB)
                //However, the round is not a good check as it might have been decoded in a retransmission prior to this one.
            {
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	      //                LOG_D(PHY,"skip pdsch decoding and report ack\n");
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                // skip pdsch decoding and report ack
                //pdlsch0_harq->status   = SCH_IDLE;
                pdlsch0->active       = 0;
                pdlsch0->harq_ack[subframe].ack = 1;
                pdlsch0->harq_ack[subframe].harq_id = harq_pid;
                pdlsch0->harq_ack[subframe].send_harq_status = 1;

                //pdlsch0_harq->first_tx = 0;
            }
            else  //normal retransmission
            {
                // nothing special to do
            }
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        }
5204
        else
5205
        {
5206
            pdlsch0_harq->status   = ACTIVE;
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        }
    }

    pdlsch0_harq->DCINdi = ndi1;
    pdlsch0_harq->mcs    = mcs1;
    pdlsch0_harq->rvidx  = rv1;
    pdlsch0_harq->nb_rb  = NPRB;

    pdlsch0_harq->codeword     = 0;
    pdlsch0_harq->Nl           = 1;
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    pdlsch0_harq->mimo_mode    = frame_parms->nb_antenna_ports_eNB == 1 ?SISO : ALAMOUTI;
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    pdlsch0_harq->dl_power_off = 1; //no power offset
    pdlsch0_harq->delta_PUCCH  = delta_PUCCH_lut[TPC &3];

    // compute resource allocation
    if(dci_format == format1A)
    {
        switch (N_RB_DL) {
        case 6:
            if (vrb_type == LOCALIZED) {
                pdlsch0_harq->rb_alloc_even[0] = localRIV2alloc_LUT6[rballoc];
                pdlsch0_harq->rb_alloc_odd[0]  = localRIV2alloc_LUT6[rballoc];
            }
            else {
                pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_even_LUT6[rballoc];
                pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_odd_LUT6[rballoc];
            }
            break;

        case 25:
            if (vrb_type == LOCALIZED) {
                pdlsch0_harq->rb_alloc_even[0] = localRIV2alloc_LUT25[rballoc];
                pdlsch0_harq->rb_alloc_odd[0]  = localRIV2alloc_LUT25[rballoc];
            }
            else {
                pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_even_LUT25[rballoc];
                pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_odd_LUT25[rballoc];
            }
            break;

        case 50:
            if (vrb_type == LOCALIZED) {
                pdlsch0_harq->rb_alloc_even[0] = localRIV2alloc_LUT50_0[rballoc];
                pdlsch0_harq->rb_alloc_even[1] = localRIV2alloc_LUT50_1[rballoc];
                pdlsch0_harq->rb_alloc_odd[0]  = localRIV2alloc_LUT50_0[rballoc];
                pdlsch0_harq->rb_alloc_odd[1]  = localRIV2alloc_LUT50_1[rballoc];
            } else { // DISTRIBUTED
                if ((rballoc&(1<<10)) == 0) {
                    rballoc = rballoc&(~(1<<10));
                    pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_gap0_even_LUT50_0[rballoc];
                    pdlsch0_harq->rb_alloc_even[1] = distRIV2alloc_gap0_even_LUT50_1[rballoc];
                    pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_gap0_odd_LUT50_0[rballoc];
                    pdlsch0_harq->rb_alloc_odd[1]  = distRIV2alloc_gap0_odd_LUT50_1[rballoc];
                }
                else {
                    rballoc = rballoc&(~(1<<10));
                    pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_gap0_even_LUT50_0[rballoc];
                    pdlsch0_harq->rb_alloc_even[1] = distRIV2alloc_gap0_even_LUT50_1[rballoc];
                    pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_gap0_odd_LUT50_0[rballoc];
                    pdlsch0_harq->rb_alloc_odd[1]  = distRIV2alloc_gap0_odd_LUT50_1[rballoc];
                }
            }
            break;

        case 100:
            if (vrb_type == LOCALIZED) {
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                pdlsch0_harq->rb_alloc_even[0] = localRIV2alloc_LUT100_0[rballoc];
                pdlsch0_harq->rb_alloc_even[1] = localRIV2alloc_LUT100_1[rballoc];
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                pdlsch0_harq->rb_alloc_even[2] = localRIV2alloc_LUT100_2[rballoc];
                pdlsch0_harq->rb_alloc_even[3] = localRIV2alloc_LUT100_3[rballoc];
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                pdlsch0_harq->rb_alloc_odd[0]  = localRIV2alloc_LUT100_0[rballoc];
                pdlsch0_harq->rb_alloc_odd[1]  = localRIV2alloc_LUT100_1[rballoc];
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                pdlsch0_harq->rb_alloc_odd[2]  = localRIV2alloc_LUT100_2[rballoc];
                pdlsch0_harq->rb_alloc_odd[3]  = localRIV2alloc_LUT100_3[rballoc];
            } else {
                if ((rballoc&(1<<10)) == 0) { //Gap 1
                    rballoc = rballoc&(~(1<<12));
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                    pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_gap0_even_LUT100_0[rballoc];
                    pdlsch0_harq->rb_alloc_even[1] = distRIV2alloc_gap0_even_LUT100_1[rballoc];
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                    pdlsch0_harq->rb_alloc_even[2] = distRIV2alloc_gap0_even_LUT100_2[rballoc];
                    pdlsch0_harq->rb_alloc_even[3] = distRIV2alloc_gap0_even_LUT100_3[rballoc];
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                    pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_gap0_odd_LUT100_0[rballoc];
                    pdlsch0_harq->rb_alloc_odd[1]  = distRIV2alloc_gap0_odd_LUT100_1[rballoc];
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                    pdlsch0_harq->rb_alloc_odd[2]  = distRIV2alloc_gap0_odd_LUT100_2[rballoc];
                    pdlsch0_harq->rb_alloc_odd[3]  = distRIV2alloc_gap0_odd_LUT100_3[rballoc];
                }
                else { //Gap 2
                    rballoc = rballoc&(~(1<<12));
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                    pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_gap1_even_LUT100_0[rballoc];
                    pdlsch0_harq->rb_alloc_even[1] = distRIV2alloc_gap1_even_LUT100_1[rballoc];
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                    pdlsch0_harq->rb_alloc_even[2] = distRIV2alloc_gap1_even_LUT100_2[rballoc];
                    pdlsch0_harq->rb_alloc_even[3] = distRIV2alloc_gap1_even_LUT100_3[rballoc];
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                    pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_gap1_odd_LUT100_0[rballoc];
                    pdlsch0_harq->rb_alloc_odd[1]  = distRIV2alloc_gap1_odd_LUT100_1[rballoc];
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                    pdlsch0_harq->rb_alloc_odd[2]  = distRIV2alloc_gap1_odd_LUT100_2[rballoc];
                    pdlsch0_harq->rb_alloc_odd[3]  = distRIV2alloc_gap1_odd_LUT100_3[rballoc];
                }
            }
            break;
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        }
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    }
    else // format1
    {
        conv_rballoc(rah,rballoc,frame_parms->N_RB_DL,pdlsch0_harq->rb_alloc_even);
        pdlsch0_harq->rb_alloc_odd[0]= pdlsch0_harq->rb_alloc_even[0];
        pdlsch0_harq->rb_alloc_odd[1]= pdlsch0_harq->rb_alloc_even[1];
        pdlsch0_harq->rb_alloc_odd[2]= pdlsch0_harq->rb_alloc_even[2];
        pdlsch0_harq->rb_alloc_odd[3]= pdlsch0_harq->rb_alloc_even[3];
    }
    if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti))
    {
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        pdlsch0_harq->TBS = TBStable[mcs1][NPRB4TBS-1];
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        pdlsch0_harq->Qm  = 2;
    }
    else
    {
        if(mcs1 < 29)
        {
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            pdlsch0_harq->TBS = TBStable[get_I_TBS(mcs1)][NPRB4TBS-1];
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            pdlsch0_harq->Qm  = get_Qm(mcs1);
        }
    }
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    compute_llr_offset(frame_parms,
                       pdcch_vars,
                       pdsch_vars,
                       pdlsch0_harq,
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                       NPRB,
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                       subframe);
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}

void prepare_dl_decoding_format1C(uint8_t N_RB_DL,
                                  DCI_INFO_EXTRACTED_t *pdci_info_extarcted,
                                  LTE_DL_FRAME_PARMS *frame_parms,
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                                  LTE_UE_PDCCH *pdcch_vars,
                                  LTE_UE_PDSCH *pdsch_vars,
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                                  uint32_t rnti,
                                  uint32_t si_rnti,
                                  uint32_t ra_rnti,
                                  uint32_t p_rnti,
                                  uint32_t frame,
                                  uint8_t  subframe,
                                  LTE_DL_UE_HARQ_t *pdlsch0_harq,
                                  LTE_UE_DLSCH_t *pdlsch0)
{

    uint8_t  harq_pid  = pdci_info_extarcted->harq_pid;
    uint32_t rballoc   = pdci_info_extarcted->rballoc;
    uint8_t  mcs1      = pdci_info_extarcted->mcs1;
    uint8_t  Ngap      = pdci_info_extarcted->Ngap;

      pdlsch0_harq->round     = 0;
      pdlsch0_harq->first_tx  = 1;
      pdlsch0_harq->vrb_type  = DISTRIBUTED;

      if (rnti==si_rnti) { // rule from Section 5.3.1 of 36.321
        if (((frame&1) == 0) && (subframe == 5))
           pdlsch0_harq->rvidx = (((3*((frame>>1)&3))+1)>>1)&3;  // SIB1
        else
           pdlsch0_harq->rvidx = (((3*(subframe&3))+1)>>1)&3;  // other SIBs
      }
      else if ((rnti==p_rnti) || (rnti==ra_rnti)) { // Section 7.1.7.3
        pdlsch0_harq->rvidx = 0;
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      }
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      pdlsch0_harq->Nl           = 1;
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      pdlsch0_harq->mimo_mode    = frame_parms->nb_antenna_ports_eNB == 1 ?SISO : ALAMOUTI;
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      pdlsch0_harq->dl_power_off = 1; //no power offset
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      pdlsch0_harq->codeword = 0;
      pdlsch0_harq->mcs      = mcs1;
      pdlsch0_harq->TBS      = TBStable1C[mcs1];
      pdlsch0_harq->Qm       = 2;
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      pdlsch0->current_harq_pid = harq_pid;
      pdlsch0->active = 1;
      pdlsch0->rnti   = rnti;
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    switch (N_RB_DL) {
    case 6:
        pdlsch0_harq->nb_rb            = RIV2nb_rb_LUT6[rballoc];
        pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_even_LUT6[rballoc];
        pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_odd_LUT6[rballoc];
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        break;
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    case 25:
        pdlsch0_harq->nb_rb            = RIV2nb_rb_LUT25[rballoc];
        pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_even_LUT25[rballoc];
        pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_odd_LUT25[rballoc];
        break;
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    case 50:
        pdlsch0_harq->nb_rb            = RIV2nb_rb_LUT50[rballoc];
        if (Ngap == 0) {
            pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_gap0_even_LUT50_0[rballoc];
            pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_gap0_odd_LUT50_0[rballoc];
            pdlsch0_harq->rb_alloc_even[1] = distRIV2alloc_gap0_even_LUT50_1[rballoc];
            pdlsch0_harq->rb_alloc_odd[1]  = distRIV2alloc_gap0_odd_LUT50_1[rballoc];
        }
        else {
            pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_gap1_even_LUT50_0[rballoc];
            pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_gap1_odd_LUT50_0[rballoc];
            pdlsch0_harq->rb_alloc_even[1] = distRIV2alloc_gap1_even_LUT50_1[rballoc];
            pdlsch0_harq->rb_alloc_odd[1]  = distRIV2alloc_gap1_odd_LUT50_1[rballoc];
        }
        break;
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    case 100:
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        pdlsch0_harq->nb_rb       = RIV2nb_rb_LUT100[rballoc];
        if (Ngap==0) {
            pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_gap0_even_LUT100_0[rballoc];
            pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_gap0_odd_LUT100_0[rballoc];
            pdlsch0_harq->rb_alloc_even[1] = distRIV2alloc_gap0_even_LUT100_1[rballoc];
            pdlsch0_harq->rb_alloc_odd[1]  = distRIV2alloc_gap0_odd_LUT100_1[rballoc];
            pdlsch0_harq->rb_alloc_even[2] = distRIV2alloc_gap0_even_LUT100_2[rballoc];
            pdlsch0_harq->rb_alloc_odd[2]  = distRIV2alloc_gap0_odd_LUT100_2[rballoc];
            pdlsch0_harq->rb_alloc_even[3] = distRIV2alloc_gap0_even_LUT100_3[rballoc];
            pdlsch0_harq->rb_alloc_odd[3]  = distRIV2alloc_gap0_odd_LUT100_3[rballoc];
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        }
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        else {
            pdlsch0_harq->rb_alloc_even[0] = distRIV2alloc_gap1_even_LUT100_0[rballoc];
            pdlsch0_harq->rb_alloc_odd[0]  = distRIV2alloc_gap1_odd_LUT100_0[rballoc];
            pdlsch0_harq->rb_alloc_even[1] = distRIV2alloc_gap1_even_LUT100_1[rballoc];
            pdlsch0_harq->rb_alloc_odd[1]  = distRIV2alloc_gap1_odd_LUT100_1[rballoc];
            pdlsch0_harq->rb_alloc_even[2] = distRIV2alloc_gap1_even_LUT100_2[rballoc];
            pdlsch0_harq->rb_alloc_odd[2]  = distRIV2alloc_gap1_odd_LUT100_2[rballoc];
            pdlsch0_harq->rb_alloc_even[3] = distRIV2alloc_gap1_even_LUT100_3[rballoc];
            pdlsch0_harq->rb_alloc_odd[3]  = distRIV2alloc_gap1_odd_LUT100_3[rballoc];
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        }
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        break;
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    default:
        AssertFatal(0,"Format 1C: Unknown N_RB_DL %d\n",frame_parms->N_RB_DL);
        break;
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    }
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    compute_llr_offset(frame_parms,
                       pdcch_vars,
                       pdsch_vars,
                       pdlsch0_harq,
                       pdlsch0_harq->nb_rb,
                       subframe);

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}
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void compute_precoding_info_2cw(uint8_t tpmi, uint8_t tbswap, uint16_t pmi_alloc, LTE_DL_FRAME_PARMS *frame_parms, LTE_DL_UE_HARQ_t *dlsch0_harq, LTE_DL_UE_HARQ_t *dlsch1_harq)
{
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switch (tpmi) {
          case 0:
            dlsch0_harq->mimo_mode   = DUALSTREAM_UNIFORM_PRECODING1;
            dlsch1_harq->mimo_mode   = DUALSTREAM_UNIFORM_PRECODING1;
            dlsch0_harq->pmi_alloc   = pmi_extend(frame_parms,0, 1);
            dlsch1_harq->pmi_alloc   = pmi_extend(frame_parms,0, 1);
          break;
          case 1:
            dlsch0_harq->mimo_mode   = DUALSTREAM_UNIFORM_PRECODINGj;
            dlsch1_harq->mimo_mode   = DUALSTREAM_UNIFORM_PRECODINGj;
            dlsch0_harq->pmi_alloc   = pmi_extend(frame_parms,1, 1);
            dlsch1_harq->pmi_alloc   = pmi_extend(frame_parms,1, 1);
          break;
          case 2: // PUSCH precoding
            dlsch0_harq->mimo_mode   = DUALSTREAM_PUSCH_PRECODING;
            dlsch1_harq->mimo_mode   = DUALSTREAM_PUSCH_PRECODING;
            if (tbswap==0){
              dlsch0_harq->pmi_alloc   = pmi_alloc;
              dlsch1_harq->pmi_alloc   = pmi_alloc^0x1555;
            } else {
                dlsch1_harq->pmi_alloc   = pmi_alloc;
                dlsch0_harq->pmi_alloc   = pmi_alloc^0x1555;
            }
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#ifdef DEBUG_HARQ
              printf ("\n \n compute_precoding_info_2cw pmi_alloc_new = %d\n", dlsch0_harq->pmi_alloc);
  #endif
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          break;
          default:
          break;
        }
}
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void compute_precoding_info_1cw(uint8_t tpmi, uint16_t pmi_alloc, LTE_DL_FRAME_PARMS *frame_parms, LTE_DL_UE_HARQ_t *dlsch_harq)
{
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switch (tpmi) {
            case 0 :
              dlsch_harq->mimo_mode   = ALAMOUTI;
            break;
            case 1:
              dlsch_harq->mimo_mode   = UNIFORM_PRECODING11;
              dlsch_harq->pmi_alloc   = pmi_extend(frame_parms,0, 0);
            break;
            case 2:
              dlsch_harq->mimo_mode   = UNIFORM_PRECODING1m1;
              dlsch_harq->pmi_alloc   = pmi_extend(frame_parms,1, 0);
            break;
            case 3:
              dlsch_harq->mimo_mode   = UNIFORM_PRECODING1j;
              dlsch_harq->pmi_alloc   = pmi_extend(frame_parms,2, 0);
            break;
            case 4:
              dlsch_harq->mimo_mode   = UNIFORM_PRECODING1mj;
              dlsch_harq->pmi_alloc   = pmi_extend(frame_parms,3, 0);
            break;
            case 5:
              dlsch_harq->mimo_mode   = PUSCH_PRECODING0;
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              dlsch_harq->pmi_alloc   = pmi_alloc;//pmi_convert(frame_parms,dlsch0->pmi_alloc,0);
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            break;
            case 6:
              dlsch_harq->mimo_mode   = PUSCH_PRECODING1;
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              dlsch_harq->pmi_alloc   = pmi_alloc;//pmi_convert(frame_parms,dlsch0->pmi_alloc,1);
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            break;
            }
  #ifdef DEBUG_HARQ
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              printf ("[DCI UE] I am calling from the UE side pmi_alloc_new = %d with tpmi %d\n", dlsch_harq->pmi_alloc, tpmi);
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  #endif
            }
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void compute_precoding_info_format2A(uint8_t tpmi,
                                     uint8_t nb_antenna_ports_eNB,
                                     uint8_t tb0_active,
                                     uint8_t tb1_active,
                                     LTE_DL_UE_HARQ_t *dlsch0_harq,
                                     LTE_DL_UE_HARQ_t *dlsch1_harq)
{
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    dlsch0_harq->dl_power_off = 0;
    dlsch1_harq->dl_power_off = 0;
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    if (nb_antenna_ports_eNB == 2) {
        if ((tb0_active==1) && (tb1_active==1)) {
          dlsch0_harq->mimo_mode = LARGE_CDD;
          dlsch1_harq->mimo_mode = LARGE_CDD;
          dlsch0_harq->dl_power_off = 1;
          dlsch1_harq->dl_power_off = 1;
        } else {
          dlsch0_harq->mimo_mode   = ALAMOUTI;
          dlsch1_harq->mimo_mode   = ALAMOUTI;
        }
      } else if (nb_antenna_ports_eNB == 4) { // 4 antenna case
        if ((tb0_active==1) && (tb1_active==1)) {
          switch (tpmi) {
          case 0: // one layer per transport block
            dlsch0_harq->mimo_mode   = LARGE_CDD;
            dlsch1_harq->mimo_mode   = LARGE_CDD;
            dlsch0_harq->dl_power_off = 1;
            dlsch1_harq->dl_power_off = 1;
            break;
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          case 1: // one-layers on TB 0, two on TB 1
            dlsch0_harq->mimo_mode   = LARGE_CDD;
            dlsch1_harq->mimo_mode   = LARGE_CDD;
            dlsch1_harq->Nl          = 2;
            dlsch0_harq->dl_power_off = 1;
            dlsch1_harq->dl_power_off = 1;
            break;
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          case 2: // two-layers on TB 0, two on TB 1
            dlsch0_harq->mimo_mode   = LARGE_CDD;
            dlsch1_harq->mimo_mode   = LARGE_CDD;
            dlsch0_harq->Nl          = 2;
            dlsch0_harq->dl_power_off = 1;
            dlsch1_harq->dl_power_off = 1;
            break;
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          case 3: //
            LOG_E(PHY,"Illegal value (3) for TPMI in Format 2A DCI\n");
            break;
          }
        } else if (tb0_active == 1) {
          switch (tpmi) {
          case 0: // one layer per transport block
            dlsch0_harq->mimo_mode   = ALAMOUTI;
            dlsch1_harq->mimo_mode   = ALAMOUTI;
            break;
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          case 1: // two-layers on TB 0
            dlsch0_harq->mimo_mode   = LARGE_CDD;
            dlsch0_harq->Nl          = 2;
            dlsch0_harq->dl_power_off = 1;
            break;
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          case 2: // two-layers on TB 0, two on TB 1
          case 3: //
            LOG_E(PHY,"Illegal value %d for TPMI in Format 2A DCI with one transport block enabled\n",tpmi);
            break;
          }
        } else if (tb1_active == 1) {
          switch (tpmi) {
          case 0: // one layer per transport block
            dlsch0_harq->mimo_mode   = ALAMOUTI;
            dlsch1_harq->mimo_mode   = ALAMOUTI;
            break;
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          case 1: // two-layers on TB 0
            dlsch1_harq->mimo_mode   = LARGE_CDD;
            dlsch1_harq->Nl          = 2;
            dlsch0_harq->dl_power_off = 1;
            break;
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          case 2: // two-layers on TB 0, two on TB 1
          case 3: //
            LOG_E(PHY,"Illegal value %d for TPMI in Format 2A DCI with one transport block enabled\n",tpmi);
            break;
          }
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        }
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      }
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      //    printf("Format 2A: NPRB=%d (rballoc %x,mcs1 %d, mcs2 %d, frame_type %d N_RB_DL %d,active %d/%d)\n",NPRB,rballoc,mcs1,mcs2,frame_parms->frame_type,frame_parms->N_RB_DL,dlsch0->active,dlsch1->active);
      //printf("UE (%x/%d): Subframe %d Format2A DCI: ndi1 %d, old_ndi1 %d, ndi2 %d, old_ndi2 %d (first tx1 %d, first tx2 %d) harq_status1 %d, harq_status2 %d\n",dlsch0->rnti,harq_pid,subframe,ndi,dlsch0_harq->DCINdi,
      //    dlsch0_harq->first_tx,dlsch1_harq->first_tx,dlsch0_harq->status,dlsch1_harq->status);
      //printf("TBS0 %d, TBS1 %d\n",dlsch0_harq->TBS,dlsch1_harq->TBS);
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}
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void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
                                    DCI_INFO_EXTRACTED_t *pdci_info_extarcted,
                                    LTE_DL_FRAME_PARMS *frame_parms,
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                                    LTE_UE_PDCCH *pdcch_vars,
                                    LTE_UE_PDSCH *pdsch_vars,
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hbilel committed
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                                    uint16_t rnti,
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                                    uint8_t subframe,
                                    LTE_DL_UE_HARQ_t *dlsch0_harq,
                                    LTE_DL_UE_HARQ_t *dlsch1_harq,
                                    LTE_UE_DLSCH_t *pdlsch0,
                                    LTE_UE_DLSCH_t *pdlsch1)
{
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    uint8_t  rah  = pdci_info_extarcted->rah;
    uint8_t  mcs1 = pdci_info_extarcted->mcs1;
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    uint8_t  mcs2 = pdci_info_extarcted->mcs2;
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    uint8_t  rv1  = pdci_info_extarcted->rv1;
    uint8_t  rv2  = pdci_info_extarcted->rv2;
    uint8_t  harq_pid = pdci_info_extarcted->harq_pid;
    uint32_t rballoc  = pdci_info_extarcted->rballoc;
    uint8_t  tbswap   = pdci_info_extarcted->tb_swap;
    uint8_t  tpmi     = pdci_info_extarcted->tpmi;
    uint8_t  TPC      = pdci_info_extarcted->TPC;
    uint8_t  ndi1     = pdci_info_extarcted->ndi1;
    uint8_t  ndi2     = pdci_info_extarcted->ndi2;
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    uint8_t TB0_active = 1;
    uint8_t TB1_active = 1;
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5651

5652
   // printf("inside prepare pdlsch1->pmi_alloc %d \n",pdlsch1->pmi_alloc);
5653

5654

5655 5656 5657 5658 5659
      if ((rv1 == 1) && (mcs1 == 0)) {
        TB0_active=0;
      }
      if ((rv2 == 1) && (mcs2 == 0)) {
        TB1_active=0;
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      }

5662
#ifdef DEBUG_HARQ
5663
      printf("[DCI UE]: TB0 status %d , TB1 status %d\n", TB0_active, TB1_active);
5664
#endif
5665

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        dlsch0_harq->mcs      = mcs1;
        dlsch1_harq->mcs      = mcs2;
        dlsch0_harq->rvidx    = rv1;
        dlsch1_harq->rvidx    = rv2;
        dlsch0_harq->DCINdi   = ndi1;
        dlsch1_harq->DCINdi   = ndi2;

        dlsch0_harq->codeword = 0;
        dlsch1_harq->codeword = 1;
        dlsch0_harq->Nl       = 1;
        dlsch1_harq->Nl       = 1;
        dlsch0_harq->delta_PUCCH  = delta_PUCCH_lut[TPC&3];
        dlsch1_harq->delta_PUCCH  = delta_PUCCH_lut[TPC&3];
        dlsch0_harq->dl_power_off = 1;
        dlsch1_harq->dl_power_off = 1;
5681

5682
        pdlsch0->current_harq_pid = harq_pid;
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5683
        pdlsch0->harq_ack[subframe].harq_id     = harq_pid;
5684
        pdlsch1->current_harq_pid = harq_pid;
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5685
        pdlsch1->harq_ack[subframe].harq_id     = harq_pid;
5686 5687 5688 5689 5690 5691

        // assume two CW are active
        dlsch0_harq->status   = ACTIVE;
        dlsch1_harq->status   = ACTIVE;
        pdlsch0->active = 1;
        pdlsch1->active = 1;
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5692 5693
        pdlsch0->rnti = rnti;
        pdlsch1->rnti = rnti;
5694

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5695

5696 5697 5698
      if (TB0_active && TB1_active && tbswap==1) {
        dlsch0_harq->codeword = 1;
        dlsch1_harq->codeword = 0;
5699
      }
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5701 5702 5703 5704 5705 5706 5707 5708 5709 5710

      if (!TB0_active && TB1_active){
        dlsch1_harq->codeword = 0;
      }

      if (TB0_active && !TB1_active){
        dlsch0_harq->codeword = 0;
      }


5711 5712 5713
      if (TB0_active==0) {
        dlsch0_harq->status = SCH_IDLE;
        pdlsch0->active     = 0;
5714
  #ifdef DEBUG_HARQ
5715
        printf("[DCI UE]: TB0 is deactivated, retransmit TB1 transmit in TM6\n");
5716
  #endif
5717
      }
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5719 5720 5721 5722
      if (TB1_active==0) {
        dlsch1_harq->status = SCH_IDLE;
        pdlsch1->active     = 0;
      }
5723

5724
#ifdef DEBUG_HARQ
5725
      printf("[DCI UE]: dlsch0_harq status %d , dlsch1_harq status %d\n", dlsch0_harq->status, dlsch1_harq->status);
5726
#endif
5727

5728 5729
      // compute resource allocation
      if (TB0_active == 1){
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5731 5732 5733 5734 5735 5736 5737
        dlsch0_harq->nb_rb = conv_nprb(rah,
                                       rballoc,
                                       frame_parms->N_RB_DL);
        conv_rballoc(rah,
                     rballoc,
                     frame_parms->N_RB_DL,
                     dlsch0_harq->rb_alloc_even);
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5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754
        dlsch0_harq->rb_alloc_odd[0]= dlsch0_harq->rb_alloc_even[0];
        dlsch0_harq->rb_alloc_odd[1]= dlsch0_harq->rb_alloc_even[1];
        dlsch0_harq->rb_alloc_odd[2]= dlsch0_harq->rb_alloc_even[2];
        dlsch0_harq->rb_alloc_odd[3]= dlsch0_harq->rb_alloc_even[3];

        if (TB1_active == 1){
          dlsch1_harq->rb_alloc_even[0]= dlsch0_harq->rb_alloc_even[0];
          dlsch1_harq->rb_alloc_even[1]= dlsch0_harq->rb_alloc_even[1];
          dlsch1_harq->rb_alloc_even[2]= dlsch0_harq->rb_alloc_even[2];
          dlsch1_harq->rb_alloc_even[3]= dlsch0_harq->rb_alloc_even[3];
          dlsch1_harq->rb_alloc_odd[0] = dlsch0_harq->rb_alloc_odd[0];
          dlsch1_harq->rb_alloc_odd[1] = dlsch0_harq->rb_alloc_odd[1];
          dlsch1_harq->rb_alloc_odd[2] = dlsch0_harq->rb_alloc_odd[2];
          dlsch1_harq->rb_alloc_odd[3] = dlsch0_harq->rb_alloc_odd[3];

          dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
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5755 5756 5757

          //dlsch0_harq->Nl       = 1;
          //dlsch1_harq->Nl       = 1;
5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772
        }
      } else if ((TB0_active == 0) && (TB1_active == 1)){

          conv_rballoc(rah,
                       rballoc,
                       frame_parms->N_RB_DL,
                       dlsch1_harq->rb_alloc_even);

          dlsch1_harq->rb_alloc_odd[0]= dlsch1_harq->rb_alloc_even[0];
          dlsch1_harq->rb_alloc_odd[1]= dlsch1_harq->rb_alloc_even[1];
          dlsch1_harq->rb_alloc_odd[2]= dlsch1_harq->rb_alloc_even[2];
          dlsch1_harq->rb_alloc_odd[3]= dlsch1_harq->rb_alloc_even[3];
          dlsch1_harq->nb_rb = conv_nprb(rah,
                                         rballoc,
                                         frame_parms->N_RB_DL);
5773 5774 5775
        }


5776 5777 5778 5779 5780
      // compute precoding matrix + mimo mode
      if(dci_format == format2)
      {
      if ((TB0_active) && (TB1_active)){  //two CW active
        compute_precoding_info_2cw(tpmi, tbswap, pdlsch0->pmi_alloc,frame_parms, dlsch0_harq, dlsch1_harq);
5781 5782

   //   printf("[DCI UE 1]: dlsch0_harq status %d , dlsch1_harq status %d\n", dlsch0_harq->status, dlsch1_harq->status);
5783 5784 5785
      } else if ((TB0_active) && (!TB1_active))  { // only CW 0 active
        compute_precoding_info_1cw(tpmi, pdlsch0->pmi_alloc, frame_parms, dlsch0_harq);
      } else {
5786
        compute_precoding_info_1cw(tpmi, pdlsch1->pmi_alloc, frame_parms, dlsch1_harq);
5787
       // printf("I am doing compute_precoding_info_1cw with tpmi %d \n", tpmi);
5788 5789
      }
      //printf(" UE DCI harq0 MIMO mode = %d\n", dlsch0_harq->mimo_mode);
5790
      if ((frame_parms->nb_antenna_ports_eNB == 1) && (TB0_active))
5791 5792 5793 5794 5795 5796 5797 5798 5799 5800
        dlsch0_harq->mimo_mode   = SISO;
      }
      else
      {
        compute_precoding_info_format2A( tpmi,
                                      frame_parms->nb_antenna_ports_eNB,
                                      TB0_active,
                                      TB1_active,
                                      dlsch0_harq,
                                      dlsch1_harq);
5801
      }
5802
  //    printf("[DCI UE 2]: dlsch0_harq status %d , dlsch1_harq status %d\n", dlsch0_harq->status, dlsch1_harq->status);
5803 5804
      // reset round + compute Qm
      if (TB0_active) {
5805
       // printf("TB0 ndi1 =%d, dlsch0_harq->DCINdi =%d, dlsch0_harq->first_tx = %d\n", ndi1, dlsch0_harq->DCINdi, dlsch0_harq->first_tx);
5806 5807
        if ((ndi1!=dlsch0_harq->DCINdi) || (dlsch0_harq->first_tx==1))  {
          dlsch0_harq->round = 0;
5808 5809
           dlsch0_harq->status = ACTIVE;
           dlsch0_harq->DCINdi = ndi1;
5810

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5811 5812
          //LOG_I(PHY,"[UE] DLSCH: New Data Indicator CW0 subframe %d (pid %d, round %d)\n",
          //           subframe,harq_pid,dlsch0_harq->round);
5813
          if ( dlsch0_harq->first_tx==1) {
5814
	    //            LOG_D(PHY,"Format 2 DCI First TX0: Clearing flag\n");
5815 5816
            dlsch0_harq->first_tx = 0;
          }
5817
        }
5818
	/*else if (rv1  != 0 )
5819 5820
	  //NDI has not been toggled but rv was increased by eNB: retransmission
	  {
5821
	    if(dlsch0_harq->status == SCH_IDLE) {
5822
            // skip pdsch decoding and report ack
5823
	      //dlsch0_harq->status   = SCH_IDLE;
5824 5825 5826 5827
            pdlsch0->active       = 0;
            pdlsch0->harq_ack[subframe].ack = 1;
            pdlsch0->harq_ack[subframe].harq_id = harq_pid;
            pdlsch0->harq_ack[subframe].send_harq_status = 1;
5828
	    }*/
5829

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        // if Imcs in [29..31] TBS is assumed to be as determined from DCI transported in the latest
        // PDCCH for the same trasport block using Imcs in [0 .. 28]
        if(dlsch0_harq->mcs <= 28)
        {
            dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
            LOG_D(PHY,"[UE] DLSCH: New TBS CW0 subframe %d (pid %d, round %d) TBS %d \n",
                       subframe,harq_pid,dlsch0_harq->round, dlsch0_harq->TBS);
        }
        else
        {
            LOG_D(PHY,"[UE] DLSCH: Keep the same TBS CW0 subframe %d (pid %d, round %d) TBS %d \n",
                       subframe,harq_pid,dlsch0_harq->round, dlsch0_harq->TBS);
        }
        //if(dlsch0_harq->Nl == 2)
        //dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][(dlsch0_harq->nb_rb<<1)-1];
        if (mcs1 <= 28)
5846
            dlsch0_harq->Qm = get_Qm(mcs1);
5847
        else if (mcs1<=31)
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            dlsch0_harq->Qm = (mcs1-28)<<1;
      }
5850

5851
   //   printf("[DCI UE 3]: dlsch0_harq status %d , dlsch1_harq status %d\n", dlsch0_harq->status, dlsch1_harq->status);
5852

5853
      if (TB1_active) {
5854
       // printf("TB1 ndi2 =%d, dlsch1_harq->DCINdi =%d, dlsch1_harq->first_tx = %d\n", ndi2, dlsch1_harq->DCINdi, dlsch1_harq->first_tx);
5855 5856
        if ((ndi2!=dlsch1_harq->DCINdi) || (dlsch1_harq->first_tx==1)) {
          dlsch1_harq->round = 0;
5857 5858
          dlsch1_harq->status = ACTIVE;
          dlsch1_harq->DCINdi = ndi2;
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5859 5860
          //LOG_I(PHY,"[UE] DLSCH: New Data Indicator CW1 subframe %d (pid %d, round %d)\n",
          //           subframe,harq_pid,dlsch0_harq->round);
5861
          if (dlsch1_harq->first_tx==1) {
5862
	    //            LOG_D(PHY,"Format 2 DCI First TX1: Clearing flag\n");
5863 5864 5865
            dlsch1_harq->first_tx = 0;
          }
        }
5866
	/*else if (rv1  != 0 )
5867 5868
	//NDI has not been toggled but rv was increased by eNB: retransmission
	  {
5869
	    if(dlsch1_harq->status == SCH_IDLE) {
5870
            // skip pdsch decoding and report ack
5871
	      //dlsch1_harq->status   = SCH_IDLE;
5872 5873 5874 5875 5876
            pdlsch1->active       = 0;
            pdlsch1->harq_ack[subframe].ack = 1;
            pdlsch1->harq_ack[subframe].harq_id = harq_pid;
            pdlsch1->harq_ack[subframe].send_harq_status = 1;
         }
5877
	  }*/
5878

5879 5880 5881 5882 5883 5884 5885
        // if Imcs in [29..31] TBS is assumed to be as determined from DCI transported in the latest
        // PDCCH for the same trasport block using Imcs in [0 .. 28]
        if(dlsch1_harq->mcs <= 28)
        {
            dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
            LOG_D(PHY,"[UE] DLSCH: New TBS CW1 subframe %d (pid %d, round %d) TBS %d \n",
                       subframe,harq_pid,dlsch1_harq->round, dlsch1_harq->TBS);
5886
        }
5887 5888 5889 5890 5891 5892
        else
        {
            LOG_D(PHY,"[UE] DLSCH: Keep the same TBS CW1 subframe %d (pid %d, round %d) TBS %d \n",
                       subframe,harq_pid,dlsch1_harq->round, dlsch1_harq->TBS);
        }
        if (mcs2 <= 28)
5893
            dlsch1_harq->Qm = get_Qm(mcs2);
5894
        else if (mcs1<=31)
5895
            dlsch1_harq->Qm = (mcs2-28)<<1;
5896
      }
5897

5898

5899 5900 5901 5902 5903 5904
      compute_llr_offset(frame_parms,
                         pdcch_vars,
                         pdsch_vars,
                         dlsch0_harq,
                         dlsch0_harq->nb_rb,
                         subframe);
5905

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5906

5907
 /* #ifdef DEBUG_HARQ
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5908
      printf("[DCI UE]: dlsch0_harq status %d , dlsch1_harq status %d\n", dlsch0_harq->status, dlsch1_harq->status);
5909
      printf("[DCI UE]: TB0_active %d , TB1_active %d\n", TB0_active, TB1_active);
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      if (dlsch0 != NULL && dlsch1 != NULL)
        printf("[DCI UE] dlsch0_harq status = %d, dlsch1_harq status = %d\n", dlsch0_harq->status, dlsch1_harq->status);
      else if (dlsch0 == NULL && dlsch1 != NULL)
        printf("[DCI UE] dlsch0_harq NULL dlsch1_harq status = %d\n", dlsch1_harq->status);
      else if (dlsch0 != NULL && dlsch1 == NULL)
        printf("[DCI UE] dlsch1_harq NULL dlsch0_harq status = %d\n", dlsch0_harq->status);
5916
  #endif*/
5917 5918 5919 5920 5921 5922 5923
}

int generate_ue_dlsch_params_from_dci(int frame,
                                      uint8_t subframe,
                                      void *dci_pdu,
                                      uint16_t rnti,
                                      DCI_format_t dci_format,
5924 5925
                                      LTE_UE_PDCCH *pdcch_vars,
                                      LTE_UE_PDSCH *pdsch_vars,
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                                      LTE_UE_DLSCH_t **dlsch,
                                      LTE_DL_FRAME_PARMS *frame_parms,
                                      PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
                                      uint16_t si_rnti,
                                      uint16_t ra_rnti,
                                      uint16_t p_rnti,
                                      uint8_t beamforming_mode,
                                      uint16_t tc_rnti)
{

    uint8_t harq_pid=0;
    uint8_t frame_type=frame_parms->frame_type;
    uint8_t tpmi=0;
    LTE_UE_DLSCH_t *dlsch0=NULL,*dlsch1=NULL;
    LTE_DL_UE_HARQ_t *dlsch0_harq=NULL,*dlsch1_harq=NULL;
5941

5942 5943
    DCI_INFO_EXTRACTED_t dci_info_extarcted;
    uint8_t status=0;
5944

5945
    if (!dlsch[0]) return -1;
5946

5947 5948 5949 5950 5951 5952 5953 5954 5955 5956 5957 5958 5959 5960 5961 5962 5963 5964 5965 5966 5967 5968 5969 5970 5971 5972 5973 5974
  #ifdef DEBUG_DCI
    LOG_D(PHY,"dci_tools.c: Filling ue dlsch params -> rnti %x, SFN/SF %d/%d, dci_format %s\n",
        rnti,
        frame%1024,
        subframe,
        (dci_format==format0?  "Format 0":(
         dci_format==format1?  "format 1":(
         dci_format==format1A? "format 1A":(
         dci_format==format1B? "format 1B":(
         dci_format==format1C? "format 1C":(
         dci_format==format1D? "format 1D":(
         dci_format==format1E_2A_M10PRB? "format 1E_2A_M10PRB":(
         dci_format==format2?  "format 2":(
         dci_format==format2A? "format 2A":(
         dci_format==format2B? "format 2B":(
         dci_format==format2C? "format 2C":(
         dci_format==format2D? "format 2D":(
         dci_format==format3?  "format 3": "UNKNOWN"
         ))))))))))))));
  #endif

    memset(&dci_info_extarcted,0,sizeof(dci_info_extarcted));
    switch (dci_format) {

    case format0:   // This is an ULSCH allocation so nothing here, inform MAC
      LOG_E(PHY,"format0 not possible\n");
      return(-1);
      break;
5975

5976 5977 5978
    case format1A:
    {
      // extract dci infomation
5979 5980 5981
#ifdef DEBUG_DCI
      LOG_I(PHY,"[DCI-FORMAT-1A] AbsSubframe %d.%d extarct dci info \n", frame, subframe);
#endif
5982 5983 5984 5985
      extract_dci1A_info(frame_parms->N_RB_DL,
                         frame_type,
                         dci_pdu,
                         &dci_info_extarcted);
5986 5987


5988 5989 5990 5991
      // check dci content
      dlsch0 = dlsch[0];
      dlsch0->active = 0;
      dlsch0_harq   = dlsch[0]->harq_processes[dci_info_extarcted.harq_pid];
5992 5993 5994
#ifdef DEBUG_DCI
      LOG_I(PHY,"[DCI-FORMAT-1A] AbsSubframe %d.%d check dci coherency \n", frame, subframe);
#endif
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      status = check_dci_format1_1a_coherency(format1A,
                                              frame_parms->N_RB_DL,
                                              rnti,
                                              tc_rnti,
                                              si_rnti,
                                              ra_rnti,
6001
                                              p_rnti,frame,subframe,
6002 6003 6004
                                              &dci_info_extarcted,
                                              dlsch0_harq);
      if(status == 0)
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6005 6006
      {
        printf("bad DCI 1A !!! \n");
6007
        return(-1);
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6008
      }
6009

6010
      // dci is correct ==> update internal structure and prepare dl decoding
6011 6012 6013
#ifdef DEBUG_DCI
      LOG_I(PHY,"[DCI-FORMAT-1A] AbsSubframe %d.%d prepare dl decoding \n", frame, subframe);
#endif
6014 6015 6016 6017
      prepare_dl_decoding_format1_1A(format1A,
                                     frame_parms->N_RB_DL,
                                     &dci_info_extarcted,
                                     frame_parms,
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                                     pdcch_vars,
                                     pdsch_vars,
6020 6021
                                     subframe,
                                     rnti,
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6022
									 tc_rnti,
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                                     si_rnti,
                                     ra_rnti,
                                     p_rnti,
                                     dlsch0_harq,
                                     dlsch0);
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6030 6031

      break;
6032
    }
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    case format1C:
    {
      // extract dci infomation
#ifdef DEBUG_DL_DECODING
      LOG_I(PHY,"[DCI Format-1C] extact dci information \n");
#endif
      extract_dci1C_info(frame_parms->N_RB_DL,
                         frame_type,
                         dci_pdu,
                         &dci_info_extarcted);
6043

6044

6045 6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061
      // check dci content
#ifdef DEBUG_DL_DECODING
      LOG_I(PHY,"[DCI Format-1C] check dci content \n");
#endif
      dlsch0 = dlsch[0];
      dlsch0->active = 0;
      dlsch0_harq = dlsch[0]->harq_processes[dci_info_extarcted.harq_pid];

      status = check_dci_format1c_coherency(frame_parms->N_RB_DL,
                                            &dci_info_extarcted,
                                            rnti,
                                            si_rnti,
                                            ra_rnti,
                                            p_rnti,
                                            dlsch0_harq);
      if(status == 0)
        return(-1);
6062

6063 6064 6065 6066 6067 6068 6069
      // dci is correct ==> update internal structure and prepare dl decoding
#ifdef DEBUG_DL_DECODING
      LOG_I(PHY,"[DCI Format-1C] prepare downlink decoding \n");
#endif
      prepare_dl_decoding_format1C(frame_parms->N_RB_DL,
                                   &dci_info_extarcted,
                                   frame_parms,
6070 6071
                                   pdcch_vars,
                                   pdsch_vars,
6072 6073 6074 6075 6076 6077 6078 6079
                                   rnti,
                                   si_rnti,
                                   ra_rnti,
                                   p_rnti,
                                   frame,
                                   subframe,
                                   dlsch0_harq,
                                   dlsch0);
6080

6081 6082
      break;
    }
6083

6084 6085 6086
    case format1:
    {
      // extract dci infomation
6087 6088 6089
#ifdef DEBUG_DCI
      LOG_I(PHY,"[DCI-FORMAT-1] AbsSubframe %d.%d extarct dci info \n", frame, subframe);
#endif
6090 6091 6092 6093
      extract_dci1_info(frame_parms->N_RB_DL,
                         frame_type,
                         dci_pdu,
                         &dci_info_extarcted);
6094

6095 6096 6097 6098
      // check dci content
      dlsch0 = dlsch[0];
      dlsch0->active = 0;
      dlsch0_harq = dlsch[0]->harq_processes[dci_info_extarcted.harq_pid];
6099

6100 6101 6102
#ifdef DEBUG_DCI
      LOG_I(PHY,"[DCI-FORMAT-1] AbsSubframe %d.%d check dci coherency \n", frame, subframe);
#endif
6103 6104 6105 6106 6107 6108
      status = check_dci_format1_1a_coherency(format1,
                                              frame_parms->N_RB_DL,
                                              rnti,
                                              tc_rnti,
                                              si_rnti,
                                              ra_rnti,
6109
                                              p_rnti,frame,subframe,
6110 6111 6112
                                              &dci_info_extarcted,
                                              dlsch0_harq);
      if(status == 0)
tct-labo4's avatar
tct-labo4 committed
6113 6114 6115 6116 6117
      {
          printf("bad DCI 1 !!! \n");
          return(-1);
      }

6118

6119
      // dci is correct ==> update internal structure and prepare dl decoding
6120 6121 6122
#ifdef DEBUG_DCI
      LOG_I(PHY,"[DCI-FORMAT-1] AbsSubframe %d.%d prepare dl decoding \n", frame, subframe);
#endif
6123 6124 6125 6126
      prepare_dl_decoding_format1_1A(format1,
                                     frame_parms->N_RB_DL,
                                     &dci_info_extarcted,
                                     frame_parms,
6127 6128
                                     pdcch_vars,
                                     pdsch_vars,
6129 6130
                                     subframe,
                                     rnti,
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fnabet committed
6131
									 tc_rnti,
6132 6133 6134 6135 6136 6137
                                     si_rnti,
                                     ra_rnti,
                                     p_rnti,
                                     dlsch0_harq,
                                     dlsch0);
      break;
6138
    }
6139

6140 6141 6142
    case format2:
    {
        // extract dci infomation
hbilel's avatar
hbilel committed
6143
        //LOG_I(PHY,"[DCI-format2] AbsSubframe %d.%d extract dci infomation \n", frame, subframe);
6144 6145 6146 6147 6148 6149
        extract_dci2_info(frame_parms->N_RB_DL,
                frame_type,
                frame_parms->nb_antenna_ports_eNB,
                dci_pdu,
                &dci_info_extarcted);

6150

6151
        // check dci content
6152 6153
        dlsch[0]->active = 1;
        dlsch[1]->active = 1;
6154 6155 6156

            dlsch0 = dlsch[0];
            dlsch1 = dlsch[1];
6157

6158 6159
    dlsch0_harq = dlsch0->harq_processes[dci_info_extarcted.harq_pid];
    dlsch1_harq = dlsch1->harq_processes[dci_info_extarcted.harq_pid];
6160 6161 6162
   // printf("before coherency dlsch[1]->pmi_alloc %d\n",dlsch[1]->pmi_alloc);
   // printf("before coherency dlsch1->pmi_alloc %d\n",dlsch1->pmi_alloc);
   // printf("before coherency dlsch1_harq->pmi_alloc %d\n",dlsch1_harq->pmi_alloc);
6163

hbilel's avatar
hbilel committed
6164
        //LOG_I(PHY,"[DCI-format2] check dci content \n");
6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175 6176
        status = check_dci_format2_2a_coherency(format2,
                frame_parms->N_RB_DL,
                &dci_info_extarcted,
                rnti,
                si_rnti,
                ra_rnti,
                p_rnti,
                dlsch0_harq,
                dlsch1_harq);
        if(status == 0)
            return(-1);

6177

6178
        // dci is correct ==> update internal structure and prepare dl decoding
hbilel's avatar
hbilel committed
6179
        //LOG_I(PHY,"[DCI-format2] update internal structure and prepare dl decoding \n");
6180 6181 6182
        prepare_dl_decoding_format2_2A(format2,
                &dci_info_extarcted,
                frame_parms,
6183 6184
                pdcch_vars,
                pdsch_vars,
hbilel's avatar
hbilel committed
6185
                rnti,
6186 6187 6188 6189 6190
                subframe,
                dlsch0_harq,
                dlsch1_harq,
                dlsch0,
                dlsch1);
6191
    }
6192
    break;
6193

6194 6195 6196
    case format2A:
    {
    // extract dci infomation
hbilel's avatar
hbilel committed
6197
    LOG_I(PHY,"[DCI-format2] AbsSubframe %d.%d extract dci infomation \n", frame%1024, subframe);
6198 6199 6200 6201 6202 6203 6204
    extract_dci2A_info(frame_parms->N_RB_DL,
                       frame_type,
                       frame_parms->nb_antenna_ports_eNB,
                       dci_pdu,
                       &dci_info_extarcted);

    // check dci content
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hbilel committed
6205 6206 6207 6208
    //LOG_I(PHY,"[DCI-format2A] check dci content \n");
    //LOG_I(PHY,"[DCI-format2A] tb_swap %d harq_pid %d\n", dci_info_extarcted.tb_swap, dci_info_extarcted.harq_pid);
      //dlsch[0]->active = 0;
      //dlsch[1]->active = 0;
6209

6210
    if (dci_info_extarcted.tb_swap == 0) {
6211 6212
      dlsch0 = dlsch[0];
      dlsch1 = dlsch[1];
6213
    } else {
6214 6215
      dlsch0 = dlsch[1];
      dlsch1 = dlsch[0];
6216 6217 6218 6219
    }
    dlsch0_harq = dlsch0->harq_processes[dci_info_extarcted.harq_pid];
    dlsch1_harq = dlsch1->harq_processes[dci_info_extarcted.harq_pid];

hbilel's avatar
hbilel committed
6220
    //LOG_I(PHY,"[DCI-format2A] check dci content \n");
6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231 6232 6233
    status = check_dci_format2_2a_coherency(format2A,
                                              frame_parms->N_RB_DL,
                                              &dci_info_extarcted,
                                              rnti,
                                              si_rnti,
                                              ra_rnti,
                                              p_rnti,
                                              dlsch0_harq,
                                              dlsch1_harq);
    if(status == 0)
      return(-1);

    // dci is correct ==> update internal structure and prepare dl decoding
hbilel's avatar
hbilel committed
6234
    //LOG_I(PHY,"[DCI-format2A] update internal structure and prepare dl decoding \n");
6235 6236 6237
    prepare_dl_decoding_format2_2A(format2A,
                                   &dci_info_extarcted,
                                   frame_parms,
6238 6239
                                   pdcch_vars,
                                   pdsch_vars,
hbilel's avatar
hbilel committed
6240
                                   rnti,
6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252 6253 6254 6255 6256
                                   subframe,
                                   dlsch0_harq,
                                   dlsch1_harq,
                                   dlsch0,
                                   dlsch1);
    }
      break;

    case format1E_2A_M10PRB:
      if (!dlsch[0]) return -1;

      harq_pid  = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->harq_pid;

      if (harq_pid>=8) {
        LOG_E(PHY,"Format 1E_2A_M10PRB: harq_pid=%d >= 8\n", harq_pid);
        return(-1);
6257 6258
      }

6259 6260
      dlsch[0]->current_harq_pid = harq_pid;
      dlsch[0]->harq_ack[subframe].harq_id = harq_pid;
6261

6262 6263 6264 6265 6266 6267 6268 6269 6270 6271 6272 6273
      /*
        tbswap = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tb_swap;
        if (tbswap == 0) {
        dlsch0 = dlsch[0];
        dlsch1 = dlsch[1];
        }
        else{
        dlsch0 = dlsch[1];
        dlsch1 = dlsch[0];
        }
      */
      dlsch0 = dlsch[0];
6274

6275 6276 6277 6278 6279 6280
      dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
      // Needs to be checked
      dlsch0_harq->codeword=0;
      conv_rballoc(((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
                   ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,frame_parms->N_RB_DL,
                   dlsch0_harq->rb_alloc_even);
6281

6282 6283 6284 6285 6286 6287 6288 6289 6290 6291 6292
      dlsch0_harq->rb_alloc_odd[0]                         = dlsch0_harq->rb_alloc_even[0];
      dlsch0_harq->rb_alloc_odd[1]                         = dlsch0_harq->rb_alloc_even[1];
      dlsch0_harq->rb_alloc_odd[2]                         = dlsch0_harq->rb_alloc_even[2];
      dlsch0_harq->rb_alloc_odd[3]                         = dlsch0_harq->rb_alloc_even[3];
      /*
      dlsch1_harq->rb_alloc_even[0]                         = dlsch0_harq->rb_alloc_even[0];
      dlsch1_harq->rb_alloc_even[1]                         = dlsch0_harq->rb_alloc_even[1];
      dlsch1_harq->rb_alloc_even[2]                         = dlsch0_harq->rb_alloc_even[2];
      dlsch1_harq->rb_alloc_even[3]                         = dlsch0_harq->rb_alloc_even[3];
      */
      dlsch0_harq->nb_rb                               = conv_nprb(((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
6293 6294
								   ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,
								   frame_parms->N_RB_DL);
6295
      //dlsch1_harq->nb_rb                               = dlsch0_harq->nb_rb;
6296

6297 6298
      dlsch0_harq->mcs             = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs;
      dlsch0_harq->delta_PUCCH     = delta_PUCCH_lut[((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->TPC&3];
6299 6300 6301



6302 6303 6304 6305 6306 6307
      /*
        if (dlsch0_harq->mcs>20) {
        printf("dci_tools.c: mcs > 20 disabled for now (asked %d)\n",dlsch0_harq->mcs);
        return(-1);
        }
      */
6308

6309 6310 6311
      //dlsch1_harq->mcs       = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs2;
      dlsch0_harq->rvidx     = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv;
      //dlsch1_harq->rvidx     = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv2;
6312

6313
      // check if either TB is disabled (see 36-213 V8.6 p. 26)
6314

6315 6316 6317
      if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) {
        dlsch0_harq->status = DISABLED;
      }
6318

6319 6320 6321 6322
      //if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) {
      //dlsch1_harq->status = DISABLED;
      //}
      dlsch0_harq->Nl        = 1;
6323

6324 6325
      //dlsch0->layer_index                         = tbswap;
      //dlsch1->layer_index                         = 1-tbswap;
6326

6327

6328 6329 6330
      // Fix this
      tpmi = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tpmi;
      //    printf("ue: tpmi %d\n",tpmi);
6331

6332 6333 6334 6335
      switch (tpmi) {
      case 0 :
        dlsch0_harq->mimo_mode   = ALAMOUTI;
        break;
6336

6337 6338 6339 6340
      case 1:
        dlsch0_harq->mimo_mode   = UNIFORM_PRECODING11;
        dlsch0_harq->pmi_alloc   = pmi_extend(frame_parms,0,0);
        break;
6341

6342 6343 6344 6345
      case 2:
        dlsch0_harq->mimo_mode   = UNIFORM_PRECODING1m1;
        dlsch0_harq->pmi_alloc   = pmi_extend(frame_parms,1, 0);
        break;
6346

6347 6348 6349
      case 3:
        dlsch0_harq->mimo_mode   = UNIFORM_PRECODING1j;
        dlsch0_harq->pmi_alloc   = pmi_extend(frame_parms,2, 0);
6350

6351
        break;
6352

6353 6354 6355 6356
      case 4:
        dlsch0_harq->mimo_mode   = UNIFORM_PRECODING1mj;
        dlsch0_harq->pmi_alloc   = pmi_extend(frame_parms,3, 0);
        break;
6357

6358 6359 6360 6361 6362 6363
      case 5:
        dlsch0_harq->mimo_mode   = PUSCH_PRECODING0;
        // pmi stored from ulsch allocation routine
        dlsch0_harq->pmi_alloc   = dlsch0->pmi_alloc;
        //LOG_I(PHY,"XXX using PMI %x\n",pmi2hex_2Ar1(dlsch0_harq->pmi_alloc));
        break;
6364

6365

6366 6367 6368 6369 6370 6371
      case 6:
        dlsch0_harq->mimo_mode   = PUSCH_PRECODING1;
        LOG_E(PHY,"Unsupported TPMI\n");
        return(-1);
        break;
      }
6372

6373

6374
      if (frame_parms->nb_antenna_ports_eNB == 1)
6375
        dlsch0_harq->mimo_mode   = SISO;
6376

6377

6378
      if ((dlsch0_harq->DCINdi != ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi) ||
6379
	(dlsch0_harq->first_tx==1)) {
6380

6381
        dlsch0_harq->round = 0;
6382
	dlsch0_harq->first_tx = 0;
6383
        dlsch0_harq->status = ACTIVE;
6384
      }
6385 6386
      /*
	else if (dlsch0_harq->status == SCH_IDLE) { // we got same ndi for a previously decoded process,
6387 6388
        // this happens if either another harq process in the same
        // is NAK or an ACK was not received
6389

6390 6391 6392 6393 6394 6395
        dlsch0->harq_ack[subframe].ack              = 1;
        dlsch0->harq_ack[subframe].harq_id          = harq_pid;
        dlsch0->harq_ack[subframe].send_harq_status = 1;
        dlsch0->active = 0;
        return(0);
      }
6396
      */
6397

6398 6399
      dlsch0_harq->DCINdi = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi;
      dlsch0_harq->mcs    = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs;
6400

6401 6402 6403 6404
      if (dlsch0_harq->nb_rb>1) {
        dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
      } else
        dlsch0_harq->TBS         =0;
6405

6406 6407
      dlsch0->rnti = rnti;
      //dlsch1->rnti = rnti;
6408

6409 6410
      dlsch0->active = 1;
      //dlsch1->active = 1;
6411

6412 6413
      dlsch0_harq->dl_power_off = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->dl_power_off;
      //dlsch1_harq->dl_power_off = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->dl_power_off;
6414

6415

6416
      break;
6417

6418 6419 6420 6421 6422
    default:
      LOG_E(PHY,"format %d not yet implemented\n",dci_format);
      return(-1);
      break;
    }
6423

gabrielC's avatar
gabrielC committed
6424
#ifdef UE_DEBUG_TRACE
6425 6426

    if (dlsch[0] && (dlsch[0]->rnti != 0xffff)) {
gabrielC's avatar
gabrielC committed
6427
        LOG_I(PHY,"dci_format:%d Abssubframe: %d.%d \n",dci_format,frame%1024,subframe);
6428
        LOG_I(PHY,"PDSCH dlsch0 UE: rnti     %x\n",dlsch[0]->rnti);
gabrielC's avatar
gabrielC committed
6429 6430
        LOG_D(PHY,"PDSCH dlsch0 UE: NBRB     %d\n",dlsch0_harq->nb_rb);
        LOG_D(PHY,"PDSCH dlsch0 UE: rballoc  %x\n",dlsch0_harq->rb_alloc_even[0]);
6431 6432
        LOG_I(PHY,"PDSCH dlsch0 UE: harq_pid %d\n",dci_info_extarcted.harq_pid);
        LOG_I(PHY,"PDSCH dlsch0 UE: g        %d\n",dlsch[0]->g_pucch);
gabrielC's avatar
gabrielC committed
6433 6434 6435 6436 6437 6438
        LOG_D(PHY,"PDSCH dlsch0 UE: round    %d\n",dlsch0_harq->round);
        LOG_D(PHY,"PDSCH dlsch0 UE: DCINdi   %d\n",dlsch0_harq->DCINdi);
        LOG_D(PHY,"PDSCH dlsch0 UE: rvidx    %d\n",dlsch0_harq->rvidx);
        LOG_D(PHY,"PDSCH dlsch0 UE: TBS      %d\n",dlsch0_harq->TBS);
        LOG_D(PHY,"PDSCH dlsch0 UE: mcs      %d\n",dlsch0_harq->mcs);
        LOG_D(PHY,"PDSCH dlsch0 UE: pwr_off  %d\n",dlsch0_harq->dl_power_off);
6439
    }
6440
#endif
6441

Cedric Roux's avatar
Cedric Roux committed
6442
#if T_TRACER
6443 6444
    if( (dlsch[0]->rnti != si_rnti) && (dlsch[0]->rnti != ra_rnti) && (dlsch[0]->rnti != p_rnti))
    {
Cedric Roux's avatar
Cedric Roux committed
6445 6446 6447 6448 6449
      T(T_UE_PHY_DLSCH_UE_DCI, T_INT(0), T_INT(frame%1024), T_INT(subframe),
        T_INT(dlsch[0]->rnti), T_INT(dci_format),
        T_INT(harq_pid),
        T_INT(dlsch0_harq->mcs),
        T_INT(dlsch0_harq->TBS));
6450
    }
Cedric Roux's avatar
Cedric Roux committed
6451
#endif
6452 6453


6454 6455 6456 6457 6458
    // compute DL power control parameters
    if (dlsch0_harq != NULL){
      computeRhoA_UE(pdsch_config_dedicated, dlsch[0],dlsch0_harq->dl_power_off, frame_parms->nb_antenna_ports_eNB);
      computeRhoB_UE(pdsch_config_dedicated,&(frame_parms->pdsch_config_common),frame_parms->nb_antenna_ports_eNB,dlsch[0],dlsch0_harq->dl_power_off);
    }
6459

6460 6461 6462 6463
    if (dlsch1_harq != NULL) {
      computeRhoA_UE(pdsch_config_dedicated, dlsch[1],dlsch1_harq->dl_power_off, frame_parms->nb_antenna_ports_eNB);
      computeRhoB_UE(pdsch_config_dedicated,&(frame_parms->pdsch_config_common),frame_parms->nb_antenna_ports_eNB,dlsch[1],dlsch1_harq->dl_power_off);
    }
6464

6465 6466

    return(0);
6467 6468 6469
}


6470 6471
uint8_t subframe2harq_pid(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8_t subframe)
{
6472 6473
  uint8_t ret = 255;

6474
  if (frame_parms->frame_type == FDD) {
6475
    ret = (((frame*10)+subframe)&7);
6476
  } else {
6477 6478 6479 6480

    switch (frame_parms->tdd_config) {

    case 1:
6481 6482 6483 6484 6485 6486 6487
      if ((subframe==2) ||
          (subframe==3) ||
          (subframe==7) ||
          (subframe==8))
        switch (subframe) {
        case 2:
        case 3:
6488
          ret = (subframe-2);
6489 6490 6491 6492
          break;

        case 7:
        case 8:
6493
          ret = (subframe-5);
6494 6495 6496 6497
          break;

        default:
          LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config);
6498
          ret = (255);
6499 6500 6501
          break;
        }

6502
      break;
6503

6504 6505
    case 2:
      if ((subframe!=2) && (subframe!=7)) {
6506 6507
	LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config);
	ret=255;
6508
      }
6509
      else ret = (subframe/7);
6510
      break;
6511

6512 6513
    case 3:
      if ((subframe<2) || (subframe>4)) {
6514
        LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config);
6515
        ret = (255);
6516
      }
6517
      else ret = (subframe-2);
6518
      break;
6519

6520 6521
    case 4:
      if ((subframe<2) || (subframe>3)) {
6522
        LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config);
6523
        ret = (255);
6524
      }
6525
      else ret = (subframe-2);
6526
      break;
6527

6528 6529
    case 5:
      if (subframe!=2) {
6530
        LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config);
6531
        ret = (255);
6532
      }
6533
      else ret = (subframe-2);
6534
      break;
6535

6536 6537
    default:
      LOG_E(PHY,"subframe2_harq_pid, Unsupported TDD mode %d\n",frame_parms->tdd_config);
6538
      ret = (255);
6539 6540
    }
  }
6541

6542 6543
  AssertFatal(ret!=255,
	      "invalid harq_pid(%d) at SFN/SF = %d/%d\n", (int8_t)ret, frame, subframe);
6544
  return ret;
6545 6546
}

6547 6548
uint8_t pdcch_alloc2ul_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t n)
{
6549
  uint8_t ul_subframe = 255;
6550

6551
  if ((frame_parms->frame_type == TDD) &&
6552 6553
      (frame_parms->tdd_config == 1) &&
      ((n==1)||(n==6))) // tdd_config 0,1 SF 1,5
6554
    ul_subframe = ((n+6)%10);
6555 6556 6557
  else if ((frame_parms->frame_type == TDD) &&
           (frame_parms->tdd_config == 6) &&
           ((n==0)||(n==1)||(n==5)||(n==6)))
6558
    ul_subframe = ((n+7)%10);
6559 6560 6561
  else if ((frame_parms->frame_type == TDD) &&
           (frame_parms->tdd_config == 6) &&
           (n==9)) // tdd_config 6 SF 9
6562
    ul_subframe = ((n+5)%10);
6563
  else
6564
    ul_subframe = ((n+4)%10);
6565

6566
  //  AssertFatal(frame_parms->frame_type == FDD || subframe_select(frame_parms,ul_subframe) == SF_UL,"illegal ul_subframe %d (n %d)\n",ul_subframe,n);
6567

6568 6569
  LOG_D(PHY, "subframe %d: PUSCH subframe = %d\n", n, ul_subframe);
  return ul_subframe;
6570 6571
}

6572 6573 6574
uint8_t ul_subframe2pdcch_alloc_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t n)
{
  if ((frame_parms->frame_type == TDD) &&
6575 6576 6577
      (frame_parms->tdd_config == 1) &&
      ((n==7)||(n==2))) // tdd_config 0,1 SF 1,5
    return((n==7)? 1 : 6);
6578 6579 6580
  else if ((frame_parms->frame_type == TDD) &&
           (frame_parms->tdd_config == 6) &&
           ((n==7)||(n==8)||(n==2)||(n==3)))
6581
    return((n+3)%10);
6582 6583 6584
  else if ((frame_parms->frame_type == TDD) &&
           (frame_parms->tdd_config == 6) &&
           (n==4)) // tdd_config 6 SF 9
6585 6586 6587 6588 6589
    return(9);
  else
    return((n+6)%10);
}

6590 6591
uint32_t pdcch_alloc2ul_frame(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t n)
{
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6592
  uint32_t ul_frame;
6593

6594
  if ((frame_parms->frame_type == TDD) &&
6595 6596
      (frame_parms->tdd_config == 1) &&
      ((n==1)||(n==6))) // tdd_config 0,1 SF 1,5
6597
    ul_frame = (frame + (n==1 ? 0 : 1));
6598 6599 6600
  else if ((frame_parms->frame_type == TDD) &&
           (frame_parms->tdd_config == 6) &&
           ((n==0)||(n==1)||(n==5)||(n==6)))
6601
    ul_frame = (frame + (n>=5 ? 1 : 0));
6602 6603 6604
  else if ((frame_parms->frame_type == TDD) &&
           (frame_parms->tdd_config == 6) &&
           (n==9)) // tdd_config 6 SF 9
6605
    ul_frame = (frame+1);
6606
  else
6607 6608 6609
    ul_frame = (frame+(n>=6 ? 1 : 0));

  LOG_D(PHY, "frame %d subframe %d: PUSCH frame = %d\n", frame, n, ul_frame);
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6610
  return ul_frame % 1024;
6611 6612
}

6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649 6650 6651 6652 6653 6654 6655 6656 6657 6658
int32_t pmi_convert_rank1_from_rank2(uint16_t pmi_alloc, int tpmi, int nb_rb)
{
  int nb_subbands = 0;
  int32_t pmi_alloc_new = 0, pmi_new = 0, pmi_old = 0;
  int i;

  switch (nb_rb) {
    case 6:
      nb_subbands = 6;
      break;
    default:
    case 25:
      nb_subbands = 7;
      break;
    case 50:
      nb_subbands = 9;
      break;
    case 100:
      nb_subbands = 13;
      break;
    }

  for (i = 0; i < nb_subbands; i++) {
    pmi_old = (pmi_alloc >> i)&1;

    if (pmi_old == 0)
      if (tpmi == 5)
        pmi_new = 0;
      else
        pmi_new = 1;
    else
      if (tpmi == 5)
        pmi_new = 2;
      else
        pmi_new = 3;

    pmi_alloc_new|=pmi_new<<(2*i);

  }
#ifdef DEBUG_HARQ
printf("  [DCI UE] pmi_alloc_old %d, pmi_alloc_new %d pmi_old %d , pmi_new %d\n", pmi_alloc, pmi_alloc_new,pmi_old, pmi_new );
#endif
return(pmi_alloc_new);

}

6659
uint16_t quantize_subband_pmi(PHY_MEASUREMENTS *meas,uint8_t eNB_id,int nb_rb)
6660
{
6661 6662 6663

  int i, aarx;
  uint16_t pmiq=0;
6664
  uint32_t pmivect = 0;
6665 6666
  uint8_t rank = meas->rank[eNB_id];
  int pmi_re,pmi_im;
6667
  int  nb_subbands=0;
6668 6669


6670 6671 6672 6673 6674 6675 6676 6677 6678 6679 6680 6681 6682 6683 6684
  switch (nb_rb) {
    case 6:
      nb_subbands = 6;
      break;
    default:
    case 25:
      nb_subbands = 7;
      break;
    case 50:
      nb_subbands = 9;
      break;
    case 100:
      nb_subbands = 13;
      break;
    }
6685

6686

6687
  for (i=0; i<nb_subbands; i++) {
6688 6689 6690 6691 6692
    pmi_re = 0;
    pmi_im = 0;

    if (rank == 0) {
      for (aarx=0; aarx<meas->nb_antennas_rx; aarx++) {
6693 6694
        pmi_re += meas->subband_pmi_re[eNB_id][i][aarx];
        pmi_im += meas->subband_pmi_im[eNB_id][i][aarx];
6695 6696 6697 6698 6699 6700 6701
      }

      //  pmi_re = meas->subband_pmi_re[eNB_id][i][meas->selected_rx_antennas[eNB_id][i]];
      //  pmi_im = meas->subband_pmi_im[eNB_id][i][meas->selected_rx_antennas[eNB_id][i]];

      //      printf("pmi => (%d,%d)\n",pmi_re,pmi_im);
      if ((pmi_re > pmi_im) && (pmi_re > -pmi_im))
6702
        pmiq = PMI_2A_11;
6703
      else if ((pmi_re < pmi_im) && (pmi_re > -pmi_im))
6704
        pmiq = PMI_2A_1j;
6705
      else if ((pmi_re < pmi_im) && (pmi_re < -pmi_im))
6706
        pmiq = PMI_2A_1m1;
6707
      else if ((pmi_re > pmi_im) && (pmi_re < -pmi_im))
6708 6709
        pmiq = PMI_2A_1mj;

6710 6711
      //      printf("subband %d, pmi%d \n",i,pmiq);
      pmivect |= (pmiq<<(2*i));
6712 6713
    }

6714 6715 6716
    else if (rank==1) {
      for (aarx=0; aarx<meas->nb_antennas_rx; aarx++) {
        pmi_re += meas->subband_pmi_re[eNB_id][i][aarx];
6717
  //printf("meas->subband_pmi_re[eNB_id][i][%d]=%d\n", aarx, meas->subband_pmi_re[eNB_id][i][aarx]);
6718
        pmi_im += meas->subband_pmi_im[eNB_id][i][aarx];
6719 6720 6721 6722 6723 6724
  //printf("meas->subband_pmi_im[eNB_id][i][%d]=%d\n",aarx, meas->subband_pmi_im[eNB_id][i][aarx]);
      }
     if (pmi_re >= pmi_im) // this is not orthogonal
     // this is orthogonal
     //if (((pmi_re >= pmi_im) && (pmi_re >= -pmi_im)) || ((pmi_re <= pmi_im) && (pmi_re >= -pmi_im)))
       pmiq = PMI_2A_R1_11;
6725
     else
6726
       pmiq = PMI_2A_R1_1j;
6727

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6728
     // printf("subband %d, pmi_re %d, pmi_im %d, pmiq %d \n",i,pmi_re,pmi_im,pmiq);
6729
     // printf("subband %d, pmi%d \n",i,pmiq);
6730
      //According to Section 7.2.4 of 36.213
6731 6732

      pmivect |= ((pmiq-1)<<(i)); //shift 1 since only one bit
6733
    }
6734 6735
    else {
      LOG_E(PHY,"PMI feedback for rank>1 not supported!\n");
6736 6737 6738 6739
      pmivect = 0;
    }

  }
6740 6741 6742
#ifdef DEBUG_HARQ
    printf( "quantize_subband_pmi pmivect %d \n", pmivect);
#endif
6743 6744 6745
  return(pmivect);
}

6746 6747
uint16_t quantize_subband_pmi2(PHY_MEASUREMENTS *meas,uint8_t eNB_id,uint8_t a_id,int nb_subbands)
{
6748 6749 6750 6751 6752 6753 6754

  uint8_t i;
  uint16_t pmiq=0;
  uint16_t pmivect = 0;
  uint8_t rank = meas->rank[eNB_id];
  int pmi_re,pmi_im;

6755
  for (i=0; i<nb_subbands; i++) {
6756 6757 6758 6759 6760 6761

    if (rank == 0) {
      pmi_re = meas->subband_pmi_re[eNB_id][i][a_id];
      pmi_im = meas->subband_pmi_im[eNB_id][i][a_id];

      if ((pmi_re > pmi_im) && (pmi_re > -pmi_im))
6762
        pmiq = PMI_2A_11;
6763
      else if ((pmi_re < pmi_im) && (pmi_re > -pmi_im))
6764
        pmiq = PMI_2A_1j;
6765
      else if ((pmi_re < pmi_im) && (pmi_re < -pmi_im))
6766
        pmiq = PMI_2A_1m1;
6767
      else if ((pmi_re > pmi_im) && (pmi_re < -pmi_im))
6768 6769
        pmiq = PMI_2A_1mj;

6770
      pmivect |= (pmiq<<(2*i));
6771
    } else {
6772 6773 6774 6775 6776 6777 6778 6779
      // This needs to be done properly!!!
      pmivect = 0;
    }
  }

  return(pmivect);
}

6780 6781
uint16_t quantize_wideband_pmi(PHY_MEASUREMENTS *meas,uint8_t eNB_id)
{
6782 6783 6784 6785 6786 6787 6788 6789 6790 6791

  uint16_t pmiq=0;
  uint8_t rank = meas->rank[eNB_id];
  //int pmi;
  int pmi_re,pmi_im;

  if (rank == 1) {
    //pmi =
    pmi_re = meas->wideband_pmi_re[eNB_id][meas->selected_rx_antennas[eNB_id][0]];
    pmi_im = meas->wideband_pmi_im[eNB_id][meas->selected_rx_antennas[eNB_id][0]];
6792

6793 6794 6795 6796 6797 6798 6799 6800 6801
    if ((pmi_re > pmi_im) && (pmi_re > -pmi_im))
      pmiq = PMI_2A_11;
    else if ((pmi_re < pmi_im) && (pmi_re > -pmi_im))
      pmiq = PMI_2A_1j;
    else if ((pmi_re < pmi_im) && (pmi_re < -pmi_im))
      pmiq = PMI_2A_1m1;
    else if ((pmi_re > pmi_im) && (pmi_re < -pmi_im))
      pmiq = PMI_2A_1mj;

6802
  } else {
6803 6804 6805 6806 6807 6808 6809 6810 6811 6812 6813 6814 6815 6816 6817 6818 6819
    // This needs to be done properly!
    pmiq = PMI_2A_11;
  }


  return(pmiq);
}
/*
  uint8_t sinr2cqi(int sinr) {
  if (sinr<-3)
  return(0);
  if (sinr>14)
  return(10);
  else
  return(3+(sinr>>1));
  }
*/
6820 6821 6822

uint8_t sinr2cqi(double sinr,uint8_t trans_mode)
{
6823
  // int flag_LA=0;
6824

6825 6826
  uint8_t retValue = 0;

6827
  if(flag_LA==0) {
6828 6829
    // Ideal Channel Estimation
    if (sinr<=-4.89)
6830
      retValue = (0);
6831
    else if (sinr < -3.53)
6832
      retValue = (3);
6833
    else if (sinr <= -1.93)
6834
      retValue = (4);
6835
    else if (sinr <= -0.43)
6836
      retValue = (5);
6837
    else if (sinr <= 1.11)
6838
      retValue = (6);
6839
    else if (sinr <= 3.26)
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      retValue = (7);
    else if (sinr <= 5.0)
      retValue = (8);
    else if (sinr <= 7.0)
      retValue = (9);
    else if (sinr <= 9.0)
      retValue = (10);
    else if (sinr <= 11.0)
      retValue = (11);
    else if (sinr <= 13.0)
      retValue = (12);
6851
    else if (sinr <= 15.5)
6852
      retValue = (13);
6853
    else if (sinr <= 17.5)
6854 6855 6856
      retValue = (14);
    else
      retValue = (15);
6857
  } else {
6858 6859
    int h=0;
    int trans_mode_tmp;
6860

6861 6862
    if (trans_mode ==5)
      trans_mode_tmp=2;
6863 6864 6865 6866 6867 6868
    else if(trans_mode ==6)
      trans_mode_tmp=3;
    else
      trans_mode_tmp = trans_mode-1;

    for(h=0; h<16; h++) {
6869
      if(sinr<=sinr_to_cqi[trans_mode_tmp][h])
6870
        retValue = (h);
6871 6872
    }
  }
6873

6874 6875
  LOG_D(PHY, "sinr=%f trans_mode=%d cqi=%d\n", sinr, trans_mode, retValue);
  return retValue;
6876 6877 6878
}
//uint32_t fill_subband_cqi(PHY_MEASUREMENTS *meas,uint8_t eNB_id) {
//
6879 6880 6881
//  uint8_t i;
////  uint16_t cqivect = 0;
//  uint32_t cqivect = 0;
6882
//
6883 6884
////  char diff_cqi;
//  int diff_cqi=0;
6885
//
6886
//  for (i=0;i<NUMBER_OF_SUBBANDS;i++) {
6887
//
6888
//    diff_cqi = -sinr2cqi(meas->wideband_cqi_dB[eNB_id][0]) + sinr2cqi(meas->subband_cqi_dB[eNB_id][0][i]);
6889
//
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//    // Note, this is Table 7.2.1-2 from 36.213
//    if (diff_cqi<=-1)
//      diff_cqi = 3;
//    else if (diff_cqi>2)
//      diff_cqi = 2;
//    cqivect |= (diff_cqi<<(2*i));
6896
//
6897
//  }
6898
//
6899
//  return(cqivect);
6900 6901 6902
//}


6903 6904
uint32_t fill_subband_cqi(PHY_MEASUREMENTS *meas,uint8_t eNB_id,uint8_t trans_mode,int nb_subbands)
{
6905 6906 6907 6908 6909 6910 6911 6912

  uint8_t i;

  uint32_t cqivect = 0,offset=0;


  int diff_cqi=0;

6913
  for (i=0; i<nb_subbands; i++) {
6914 6915 6916 6917 6918 6919

    diff_cqi = -sinr2cqi(meas->wideband_cqi_avg[eNB_id],trans_mode) + sinr2cqi(meas->subband_cqi_tot_dB[eNB_id][i],trans_mode);

    // Note, this is Table 7.2.1-2 from 36.213
    if (diff_cqi<=-1)
      offset = 3;
6920 6921
    else if (diff_cqi>=2)
      offset = 2;
6922
    else
6923
      offset=(uint32_t)diff_cqi;
6924 6925 6926 6927 6928 6929 6930 6931

    cqivect |= (offset<<(2*i));

  }

  return(cqivect);
}

6932 6933 6934
void fill_CQI(LTE_UE_ULSCH_t *ulsch,PHY_MEASUREMENTS *meas,uint8_t eNB_id,uint8_t harq_pid,int N_RB_DL,uint16_t rnti, uint8_t trans_mode, double sinr_eff)
{

6935
  //  printf("[PHY][UE] Filling CQI for eNB %d, meas->wideband_cqi_tot[%d] %d\n",
6936 6937
  //      eNB_id,eNB_id,meas->wideband_cqi_tot[eNB_id]);
  double sinr_tmp;
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6938 6939 6940
  uint8_t *o = ulsch->o;
  UCI_format_t uci_format = ulsch->uci_format;

6941 6942 6943
  if(flag_LA==1)
    sinr_tmp = sinr_eff;
  else
6944 6945
    sinr_tmp = (double) meas->wideband_cqi_avg[eNB_id];

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6946 6947


6948
  //LOG_I(PHY,"[UE][UCI] Filling CQI format %d for eNB %d N_RB_DL %d\n",uci_format,eNB_id,N_RB_DL);
6949

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6950 6951 6952 6953 6954 6955 6956 6957
  switch (N_RB_DL) {

  case 6:
    switch (uci_format) {
    case wideband_cqi_rank1_2A:
      ((wideband_cqi_rank1_2A_1_5MHz *)o)->cqi1 = sinr2cqi(sinr_tmp,trans_mode);
      ((wideband_cqi_rank1_2A_1_5MHz *)o)->pmi  = quantize_subband_pmi(meas,eNB_id,6);
      break;
6958

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6959 6960 6961 6962 6963
    case wideband_cqi_rank2_2A:
      ((wideband_cqi_rank2_2A_1_5MHz *)o)->cqi1 = sinr2cqi(sinr_tmp,trans_mode); //FIXME: calculate rank2 cqi
      ((wideband_cqi_rank2_2A_1_5MHz *)o)->cqi2 = sinr2cqi(sinr_tmp,trans_mode); //FIXME: calculate rank2 cqi
      ((wideband_cqi_rank2_2A_1_5MHz *)o)->pmi  = quantize_subband_pmi(meas,eNB_id,6);
      break;
6964

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6965 6966 6967 6968
    case HLC_subband_cqi_nopmi:
      ((HLC_subband_cqi_nopmi_1_5MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_nopmi_1_5MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,6);
      break;
6969

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6970 6971 6972 6973 6974
    case HLC_subband_cqi_rank1_2A:
      ((HLC_subband_cqi_rank1_2A_1_5MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank1_2A_1_5MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,6);
      ((HLC_subband_cqi_rank1_2A_1_5MHz *)o)->pmi      = quantize_wideband_pmi(meas,eNB_id);
      break;
6975

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    case HLC_subband_cqi_rank2_2A:
      // This has to be improved!!!
      ((HLC_subband_cqi_rank2_2A_1_5MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank2_2A_1_5MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,6);
      ((HLC_subband_cqi_rank2_2A_1_5MHz *)o)->cqi2     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank2_2A_1_5MHz *)o)->diffcqi2 = fill_subband_cqi(meas,eNB_id,trans_mode,6);
      ((HLC_subband_cqi_rank2_2A_1_5MHz *)o)->pmi      = quantize_subband_pmi(meas,eNB_id,6);
      break;
6984

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6985
    case HLC_subband_cqi_mcs_CBA:
6986
      // this is the cba mcs uci for cba transmission
6987
      ((HLC_subband_cqi_mcs_CBA_1_5MHz *)o)->mcs     = ulsch->harq_processes[harq_pid]->mcs;
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6988
      ((HLC_subband_cqi_mcs_CBA_1_5MHz *)o)->crnti  = rnti;
6989
      LOG_D(PHY,"fill uci for cba rnti %x, mcs %d \n", rnti, ulsch->harq_processes[harq_pid]->mcs);
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6990
      break;
6991

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6992 6993
    case ue_selected:
      LOG_E(PHY,"fill_CQI ue_selected CQI not supported yet!!!\n");
6994
      AssertFatal(1==0,"fill_CQI ue_selected CQI not supported yet!!!");
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6995
      break;
6996

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6997 6998
    default:
      LOG_E(PHY,"unsupported CQI mode (%d)!!!\n",uci_format);
6999
      AssertFatal(1==0,"unsupported CQI mode !!!");
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7000
      break;
7001

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7002
    }
7003

7004
    break;
7005

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  case 25:
    switch (uci_format) {
    case wideband_cqi_rank1_2A:
      ((wideband_cqi_rank1_2A_5MHz *)o)->cqi1 = sinr2cqi(sinr_tmp,trans_mode);
      ((wideband_cqi_rank1_2A_5MHz *)o)->pmi  = quantize_subband_pmi(meas,eNB_id,7);
      break;
7012

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    case wideband_cqi_rank2_2A:
      ((wideband_cqi_rank2_2A_5MHz *)o)->cqi1 = sinr2cqi(sinr_tmp,trans_mode); //FIXME: calculate rank2 cqi
      ((wideband_cqi_rank2_2A_5MHz *)o)->cqi2 = sinr2cqi(sinr_tmp,trans_mode); //FIXME: calculate rank2 cqi
      ((wideband_cqi_rank2_2A_5MHz *)o)->pmi  = quantize_subband_pmi(meas,eNB_id,7);
      break;
7018

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    case HLC_subband_cqi_nopmi:
      ((HLC_subband_cqi_nopmi_5MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_nopmi_5MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,7);
      break;
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    case HLC_subband_cqi_rank1_2A:
      ((HLC_subband_cqi_rank1_2A_5MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank1_2A_5MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,7);
      ((HLC_subband_cqi_rank1_2A_5MHz *)o)->pmi      = quantize_wideband_pmi(meas,eNB_id);
      break;
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    case HLC_subband_cqi_rank2_2A:
      // This has to be improved!!!
      ((HLC_subband_cqi_rank2_2A_5MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank2_2A_5MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,7);
      ((HLC_subband_cqi_rank2_2A_5MHz *)o)->cqi2     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank2_2A_5MHz *)o)->diffcqi2 = fill_subband_cqi(meas,eNB_id,trans_mode,7);
      ((HLC_subband_cqi_rank2_2A_5MHz *)o)->pmi      = quantize_subband_pmi(meas,eNB_id,7);
      break;
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7039
    case HLC_subband_cqi_mcs_CBA:
7040
      // this is the cba mcs uci for cba transmission
7041
      ((HLC_subband_cqi_mcs_CBA_5MHz *)o)->mcs     = ulsch->harq_processes[harq_pid]->mcs;
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      ((HLC_subband_cqi_mcs_CBA_5MHz *)o)->crnti  = rnti;
7043
      LOG_N(PHY,"fill uci for cba rnti %x, mcs %d \n", rnti, ulsch->harq_processes[harq_pid]->mcs);
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      break;
7045

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    case ue_selected:
      LOG_E(PHY,"fill_CQI ue_selected CQI not supported yet!!!\n");
7048
      AssertFatal(1==0,"fill_CQI ue_selected CQI not supported yet!!!");
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      break;
7050

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    default:
      LOG_E(PHY,"unsupported CQI mode (%d)!!!\n",uci_format);
7053
      AssertFatal(1==0,"unsupported CQI mode !!!");
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      break;
7055

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    }
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    break;

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  case 50:
    switch (uci_format) {
    case wideband_cqi_rank1_2A:
      ((wideband_cqi_rank1_2A_10MHz *)o)->cqi1 = sinr2cqi(sinr_tmp,trans_mode);
      ((wideband_cqi_rank1_2A_10MHz *)o)->pmi  = quantize_subband_pmi(meas,eNB_id,9);
      break;
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    case wideband_cqi_rank2_2A:
      ((wideband_cqi_rank2_2A_10MHz *)o)->cqi1 = sinr2cqi(sinr_tmp,trans_mode); //FIXME: calculate rank2 cqi
      ((wideband_cqi_rank2_2A_10MHz *)o)->cqi2 = sinr2cqi(sinr_tmp,trans_mode); //FIXME: calculate rank2 cqi
      ((wideband_cqi_rank2_2A_10MHz *)o)->pmi  = quantize_subband_pmi(meas,eNB_id,9);
      break;
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    case HLC_subband_cqi_nopmi:
      ((HLC_subband_cqi_nopmi_10MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_nopmi_10MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,9);
      break;
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    case HLC_subband_cqi_rank1_2A:
      ((HLC_subband_cqi_rank1_2A_10MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank1_2A_10MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,9);
      ((HLC_subband_cqi_rank1_2A_10MHz *)o)->pmi      = quantize_wideband_pmi(meas,eNB_id);
      break;
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    case HLC_subband_cqi_rank2_2A:
      // This has to be improved!!!
      ((HLC_subband_cqi_rank2_2A_10MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank2_2A_10MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,9);
      ((HLC_subband_cqi_rank2_2A_10MHz *)o)->cqi2     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank2_2A_10MHz *)o)->diffcqi2 = fill_subband_cqi(meas,eNB_id,trans_mode,9);
      ((HLC_subband_cqi_rank2_2A_10MHz *)o)->pmi      = quantize_subband_pmi(meas,eNB_id,9);
      break;
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    case HLC_subband_cqi_mcs_CBA:
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      // this is the cba mcs uci for cba transmission
      ((HLC_subband_cqi_mcs_CBA_10MHz *)o)->mcs     = ulsch->harq_processes[harq_pid]->mcs;
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      ((HLC_subband_cqi_mcs_CBA_10MHz *)o)->crnti  = rnti;
7097
      LOG_N(PHY,"fill uci for cba rnti %x, mcs %d \n", rnti, ulsch->harq_processes[harq_pid]->mcs);
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      break;
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    case ue_selected:
      LOG_E(PHY,"fill_CQI ue_selected CQI not supported yet!!!\n");
7102
      AssertFatal(1==0,"fill_CQI ue_selected CQI not supported yet!!!");
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7103
      break;
7104

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    default:
      LOG_E(PHY,"unsupported CQI mode (%d)!!!\n",uci_format);
7107
      AssertFatal(1==0,"unsupported CQI mode !!!");
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7108
      break;
7109

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    }
7111

7112
    break;
7113

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  case 100:
    switch (uci_format) {
    case wideband_cqi_rank1_2A:
      ((wideband_cqi_rank1_2A_20MHz *)o)->cqi1 = sinr2cqi(sinr_tmp,trans_mode);
      ((wideband_cqi_rank1_2A_20MHz *)o)->pmi  = quantize_subband_pmi(meas,eNB_id,13);
      break;
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    case wideband_cqi_rank2_2A:
      ((wideband_cqi_rank2_2A_20MHz *)o)->cqi1 = sinr2cqi(sinr_tmp,trans_mode); //FIXME: calculate rank2 cqi
      ((wideband_cqi_rank2_2A_20MHz *)o)->cqi2 = sinr2cqi(sinr_tmp,trans_mode); //FIXME: calculate rank2 cqi
      ((wideband_cqi_rank2_2A_20MHz *)o)->pmi  = quantize_subband_pmi(meas,eNB_id,13);
      break;
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    case HLC_subband_cqi_nopmi:
      ((HLC_subband_cqi_nopmi_20MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_nopmi_20MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,13);
      break;
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    case HLC_subband_cqi_rank1_2A:
      ((HLC_subband_cqi_rank1_2A_20MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank1_2A_20MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,13);
      ((HLC_subband_cqi_rank1_2A_20MHz *)o)->pmi      = quantize_wideband_pmi(meas,eNB_id);
      break;
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    case HLC_subband_cqi_rank2_2A:
      // This has to be improved!!!
      ((HLC_subband_cqi_rank2_2A_20MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank2_2A_20MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode,13);
      ((HLC_subband_cqi_rank2_2A_20MHz *)o)->cqi2     = sinr2cqi(sinr_tmp,trans_mode);
      ((HLC_subband_cqi_rank2_2A_20MHz *)o)->diffcqi2 = fill_subband_cqi(meas,eNB_id,trans_mode,13);
      ((HLC_subband_cqi_rank2_2A_20MHz *)o)->pmi      = quantize_subband_pmi(meas,eNB_id,13);
      break;
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7147
    case HLC_subband_cqi_mcs_CBA:
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      // this is the cba mcs uci for cba transmission
      ((HLC_subband_cqi_mcs_CBA_20MHz *)o)->mcs     = ulsch->harq_processes[harq_pid]->mcs;
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7150
      ((HLC_subband_cqi_mcs_CBA_20MHz *)o)->crnti  = rnti;
7151
      LOG_N(PHY,"fill uci for cba rnti %x, mcs %d \n", rnti, ulsch->harq_processes[harq_pid]->mcs);
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      break;
7153

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    case ue_selected:
      LOG_E(PHY,"fill_CQI ue_selected CQI not supported yet!!!\n");
7156
      AssertFatal(1==0,"fill_CQI ue_selected CQI not supported yet!!!");
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      break;
7158

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    default:
      LOG_E(PHY,"unsupported CQI mode (%d)!!!\n",uci_format);
7161
      AssertFatal(1==0,"unsupported CQI mode !!!");
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      break;
7163

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    }
7165

7166
    break;
7167

7168
  }
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7170

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}

7173 7174 7175
void reset_cba_uci(void *o)
{
  // this is the cba mcs uci for cba transmission
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  ((HLC_subband_cqi_mcs_CBA_5MHz *)o)->mcs     = 0; //fixme
  ((HLC_subband_cqi_mcs_CBA_5MHz *)o)->crnti  = 0x0;
}

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7181
uint32_t pmi_extend(LTE_DL_FRAME_PARMS *frame_parms,uint8_t wideband_pmi, uint8_t rank)
7182
{
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7184
  uint8_t i,wideband_pmi2;
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  uint32_t pmi_ex = 0;

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  if (frame_parms->N_RB_DL!=25) {
    LOG_E(PHY,"pmi_extend not yet implemented for anything else than 25PRB\n");
    return(-1);
  }

  if (rank==0) {
    wideband_pmi2=wideband_pmi&3;
    for (i=0; i<14; i+=2)
      pmi_ex|=(wideband_pmi2<<i);
  }
  else if (rank==1) {
    wideband_pmi2=wideband_pmi&1;
    for (i=0; i<7; i++)
      pmi_ex|=(wideband_pmi2<<i);
  }
  else {
    LOG_E(PHY,"unsupported rank\n");
    return(-1);
  }
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  return(pmi_ex);
}


int generate_ue_ulsch_params_from_dci(void *dci_pdu,
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                                      uint16_t rnti,
                                      uint8_t subframe,
                                      DCI_format_t dci_format,
7215
                                      PHY_VARS_UE *ue,
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                                      UE_rxtx_proc_t *proc,
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                                      uint16_t si_rnti,
                                      uint16_t ra_rnti,
                                      uint16_t p_rnti,
                                      uint16_t cba_rnti,
                                      uint8_t eNB_id,
                                      uint8_t use_srs)
{
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  uint8_t harq_pid;
7226
  uint8_t transmission_mode = ue->transmission_mode[eNB_id];
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  ANFBmode_t AckNackFBMode;
7228
  LTE_UE_ULSCH_t *ulsch = ue->ulsch[eNB_id];
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  LTE_UE_DLSCH_t **dlsch = ue->dlsch[ue->current_thread_id[subframe]][0];
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  PHY_MEASUREMENTS *meas = &ue->measurements;
  LTE_DL_FRAME_PARMS *frame_parms = &ue->frame_parms;
  //  uint32_t current_dlsch_cqi = ue->current_dlsch_cqi[eNB_id];
7233

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  if(frame_parms->frame_type == TDD)
  {
      AckNackFBMode = ue->pucch_config_dedicated[eNB_id].tdd_AckNackFeedbackMode;
  }
  else
  {
      AckNackFBMode = 1; // 1: multiplexing for FDD
  }

7243
  uint32_t cqi_req;
7244
  uint32_t dai=3;
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  uint32_t cshift;
  uint32_t TPC;
  uint32_t ndi;
  uint32_t mcs;
  uint32_t rballoc,RIV_max;
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  uint16_t* RIV2first_rb_LUT;
  uint16_t* RIV2nb_rb_LUT;

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  //  uint32_t hopping;
  //  uint32_t type;

  if (dci_format == format0) {

7258 7259 7260
    if (!ulsch)
      return -1;

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    if (rnti == ra_rnti)
      harq_pid = 0;
    else
      harq_pid = subframe2harq_pid(frame_parms,
7265
                                   pdcch_alloc2ul_frame(frame_parms,proc->frame_rx,subframe),
7266
                                   pdcch_alloc2ul_subframe(frame_parms,subframe));
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    LOG_D(PHY,"Frame %d, Subframe %d: Programming ULSCH for (%d.%d) => harq_pid %d\n",
	  proc->frame_rx,subframe,
	  pdcch_alloc2ul_frame(frame_parms,proc->frame_rx,subframe),
	  pdcch_alloc2ul_subframe(frame_parms,subframe), harq_pid);
7271

7272 7273
    if (harq_pid == 255) {
      LOG_E(PHY, "frame %d, subframe %d, rnti %x, format %d: illegal harq_pid!\n",
7274
            proc->frame_rx, subframe, rnti, dci_format);
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      return(-1);
    }

    switch (frame_parms->N_RB_DL) {
    case 6:
      if (frame_parms->frame_type == TDD) {
7281 7282 7283 7284 7285 7286 7287
        cqi_req = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
        dai     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->dai;
        cshift  = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
        ndi     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
        mcs     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
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        //  hopping = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->hopping=hopping;
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        //  type    = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->type;
      } else {
        cqi_req = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->cqi_req;
        cshift  = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->TPC;
        ndi     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->ndi;
        mcs     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->rballoc;
7297
        //  hopping = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->hopping=hopping;
7298
        //  type    = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->type;
7299
      }
7300

7301
      RIV_max = RIV_max6;
7302 7303
      RIV2first_rb_LUT = RIV2first_rb_LUT6;
      RIV2nb_rb_LUT = RIV2nb_rb_LUT6;
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      break;

    case 25:
      if (frame_parms->frame_type == TDD) {
7309 7310 7311 7312 7313 7314 7315
        cqi_req = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
        dai     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->dai;
        cshift  = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
        ndi     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
        mcs     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
7316
        //  hopping = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->hopping=hopping;
7317 7318 7319 7320 7321 7322 7323 7324
        //  type    = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->type;
      } else {
        cqi_req = ((DCI0_5MHz_FDD_t *)dci_pdu)->cqi_req;
        cshift  = ((DCI0_5MHz_FDD_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_5MHz_FDD_t *)dci_pdu)->TPC;
        ndi     = ((DCI0_5MHz_FDD_t *)dci_pdu)->ndi;
        mcs     = ((DCI0_5MHz_FDD_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_5MHz_FDD_t *)dci_pdu)->rballoc;
7325
        //  hopping = ((DCI0_5MHz_FDD_t *)dci_pdu)->hopping=hopping;
7326
        //  type    = ((DCI0_5MHz_FDD_t *)dci_pdu)->type;
7327
      }
7328

7329
      RIV_max = RIV_max25;
7330 7331
      RIV2first_rb_LUT = RIV2first_rb_LUT25;
      RIV2nb_rb_LUT = RIV2nb_rb_LUT25;
7332
      //      printf("***********rballoc %d, first_rb %d, nb_rb %d (dci %p)\n",rballoc,ulsch->harq_processes[harq_pid]->first_rb,ulsch->harq_processes[harq_pid]->nb_rb,dci_pdu);
7333 7334 7335 7336
      break;

    case 50:
      if (frame_parms->frame_type == TDD) {
7337 7338 7339 7340 7341 7342 7343
        cqi_req = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
        dai     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->dai;
        cshift  = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->TPC;
        ndi     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->ndi;
        mcs     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
7344
        //  hopping = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->hopping=hopping;
7345 7346 7347 7348 7349 7350 7351 7352
        //  type    = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->type;
      } else {
        cqi_req = ((DCI0_10MHz_FDD_t *)dci_pdu)->cqi_req;
        cshift  = ((DCI0_10MHz_FDD_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_10MHz_FDD_t *)dci_pdu)->TPC;
        ndi     = ((DCI0_10MHz_FDD_t *)dci_pdu)->ndi;
        mcs     = ((DCI0_10MHz_FDD_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_10MHz_FDD_t *)dci_pdu)->rballoc;
7353
        //  hopping = ((DCI0_10MHz_FDD_t *)dci_pdu)->hopping=hopping;
7354
        //  type    = ((DCI0_10MHz_FDD_t *)dci_pdu)->type;
7355 7356 7357
      }

      RIV_max = RIV_max50;
7358 7359
      RIV2first_rb_LUT = RIV2first_rb_LUT50;
      RIV2nb_rb_LUT = RIV2nb_rb_LUT50;
7360 7361

      break;
7362

7363 7364
    case 100:
      if (frame_parms->frame_type == TDD) {
7365 7366 7367 7368 7369 7370 7371
        cqi_req = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
        dai     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->dai;
        cshift  = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->TPC;
        ndi     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->ndi;
        mcs     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
7372
        //  hopping = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->hopping=hopping;
7373 7374 7375 7376 7377 7378 7379 7380
        //  type    = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->type;
      } else {
        cqi_req = ((DCI0_20MHz_FDD_t *)dci_pdu)->cqi_req;
        cshift  = ((DCI0_20MHz_FDD_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_20MHz_FDD_t *)dci_pdu)->TPC;
        ndi     = ((DCI0_20MHz_FDD_t *)dci_pdu)->ndi;
        mcs     = ((DCI0_20MHz_FDD_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_20MHz_FDD_t *)dci_pdu)->rballoc;
7381
        //  hopping = ((DCI0_20MHz_FDD_t *)dci_pdu)->hopping=hopping;
7382
        //  type    = ((DCI0_20MHz_FDD_t *)dci_pdu)->type;
7383
      }
7384

7385
      RIV_max = RIV_max100;
7386 7387
      RIV2first_rb_LUT = RIV2first_rb_LUT100;
      RIV2nb_rb_LUT = RIV2nb_rb_LUT100;
7388

Raymond Knopp's avatar
Raymond Knopp committed
7389
      //      printf("rb_alloc (20 MHz dci) %d\n",rballoc);
7390 7391 7392
      break;

    default:
winckel's avatar
winckel committed
7393 7394
      LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
      DevParam (frame_parms->N_RB_DL, 0, 0);
7395 7396 7397 7398 7399
      break;
    }


    if (rballoc > RIV_max) {
7400 7401 7402 7403
      LOG_E(PHY,"frame %d, subframe %d, rnti %x, format %d: FATAL ERROR: generate_ue_ulsch_params_from_dci, rb_alloc[%d] > RIV_max[%d]\n",
            proc->frame_rx, subframe, rnti, dci_format,rballoc,RIV_max);
      LOG_E(PHY,"Wrong DCI0 detection, do not transmit PUSCH for HARQID: %d\n",harq_pid);
      ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 0;
7404 7405 7406 7407 7408 7409
      return(-1);
    }


    // indicate that this process is to be serviced in subframe n+4
    if ((rnti >= cba_rnti) && (rnti < p_rnti))
7410
      ulsch->harq_processes[harq_pid]->subframe_cba_scheduling_flag = 1; //+=1 this indicates the number of dci / cba group: not supported in the data struct
7411
    else
7412 7413 7414 7415 7416
    {
        ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
        //LOG_I(PHY,"[HARQ-UL harqId: %d] DCI0 ==> subframe_scheduling_flag = %d round: %d\n", harq_pid, ulsch->harq_processes[harq_pid]->subframe_scheduling_flag, ulsch->harq_processes[harq_pid]->round);

    }
7417

7418
    ulsch->harq_processes[harq_pid]->TPC                                   = TPC;
7419 7420
    ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT[rballoc];
    ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT[rballoc];
7421

7422
    if (ue->ul_power_control_dedicated[eNB_id].accumulationEnabled == 1) {
7423
      LOG_D(PHY,"[UE %d][PUSCH %d] Frame %d subframe %d: f_pusch (ACC) %d, adjusting by %d (TPC %d)\n",
7424
            ue->Mod_id,harq_pid,proc->frame_rx,subframe,ulsch->f_pusch,
7425 7426 7427
            delta_PUSCH_acc[ue->ulsch[eNB_id]->harq_processes[harq_pid]->TPC],
            ue->ulsch[eNB_id]->harq_processes[harq_pid]->TPC);
      ulsch->f_pusch += delta_PUSCH_acc[ue->ulsch[eNB_id]->harq_processes[harq_pid]->TPC];
7428
    } else {
7429
      LOG_D(PHY,"[UE %d][PUSCH %d] Frame %d subframe %d: f_pusch (ABS) %d, adjusting to %d (TPC %d)\n",
7430
            ue->Mod_id,harq_pid,proc->frame_rx,subframe,ulsch->f_pusch,
7431 7432 7433
            delta_PUSCH_abs[ue->ulsch[eNB_id]->harq_processes[harq_pid]->TPC],
            ue->ulsch[eNB_id]->harq_processes[harq_pid]->TPC);
      ulsch->f_pusch = delta_PUSCH_abs[ue->ulsch[eNB_id]->harq_processes[harq_pid]->TPC];
7434
    }
7435

7436 7437 7438
    if (ulsch->harq_processes[harq_pid]->first_tx==1) {
      //      ulsch->harq_processes[harq_pid]->Ndi                                   = 1;
      ulsch->harq_processes[harq_pid]->first_tx=0;
7439
      ulsch->harq_processes[harq_pid]->DCINdi= ndi;
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Raymond Knopp committed
7440
      ulsch->harq_processes[harq_pid]->round = 0;
7441
    } else {
7442
      if (ulsch->harq_processes[harq_pid]->DCINdi!=ndi) { // new SDU opportunity
7443 7444 7445 7446 7447
        //  ulsch->harq_processes[harq_pid]->Ndi = 1;
        ulsch->harq_processes[harq_pid]->DCINdi= ndi;
        ulsch->harq_processes[harq_pid]->round = 0;
      } else {
        //  ulsch->harq_processes[harq_pid]->Ndi = 0;
7448 7449 7450 7451 7452 7453 7454
        //ulsch->harq_processes[harq_pid]->round++;  // This is done in phich RX

        //#ifdef DEBUG_PHICH
        //LOG_I(PHY,"[UE  %d][PUSCH %d] Frame %d subframe %d Adaptative Retrans, NDI not toggled => Nack. maxHARQ_Tx %d \n",
        //      ue->Mod_id,harq_pid,
        //      proc->frame_rx,
        //      subframe,
7455
        //      ulsch->Mlimit);
7456
        //#endif
7457
/*
7458
        if (ulsch->harq_processes[harq_pid]->round > 0) // NACK detected on phich
7459
        {
7460
            // ulsch->harq_processes[harq_pid]->round++; already done on phich_rx
7461
            // ulsch->harq_processes[harq_pid] = ulsch->harq_processes[8];
7462 7463
            // LOG_I(PHY,"          Adaptative retransmission - copy temporary harq Process to current harq process. [harqId %d round %d] \n",harq_pid, ulsch->harq_processes[8]->round);

7464
            if (ulsch->harq_processes[harq_pid]->round >= ulsch->Mlimit) //UE_mac_inst[eNB_id].scheduling_info.maxHARQ_Tx)
7465 7466 7467 7468 7469 7470 7471 7472 7473 7474 7475 7476 7477 7478 7479 7480 7481
            {
                ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 0;
                ulsch->harq_processes[harq_pid]->round  = 0;
                ulsch->harq_processes[harq_pid]->status = IDLE;
                //LOG_I(PHY,"          PUSCH MAX Retransmission acheived ==> flush harq buff (%d) \n",harq_pid);
                //LOG_I(PHY,"          [HARQ-UL harqId: %d] Adaptative retransmission NACK MAX RETRANS(%d) ==> subframe_scheduling_flag = %d round: %d\n", harq_pid, UE_mac_inst[eNB_id].scheduling_info.maxHARQ_Tx, ulsch->harq_processes[harq_pid]->subframe_scheduling_flag, ulsch->harq_processes[harq_pid]->round);
            }
            else
            {
                // ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
                uint8_t rv_table[4] = {0, 2, 3, 1};
                ulsch->harq_processes[harq_pid]->rvidx = rv_table[ulsch->harq_processes[harq_pid]->round&3];
                ulsch->O_RI = 0;
                ulsch->O    = 0;
                ulsch->uci_format = HLC_subband_cqi_nopmi;
                //LOG_I(PHY,"          [HARQ-UL harqId: %d] Adaptative retransmission NACK ==> subframe_scheduling_flag = %d round: %d\n", harq_pid, ulsch->harq_processes[harq_pid]->subframe_scheduling_flag,ulsch->harq_processes[harq_pid]->round);
            }
7482
        }
7483
*/
7484 7485
      }
    }
7486 7487

    ulsch->harq_processes[harq_pid]->n_DMRS                                = cshift;
7488 7489

    //printf("nb_rb %d, first_rb %d (RIV %d)\n",ulsch->harq_processes[harq_pid]->nb_rb,ulsch->harq_processes[harq_pid]->first_rb,rballoc);
7490
    if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
7491 7492 7493 7494
      // ulsch->cba_rnti[0]=rnti;
    } else {
      ulsch->rnti = rnti;
    }
7495

7496
    //    printf("[PHY][UE] DCI format 0: harq_pid %d nb_rb %d, rballoc %d\n",harq_pid,ulsch->harq_processes[harq_pid]->nb_rb,
7497
    //     ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->rballoc);
7498 7499 7500 7501 7502 7503 7504 7505 7506 7507 7508 7509 7510 7511 7512 7513 7514 7515 7516 7517 7518 7519 7520 7521 7522 7523 7524 7525 7526 7527 7528 7529 7530 7531 7532
    //Mapping of cyclic shift field in DCI format0 to n_DMRS2 (3GPP 36.211, Table 5.5.2.1.1-1)
    if(cshift == 0)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 0;
    else if(cshift == 1)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 6;
    else if(cshift == 2)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 3;
    else if(cshift == 3)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 4;
    else if(cshift == 4)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 2;
    else if(cshift == 5)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 8;
    else if(cshift == 6)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 10;
    else if(cshift == 7)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 9;


    //reserved for cooperative communication
    /*
      if(ulsch->n_DMRS2 == 6)
      ulsch->cooperation_flag = 2;
      else
      ulsch->cooperation_flag = 0;
    */

    if ((ulsch->harq_processes[harq_pid]->nb_rb>0) && (ulsch->harq_processes[harq_pid]->nb_rb < 25))
      ulsch->power_offset = ue_power_offsets[ulsch->harq_processes[harq_pid]->nb_rb-1];

    //    if (ulsch->harq_processes[harq_pid]->Ndi == 1)
    //    ulsch->harq_processes[harq_pid]->status = ACTIVE;


    if (cqi_req == 1) {
7533 7534 7535 7536 7537 7538 7539 7540 7541 7542

      if( (AntennaInfoDedicated__transmissionMode_tm3 == transmission_mode) || (AntennaInfoDedicated__transmissionMode_tm4 == transmission_mode) )
      {
          ulsch->O_RI = 1;
      }
      else
      {
          ulsch->O_RI = 0;
      }
      //ulsch->O_RI = 0; //we only support 2 antenna ports, so this is always 1 according to 3GPP 36.213 Table
7543 7544 7545

      switch(transmission_mode) {
        // The aperiodic CQI reporting mode is fixed for every transmission mode instead of being configured by higher layer signaling
7546
      case 1:
7547
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
7548
          switch (ue->frame_parms.N_RB_DL) {
7549 7550 7551 7552 7553 7554 7555 7556 7557 7558 7559 7560 7561 7562 7563 7564 7565 7566 7567 7568
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
          ulsch->o_RI[0]                             = 0;
        } else  if(meas->rank[eNB_id] == 0) {
7569
          switch (ue->frame_parms.N_RB_DL) {
7570 7571 7572 7573 7574 7575 7576 7577 7578 7579 7580 7581 7582 7583 7584 7585 7586 7587 7588 7589
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_nopmi;
          ulsch->o_RI[0]                             = 0;
        } else {
7590
          switch (ue->frame_parms.N_RB_DL) {
7591 7592 7593 7594 7595 7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611 7612 7613
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_nopmi;
          ulsch->o_RI[0]                             = 1;
        }

        break;

7614
      case 2:
7615
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
7616
          switch (ue->frame_parms.N_RB_DL) {
7617 7618 7619 7620 7621 7622 7623 7624 7625 7626 7627 7628 7629 7630 7631 7632 7633 7634 7635 7636
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
          ulsch->o_RI[0]                             = 0;
        } else if(meas->rank[eNB_id] == 0) {
7637
          switch (ue->frame_parms.N_RB_DL) {
7638 7639 7640 7641 7642 7643 7644 7645 7646 7647 7648 7649 7650 7651 7652 7653 7654 7655 7656 7657
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_nopmi;
          ulsch->o_RI[0]                             = 0;
        } else {
7658
          switch (ue->frame_parms.N_RB_DL) {
7659 7660 7661 7662 7663 7664 7665 7666 7667 7668 7669 7670 7671 7672 7673 7674 7675 7676 7677 7678 7679 7680 7681
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_nopmi;
          ulsch->o_RI[0]                             = 1;
        }

        break;

7682
      case 3:
7683
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
7684
          switch (ue->frame_parms.N_RB_DL) {
7685 7686 7687 7688 7689 7690 7691 7692 7693 7694 7695 7696 7697 7698 7699 7700 7701 7702 7703 7704
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
          ulsch->o_RI[0]                             = 0;
        } else if(meas->rank[eNB_id] == 0) {
7705
          switch (ue->frame_parms.N_RB_DL) {
7706 7707 7708 7709 7710 7711 7712 7713 7714 7715 7716 7717 7718 7719 7720 7721 7722 7723 7724 7725
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_nopmi;
          ulsch->o_RI[0]                             = 0;
        } else {
7726
          switch (ue->frame_parms.N_RB_DL) {
7727 7728 7729 7730 7731 7732 7733 7734 7735 7736 7737 7738 7739 7740 7741 7742 7743 7744 7745 7746 7747 7748 7749
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_nopmi;
          ulsch->o_RI[0]                             = 1;
        }

        break;

7750
      case 4:
7751
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
7752
          switch (ue->frame_parms.N_RB_DL) {
7753 7754 7755 7756 7757 7758 7759 7760 7761 7762 7763 7764 7765 7766 7767 7768 7769 7770 7771 7772
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
          ulsch->o_RI[0]                             = 0;
        } else if(meas->rank[eNB_id] == 0) {
7773
          switch (ue->frame_parms.N_RB_DL) {
7774 7775 7776 7777 7778 7779 7780 7781 7782 7783 7784 7785 7786 7787 7788 7789 7790 7791 7792 7793
          case 6:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_20MHz;
            break;
          }

          ulsch->uci_format                          = wideband_cqi_rank1_2A;
          ulsch->o_RI[0]                             = 0;
        } else {
7794
          switch (ue->frame_parms.N_RB_DL) {
7795 7796 7797 7798 7799 7800 7801 7802 7803 7804 7805 7806 7807 7808 7809 7810 7811 7812 7813 7814 7815 7816 7817
          case 6:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_20MHz;
            break;
          }

          ulsch->uci_format                          = wideband_cqi_rank2_2A;
          ulsch->o_RI[0]                             = 1;
        }

        break;

7818
      case 5:
7819
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
7820
          switch (ue->frame_parms.N_RB_DL) {
7821 7822 7823 7824 7825 7826 7827 7828 7829 7830 7831 7832 7833 7834 7835 7836 7837 7838 7839 7840
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
          ulsch->o_RI[0]                             = 0;
        } else if(meas->rank[eNB_id] == 0) {
7841
          switch (ue->frame_parms.N_RB_DL) {
7842 7843 7844 7845 7846 7847 7848 7849 7850 7851 7852 7853 7854 7855 7856 7857 7858 7859 7860 7861
          case 6:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_20MHz;
            break;
          }

          ulsch->uci_format                          = wideband_cqi_rank1_2A;
          ulsch->o_RI[0]                             = 0;
        } else {
7862
          switch (ue->frame_parms.N_RB_DL) {
7863 7864 7865 7866 7867 7868 7869 7870 7871 7872 7873 7874 7875 7876 7877 7878 7879 7880 7881 7882 7883 7884 7885
          case 6:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_20MHz;
            break;
          }

          ulsch->uci_format                          = wideband_cqi_rank2_2A;
          ulsch->o_RI[0]                             = 1;
        }

        break;

7886
      case 6:
7887
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
7888
          switch (ue->frame_parms.N_RB_DL) {
7889 7890 7891 7892 7893 7894 7895 7896 7897 7898 7899 7900 7901 7902 7903 7904 7905 7906 7907 7908
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
          ulsch->o_RI[0]                             = 0;
        } else if(meas->rank[eNB_id] == 0) {
7909
          switch (ue->frame_parms.N_RB_DL) {
7910 7911 7912 7913 7914 7915 7916 7917 7918 7919 7920 7921 7922 7923 7924 7925 7926 7927 7928 7929
          case 6:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_20MHz;
            break;
          }

          ulsch->uci_format                          = wideband_cqi_rank1_2A;
          ulsch->o_RI[0]                             = 0;
        } else {
7930
          switch (ue->frame_parms.N_RB_DL) {
7931 7932 7933 7934 7935 7936 7937 7938 7939 7940 7941 7942 7943 7944 7945 7946 7947 7948 7949 7950 7951 7952 7953
          case 6:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_20MHz;
            break;
          }

          ulsch->uci_format                          = wideband_cqi_rank2_2A;
          ulsch->o_RI[0]                             = 1;
        }

        break;

7954
      case 7:
7955
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
7956
          switch (ue->frame_parms.N_RB_DL) {
7957 7958 7959 7960 7961 7962 7963 7964 7965 7966 7967 7968 7969 7970 7971 7972 7973 7974 7975 7976
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
          ulsch->o_RI[0]                             = 0;
        } else if(meas->rank[eNB_id] == 0) {
7977
          switch (ue->frame_parms.N_RB_DL) {
7978 7979 7980 7981 7982 7983 7984 7985 7986 7987 7988 7989 7990 7991 7992 7993 7994 7995 7996 7997
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_nopmi;
          ulsch->o_RI[0]                             = 0;
        } else {
7998
          switch (ue->frame_parms.N_RB_DL) {
7999 8000 8001 8002 8003 8004 8005 8006 8007 8008 8009 8010 8011 8012 8013 8014 8015 8016 8017 8018 8019 8020 8021
          case 6:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->uci_format                          = HLC_subband_cqi_nopmi;
          ulsch->o_RI[0]                             = 1;
        }

        break;

8022
      default:
8023 8024
        LOG_E(PHY,"Incorrect Transmission Mode \n");
        break;
8025
      }
8026
    } else {
8027 8028 8029 8030
      ulsch->O_RI = 0;
      ulsch->O                                   = 0;
      ulsch->uci_format                          = HLC_subband_cqi_nopmi;
    }
8031

8032
    print_CQI(ulsch->o,ulsch->uci_format,eNB_id,ue->frame_parms.N_RB_DL);
8033

8034
    ulsch->bundling = 1-AckNackFBMode;
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8035 8036

    if (frame_parms->frame_type == FDD) {
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8037 8038
      //int dl_subframe = (subframe<4) ? (subframe+6) : (subframe-4);
      int dl_subframe = subframe;
8039

8040
      if (ue->dlsch[ue->current_thread_id[subframe]][eNB_id][0]->harq_ack[dl_subframe].send_harq_status>0) { // we have downlink transmission
8041 8042 8043
        ulsch->harq_processes[harq_pid]->O_ACK = 1;
      } else {
        ulsch->harq_processes[harq_pid]->O_ACK = 0;
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8044
      }
8045
      /*LOG_I(PHY,"DCI 0 Processing: dl_subframe %d send_harq_status Odd %d send_harq_status Even %d harq_pid %d O_ACK %d\n", dl_subframe,
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8046 8047 8048
              ue->dlsch[0][eNB_id][0]->harq_ack[dl_subframe].send_harq_status,
              ue->dlsch[1][eNB_id][0]->harq_ack[dl_subframe].send_harq_status,
              harq_pid,
8049
              ulsch->harq_processes[harq_pid]->O_ACK);*/
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8050

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8051 8052
    } else {
      if (ulsch->bundling)
8053
        ulsch->harq_processes[harq_pid]->O_ACK = (dai == 3)? 0 : 1;
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8054
      else
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8055
        ulsch->harq_processes[harq_pid]->O_ACK = (dai >= 2)? 2 : (dai+1)&3; //(dai+1)&3;
8056

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8057 8058
      //      ulsch->harq_processes[harq_pid]->V_UL_DAI = dai+1;
    }
8059

8060 8061
    dlsch[0]->harq_ack[subframe].vDAI_UL = dai+1;

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8062

8063
    LOG_D(PHY, "[PUSCH %d] Format0 DCI %s, CQI_req=%d, cshift=%d, TPC=%d, DAI=%d, vDAI_UL[sf#%d]=%d, NDI=%d, MCS=%d, RBalloc=%d, first_rb=%d, harq_pid=%d, nb_rb=%d, subframe_scheduling_flag=%d"
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8064
            "   ulsch->bundling %d, O_ACK %d \n",
8065 8066
        harq_pid,
        (frame_parms->frame_type == TDD? "TDD" : "FDD"),
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8067 8068 8069 8070
        cqi_req, cshift, TPC, dai, subframe, dlsch[0]->harq_ack[subframe].vDAI_UL, ndi, mcs, rballoc,
        ulsch->harq_processes[harq_pid]->first_rb, harq_pid, ulsch->harq_processes[harq_pid]->nb_rb,
        ulsch->harq_processes[harq_pid]->subframe_scheduling_flag,
        ulsch->bundling,
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        ulsch->harq_processes[harq_pid]->O_ACK);

8073 8074 8075
    LOG_D(PHY,"Setting beta_offset_cqi_times8 to %d, index %d\n",
	  beta_cqi[ue->pusch_config_dedicated[eNB_id].betaOffset_CQI_Index],
	  ue->pusch_config_dedicated[eNB_id].betaOffset_CQI_Index);
8076

8077 8078 8079
    ulsch->beta_offset_cqi_times8                = beta_cqi[ue->pusch_config_dedicated[eNB_id].betaOffset_CQI_Index];//18;
    ulsch->beta_offset_ri_times8                 = beta_ri[ue->pusch_config_dedicated[eNB_id].betaOffset_RI_Index];//10;
    ulsch->beta_offset_harqack_times8            = beta_ack[ue->pusch_config_dedicated[eNB_id].betaOffset_ACK_Index];//16;
8080 8081 8082 8083

    ulsch->Nsymb_pusch                             = 12-(frame_parms->Ncp<<1)-(use_srs==0?0:1);
    ulsch->srs_active                              = use_srs;

8084 8085 8086 8087
    if ((rnti >= cba_rnti) && (rnti < p_rnti))
      ulsch->harq_processes[harq_pid]->status = CBA_ACTIVE;
    else
      ulsch->harq_processes[harq_pid]->status = ACTIVE;
8088

8089
    ulsch->harq_processes[harq_pid]->rvidx = 0;
8090

8091 8092 8093 8094
    //      ulsch->harq_processes[harq_pid]->calibration_flag =0;
    if (mcs < 29) {
      ulsch->harq_processes[harq_pid]->mcs = mcs;
      // ulsch->harq_processes[harq_pid]->round = 0;
8095
    } else {
8096 8097 8098 8099 8100 8101 8102
      ulsch->harq_processes[harq_pid]->rvidx = mcs - 28;
      if (ulsch->harq_processes[harq_pid]->round == 0) {
        LOG_W(PHY,"PUSCH::mcs = %d and DCI0::mcs(%d) > 28 and round == %d\n", ulsch->harq_processes[harq_pid]->mcs, mcs, ulsch->harq_processes[harq_pid]->round);
      } else {
        LOG_D(PHY,"PUSCH::mcs = %d and DCI0::mcs(%d) > 28 and round == %d\n", ulsch->harq_processes[harq_pid]->mcs, mcs, ulsch->harq_processes[harq_pid]->round);
      }
      //LOG_E(PHY,"Fatal: mcs(%d) > 28!!! and round == 0\n", mcs);
8103
    }
8104
    ulsch->harq_processes[harq_pid]->TBS = TBStable[get_I_TBS_UL(ulsch->harq_processes[harq_pid]->mcs)][ulsch->harq_processes[harq_pid]->nb_rb-1];
8105

8106 8107 8108 8109 8110 8111 8112 8113 8114 8115 8116 8117 8118 8119
    /*
       else if (ulsch->harq_processes[harq_pid]->mcs == 29) {
       ulsch->harq_processes[harq_pid]->mcs = 4;
       ulsch->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS_UL(ulsch->harq_processes[harq_pid]->mcs)][ulsch->harq_processes[harq_pid]->nb_rb-1];
    // ulsch->harq_processes[harq_pid]->calibration_flag =1;
    // printf("Auto-Calibration (UE): mcs %d, TBS %d, nb_rb %d\n",ulsch->harq_processes[harq_pid]->mcs,ulsch->harq_processes[harq_pid]->TBS,ulsch->harq_processes[harq_pid]->nb_rb);
    }*/
    ulsch->harq_processes[harq_pid]->Msc_initial   = 12*ulsch->harq_processes[harq_pid]->nb_rb;
    ulsch->harq_processes[harq_pid]->Nsymb_initial = ulsch->Nsymb_pusch;

    // a Ndi=1 automatically acknowledges previous PUSCH transmission
    if (ue->ulsch_Msg3_active[eNB_id] == 1)
      ue->ulsch_Msg3_active[eNB_id] = 0;

8120
    LOG_D(PHY,"[UE %d][PUSCH %d] Frame %d, subframe %d : Programming PUSCH with n_DMRS2 %d (cshift %d), nb_rb %d, first_rb %d, mcs %d, round %d, rv %d, ulsch_ue_Msg3_active %d, cqi_req %d => O %d\n",
8121 8122
        ue->Mod_id,harq_pid,
        proc->frame_rx,subframe,ulsch->harq_processes[harq_pid]->n_DMRS2,cshift,ulsch->harq_processes[harq_pid]->nb_rb,ulsch->harq_processes[harq_pid]->first_rb,
8123
	  ulsch->harq_processes[harq_pid]->mcs,ulsch->harq_processes[harq_pid]->round,ulsch->harq_processes[harq_pid]->rvidx, ue->ulsch_Msg3_active[eNB_id],cqi_req,ulsch->O);
8124 8125

  // ulsch->n_DMRS2 = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
8126

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8127 8128
#ifdef UE_DEBUG_TRACE

8129
    LOG_D(PHY,"Format 0 DCI : ulsch (ue): AbsSubframe %d.%d\n",proc->frame_rx%1024,subframe);
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8130 8131 8132 8133 8134 8135 8136
    LOG_D(PHY,"Format 0 DCI : ulsch (ue): NBRB        %d\n",ulsch->harq_processes[harq_pid]->nb_rb);
    LOG_D(PHY,"Format 0 DCI :ulsch (ue): first_rb    %d\n",ulsch->harq_processes[harq_pid]->first_rb);
    LOG_D(PHY,"Format 0 DCI :ulsch (ue): rballoc     %d\n",rballoc);
    LOG_D(PHY,"Format 0 DCI :ulsch (ue): harq_pid    %d\n",harq_pid);
    LOG_D(PHY,"Format 0 DCI :ulsch (ue): first_tx       %d\n",ulsch->harq_processes[harq_pid]->first_tx);
    LOG_D(PHY,"Format 0 DCI :ulsch (ue): DCINdi       %d\n",ulsch->harq_processes[harq_pid]->DCINdi);
    LOG_D(PHY,"Format 0 DCI :ulsch (ue): round       %d\n",ulsch->harq_processes[harq_pid]->round);
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8137
    //LOG_I(PHY,"Format 0 DCI :ulsch (ue): TBS         %d\n",ulsch->harq_processes[harq_pid]->TBS);
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8138
    LOG_D(PHY,"Format 0 DCI :ulsch (ue): mcs         %d\n",ulsch->harq_processes[harq_pid]->mcs);
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8139 8140
    //LOG_I(PHY,"Format 0 DCI :ulsch (ue): O           %d\n",ulsch->O);
    //LOG_I(PHY,"Format 0 DCI :ulsch (ue): cqiReq      %d\n",cqi_req);
8141
    //if (frame_parms->frame_type == TDD)
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8142
    //  LOG_I(PHY,"Format 0 DCI :ulsch (ue): O_ACK/DAI   %d/%d\n",ulsch->harq_processes[harq_pid]->O_ACK,dai);
8143
    //else
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8144
    //  LOG_I(PHY,"Format 0 DCI :ulsch (ue): O_ACK       %d\n",ulsch->harq_processes[harq_pid]->O_ACK);
8145

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8146 8147 8148
    LOG_D(PHY,"Format 0 DCI :ulsch (ue): Nsymb_pusch   %d\n",ulsch->Nsymb_pusch);
    LOG_D(PHY,"Format 0 DCI :ulsch (ue): cshift        %d\n",ulsch->harq_processes[harq_pid]->n_DMRS2);
    LOG_D(PHY,"Format 0 DCI :ulsch (ue): phich status  %d\n",ulsch->harq_processes[harq_pid]->status);
8149 8150
#else
    UNUSED_VARIABLE(dai);
8151 8152
#endif
    return(0);
8153
  } else {
8154
    LOG_E(PHY,"frame %d, subframe %d: FATAL ERROR, generate_ue_ulsch_params_from_dci, Illegal dci_format %d\n",
8155
          proc->frame_rx, subframe,dci_format);
8156 8157 8158 8159 8160
    return(-1);
  }

}

8161
/*
8162
int generate_eNB_ulsch_params_from_dci(PHY_VARS_eNB *eNB,
8163 8164
                                       eNB_rxtx_proc_t *proc,
                                       void *dci_pdu,
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                                       uint16_t rnti,
                                       DCI_format_t dci_format,
                                       uint8_t UE_id,
                                       uint16_t si_rnti,
                                       uint16_t ra_rnti,
                                       uint16_t p_rnti,
                                       uint16_t cba_rnti,
                                       uint8_t use_srs)
{
8174 8175 8176

  uint8_t harq_pid;
  uint32_t rb_alloc;
8177 8178 8179 8180
  uint8_t transmission_mode=eNB->transmission_mode[UE_id];
  ANFBmode_t AckNackFBMode = eNB->pucch_config_dedicated[UE_id].tdd_AckNackFeedbackMode;
  LTE_eNB_ULSCH_t *ulsch=eNB->ulsch[UE_id];
  LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms;
8181
  int subframe = proc->subframe_tx;
8182

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8183 8184 8185 8186 8187 8188 8189
  uint32_t cqi_req = 0;
  uint32_t dai = 0;
  uint32_t cshift = 0;
  uint32_t TPC = 0;
  uint32_t mcs = 0;
  uint32_t rballoc = UINT32_MAX;
  uint32_t RIV_max = 0;
8190 8191 8192
  //  uint32_t hopping;
  //  uint32_t type;

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8193
#ifdef DEBUG_DCI
8194
  printf("filling eNB ulsch params for rnti %x, dci format %d, dci %x, subframe %d\n",
8195
        rnti,dci_format,*(uint32_t*)dci_pdu,subframe);
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8196
#endif
8197 8198 8199

  if (dci_format == format0) {

8200 8201
    harq_pid = subframe2harq_pid(frame_parms,
                                 pdcch_alloc2ul_frame(frame_parms,
8202 8203
                                                      proc->frame_tx,
                                                      subframe),
8204
                                 pdcch_alloc2ul_subframe(frame_parms,subframe));
8205 8206 8207
    switch (frame_parms->N_RB_DL) {
    case 6:
      if (frame_parms->frame_type == TDD) {
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        cqi_req = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
        dai     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->dai;
        cshift  = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
        mcs     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
8214
        //  hopping = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->hopping=hopping;
8215 8216 8217 8218 8219 8220 8221
        //  type    = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->type;
      } else {
        cqi_req = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->cqi_req;
        cshift  = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->TPC;
        mcs     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->rballoc;
8222
        //  hopping = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->hopping=hopping;
8223
        //  type    = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->type;
8224
      }
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8225
      
8226 8227 8228 8229 8230
      RIV_max = RIV_max6;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT6[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT6[rballoc];

      break;
8231

8232 8233
    case 25:
      if (frame_parms->frame_type == TDD) {
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        cqi_req = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
        dai     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->dai;
        cshift  = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
        mcs     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
        //  hopping = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->hopping;
        //  type    = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->type;
      } else {
        cqi_req = ((DCI0_5MHz_FDD_t *)dci_pdu)->cqi_req;
        cshift  = ((DCI0_5MHz_FDD_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_5MHz_FDD_t *)dci_pdu)->TPC;
        mcs     = ((DCI0_5MHz_FDD_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_5MHz_FDD_t *)dci_pdu)->rballoc;
        //  hopping = ((DCI0_5MHz_FDD_t *)dci_pdu)->hopping;
        //  type    = ((DCI0_5MHz_FDD_t *)dci_pdu)->type;
8250
      }
8251

8252 8253 8254 8255 8256
      RIV_max = RIV_max25;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT25[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT25[rballoc];

      break;
8257

8258 8259
    case 50:
      if (frame_parms->frame_type == TDD) {
8260 8261 8262 8263 8264 8265 8266 8267 8268 8269 8270 8271 8272 8273 8274 8275
        cqi_req = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
        dai     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->dai;
        cshift  = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->TPC;
        mcs     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
        //  hopping = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->hopping;
        //  type    = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->type;
      } else {
        cqi_req = ((DCI0_10MHz_FDD_t *)dci_pdu)->cqi_req;
        cshift  = ((DCI0_10MHz_FDD_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_10MHz_FDD_t *)dci_pdu)->TPC;
        mcs     = ((DCI0_10MHz_FDD_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_10MHz_FDD_t *)dci_pdu)->rballoc;
        //  hopping = ((DCI0_10MHz_FDD_t *)dci_pdu)->hopping;
        //  type    = ((DCI0_10MHz_FDD_t *)dci_pdu)->type;
8276
      }
8277

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      RIV_max = RIV_max50;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT50[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT50[rballoc];

      break;
8283

8284 8285
    case 100:
      if (frame_parms->frame_type == TDD) {
8286 8287 8288 8289 8290 8291 8292 8293 8294 8295 8296 8297 8298 8299 8300 8301
        cqi_req = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
        dai     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->dai;
        cshift  = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->TPC;
        mcs     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
        //  hopping = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->hopping;
        //  type    = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->type;
      } else {
        cqi_req = ((DCI0_20MHz_FDD_t *)dci_pdu)->cqi_req;
        cshift  = ((DCI0_20MHz_FDD_t *)dci_pdu)->cshift;
        TPC     = ((DCI0_20MHz_FDD_t *)dci_pdu)->TPC;
        mcs     = ((DCI0_20MHz_FDD_t *)dci_pdu)->mcs;
        rballoc = ((DCI0_20MHz_FDD_t *)dci_pdu)->rballoc;
        //  hopping = ((DCI0_20MHz_FDD_t *)dci_pdu)->hopping;
        //  type    = ((DCI0_20MHz_FDD_t *)dci_pdu)->type;
8302
      }
8303

8304 8305 8306 8307
      RIV_max = RIV_max100;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT100[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT100[rballoc];

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8308
      //printf("eNB: rb_alloc (20 MHz dci) %d\n",rballoc);
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8309 8310 8311 8312 8313
      break;

    default:
      LOG_E(PHY,"Invalid N_RB_DL %d\n", frame_parms->N_RB_DL);
      DevParam (frame_parms->N_RB_DL, 0, 0);
8314 8315
      break;
    }
8316

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8317

8318
    rb_alloc = rballoc;
8319 8320
    AssertFatal(rb_alloc>RIV_max,
		"Format 0: rb_alloc (%d) > RIV_max (%d)\n",rb_alloc,RIV_max);
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8321
#ifdef DEBUG_DCI
8322
    printf("generate_eNB_ulsch_params_from_dci: subframe %d, rnti %x,harq_pid %d,cqi_req %d\n",subframe,rnti,harq_pid,cqi_req);
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8323
#endif
8324 8325 8326 8327

    ulsch->harq_processes[harq_pid]->dci_alloc                             = 1;
    ulsch->harq_processes[harq_pid]->rar_alloc                             = 0;
    ulsch->harq_processes[harq_pid]->TPC                                   = TPC;
8328
    ulsch->harq_processes[harq_pid]->n_DMRS                                = cshift;
8329 8330 8331


    if (cqi_req == 1) {
8332 8333 8334 8335 8336 8337 8338
      // 36.213 7.2.1 (release 10) says:
      // "RI is only reported for transmission modes 3 and 4,
      // as well as transmission modes 8 and 9 with PMI/RI reporting"
      // This is for aperiodic reporting.
      // TODO: deal with TM 8&9 correctly when they are implemented.
      // TODO: deal with periodic reporting if we implement it.
      //
8339 8340 8341 8342
      if (transmission_mode == 3 || transmission_mode == 4)
        ulsch->harq_processes[harq_pid]->O_RI = 1; //we only support 2 antenna ports, so this is always 1 according to 3GPP 36.213 Table
      else
        ulsch->harq_processes[harq_pid]->O_RI = 0;
8343 8344 8345

      switch(transmission_mode) {
        // The aperiodic CQI reporting mode is fixed for every transmission mode instead of being configured by higher layer signaling
8346
      case 1:
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        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
          ulsch->harq_processes[harq_pid]->Or2                                   = 0;

          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_mcs_CBA;
        } else {
          ulsch->harq_processes[harq_pid]->Or2                                   = 0;

          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_nopmi;
        }

        break;

8395
      case 2:
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        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
          ulsch->harq_processes[harq_pid]->Or2                                   = 0;

          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_mcs_CBA;
        } else {
          ulsch->harq_processes[harq_pid]->Or2                                   = 0;

          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_nopmi;
        }

        break;

8444
      case 3:
8445 8446 8447 8448 8449 8450 8451 8452 8453 8454 8455 8456 8457 8458 8459 8460 8461 8462 8463 8464 8465 8466 8467 8468 8469 8470 8471 8472 8473 8474 8475 8476 8477 8478 8479 8480 8481 8482 8483 8484 8485 8486 8487 8488 8489 8490 8491 8492
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
          ulsch->harq_processes[harq_pid]->Or2                                   = 0;

          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_mcs_CBA;
        } else {
          ulsch->harq_processes[harq_pid]->Or2                                   = 0;

          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_nopmi;
        }

        break;

8493
      case 4:
8494 8495 8496 8497 8498 8499 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 8510 8511 8512 8513 8514 8515 8516 8517 8518 8519 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 8530 8531 8532 8533 8534 8535 8536 8537 8538 8539 8540 8541 8542 8543 8544
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
          ulsch->harq_processes[harq_pid]->Or2                                   = 0;

          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_mcs_CBA;
        } else {
          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_1_5MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_5MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_10MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_20MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_20MHz;
            break;

          }

          ulsch->harq_processes[harq_pid]->uci_format                          = wideband_cqi_rank1_2A;
        }

        break;

8545
      case 5:
8546 8547 8548 8549 8550 8551 8552 8553 8554 8555 8556 8557 8558 8559 8560 8561 8562 8563 8564 8565 8566 8567 8568 8569 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 8590 8591 8592 8593 8594 8595
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
          ulsch->harq_processes[harq_pid]->Or2                                   = 0;

          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_mcs_CBA;
        } else {
          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_1_5MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_5MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_10MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_20MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                          = wideband_cqi_rank1_2A;
        }

        break;

8596
      case 6:
8597 8598 8599 8600 8601 8602 8603 8604 8605 8606 8607 8608 8609 8610 8611 8612 8613 8614 8615 8616 8617 8618 8619 8620 8621 8622 8623 8624 8625 8626 8627 8628 8629 8630 8631 8632 8633 8634 8635 8636 8637 8638 8639 8640 8641 8642 8643 8644 8645 8646
        if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
          ulsch->harq_processes[harq_pid]->Or2                                   = 0;

          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_mcs_CBA;
        } else {
          switch (frame_parms->N_RB_DL) {
          case 6:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_1_5MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_1_5MHz;
            break;

          case 25:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_5MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_5MHz;
            break;

          case 50:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_10MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_10MHz;
            break;

          case 100:
            ulsch->harq_processes[harq_pid]->Or2                                 = sizeof_wideband_cqi_rank2_2A_20MHz;
            ulsch->harq_processes[harq_pid]->Or1                                 = sizeof_wideband_cqi_rank1_2A_20MHz;
            break;
          }

          ulsch->harq_processes[harq_pid]->uci_format                          = wideband_cqi_rank1_2A;
        }

        break;

8647
      case 7:
8648 8649 8650 8651 8652 8653 8654 8655 8656 8657 8658 8659 8660 8661 8662 8663 8664 8665 8666 8667 8668 8669 8670
        ulsch->harq_processes[harq_pid]->Or2                                   = 0;

        switch (frame_parms->N_RB_DL) {
        case 6:
          ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_1_5MHz;
          break;

        case 25:
          ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
          break;

        case 50:
          ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_10MHz;
          break;

        case 100:
          ulsch->harq_processes[harq_pid]->Or1                                   = sizeof_HLC_subband_cqi_nopmi_20MHz;
          break;
        }

        ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_nopmi;
        break;

8671
      default:
8672 8673
        LOG_E(PHY,"Incorrect Transmission Mode \n");
        break;
8674
      }
8675
    } else {
8676
      ulsch->harq_processes[harq_pid]->O_RI = 0;
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8677
      ulsch->harq_processes[harq_pid]->Or2                                   = 0;
8678
      ulsch->harq_processes[harq_pid]->Or1                                   = 0;
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8679
      ulsch->harq_processes[harq_pid]->uci_format                            = HLC_subband_cqi_nopmi;
8680 8681
    }

8682 8683
    ulsch->bundling = 1-AckNackFBMode;

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8684 8685
    if (frame_parms->frame_type == FDD) {
      int dl_subframe = (subframe<4) ? (subframe+6) : (subframe-4);
8686

8687
      if (eNB->dlsch[UE_id][0]->subframe_tx[dl_subframe]>0) { // we have downlink transmission
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        ulsch->harq_processes[harq_pid]->O_ACK = 1;
      } else {
        ulsch->harq_processes[harq_pid]->O_ACK = 0;
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8691 8692 8693
      }
    } else {
      if (ulsch->bundling)
8694
        ulsch->harq_processes[harq_pid]->O_ACK = (dai == 3)? 0 : 1;
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8695
      else
8696 8697
        ulsch->harq_processes[harq_pid]->O_ACK = (dai+1)&3;

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8698 8699
      ulsch->harq_processes[harq_pid]->V_UL_DAI = dai+1;
    }
8700

8701 8702 8703
    ulsch->beta_offset_cqi_times8                = beta_cqi[eNB->pusch_config_dedicated[UE_id].betaOffset_CQI_Index];//18;
    ulsch->beta_offset_ri_times8                 = beta_ri[eNB->pusch_config_dedicated[UE_id].betaOffset_RI_Index];//10;
    ulsch->beta_offset_harqack_times8            = beta_ack[eNB->pusch_config_dedicated[UE_id].betaOffset_ACK_Index];//16;
8704

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8705 8706
    ulsch->harq_processes[harq_pid]->Nsymb_pusch                             = 12-(frame_parms->Ncp<<1)-(use_srs==0?0:1);
    ulsch->harq_processes[harq_pid]->srs_active                            = use_srs;
8707

8708 8709 8710 8711 8712 8713 8714 8715 8716 8717 8718 8719 8720 8721 8722 8723 8724 8725 8726 8727
    //Mapping of cyclic shift field in DCI format0 to n_DMRS2 (3GPP 36.211, Table 5.5.2.1.1-1)
    if(cshift == 0)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 0;
    else if(cshift == 1)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 6;
    else if(cshift == 2)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 3;
    else if(cshift == 3)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 4;
    else if(cshift == 4)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 2;
    else if(cshift == 5)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 8;
    else if(cshift == 6)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 10;
    else if(cshift == 7)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 9;


    LOG_D(PHY,"[eNB %d][PUSCH %d] Frame %d, subframe %d : Programming PUSCH with n_DMRS2 %d (cshift %d)\n",
8728
          eNB->Mod_id,harq_pid,proc->frame_tx,subframe,ulsch->harq_processes[harq_pid]->n_DMRS2,cshift);
8729 8730 8731



8732
    if (ulsch->harq_processes[harq_pid]->round == 0) {
8733
      if ((rnti >= cba_rnti) && (rnti < p_rnti))
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        ulsch->harq_processes[harq_pid]->status = CBA_ACTIVE;
      else
        ulsch->harq_processes[harq_pid]->status = ACTIVE;

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      ulsch->harq_processes[harq_pid]->rvidx = 0;
      ulsch->harq_processes[harq_pid]->mcs         = mcs;
      //      ulsch->harq_processes[harq_pid]->calibration_flag = 0;
      //if (ulsch->harq_processes[harq_pid]->mcs)
8742 8743 8744
      //
      //if (ulsch->harq_processes[harq_pid]->mcs == 29) {
      //ulsch->harq_processes[harq_pid]->mcs = 4;
8745 8746
      // ulsch->harq_processes[harq_pid]->calibration_flag = 1;
      // printf("Auto-Calibration (eNB): mcs %d, nb_rb %d\n",ulsch->harq_processes[harq_pid]->mcs,ulsch->harq_processes[harq_pid]->nb_rb);
8747 8748
      //}
      
8749
      ulsch->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS_UL(ulsch->harq_processes[harq_pid]->mcs)][ulsch->harq_processes[harq_pid]->nb_rb-1];
8750

8751
      ulsch->harq_processes[harq_pid]->Msc_initial   = 12*ulsch->harq_processes[harq_pid]->nb_rb;
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8752
      ulsch->harq_processes[harq_pid]->Nsymb_initial = ulsch->harq_processes[harq_pid]->Nsymb_pusch;
8753
      ulsch->harq_processes[harq_pid]->round = 0;
8754
    } else {
8755
      if (mcs>28)
8756
        ulsch->harq_processes[harq_pid]->rvidx = mcs - 28;
8757
      else {
8758 8759
        ulsch->harq_processes[harq_pid]->rvidx = 0;
        ulsch->harq_processes[harq_pid]->mcs = mcs;
8760
      }
8761

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      //      ulsch->harq_processes[harq_pid]->round++;
    }
8764 8765

    if ((rnti >= cba_rnti) && (rnti < p_rnti)) {
8766
      ulsch->cba_rnti[0] = rnti;
8767 8768
    } else {
      ulsch->rnti = rnti;
8769
    }
8770

8771 8772 8773
    //ulsch->n_DMRS2 = cshift;

#ifdef DEBUG_DCI
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    printf("ulsch (eNB): NBRB          %d\n",ulsch->harq_processes[harq_pid]->nb_rb);
    printf("ulsch (eNB): first_rb      %d\n",ulsch->harq_processes[harq_pid]->first_rb);
    printf("ulsch (eNB): harq_pid      %d\n",harq_pid);
    printf("ulsch (eNB): round         %d\n",ulsch->harq_processes[harq_pid]->round);
    printf("ulsch (eNB): TBS           %d\n",ulsch->harq_processes[harq_pid]->TBS);
    printf("ulsch (eNB): mcs           %d\n",ulsch->harq_processes[harq_pid]->mcs);
    printf("ulsch (eNB): Or1           %d\n",ulsch->harq_processes[harq_pid]->Or1);
    printf("ulsch (eNB): Nsymb_pusch   %d\n",ulsch->harq_processes[harq_pid]->Nsymb_pusch);
    printf("ulsch (eNB): cshift        %d\n",ulsch->harq_processes[harq_pid]->n_DMRS2);
8783 8784
#else
    UNUSED_VARIABLE(dai);
8785 8786
#endif
    return(0);
8787
  } else {
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    LOG_E(PHY,"generate_eNB_ulsch_params_from_dci, Illegal dci_format %d\n",dci_format);
    return(-1);
  }

}
8793
*/
8794

8795
double sinr_eff_cqi_calc(PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe)
8796
{
8797 8798 8799
  uint8_t transmission_mode = ue->transmission_mode[eNB_id];
  PHY_MEASUREMENTS *meas = &ue->measurements;
  LTE_DL_FRAME_PARMS *frame_parms =  &ue->frame_parms;
8800
  int32_t **dl_channel_est = ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_id];
8801
  double *s_dB;
8802 8803
  s_dB = ue->sinr_CQI_dB;
  //  LTE_UE_ULSCH_t *ulsch  = ue->ulsch[eNB_id];
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  //for the calculation of SINR_eff for CQI calculation
  int count,a_rx,a_tx;
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  double abs_channel=0;
  double channelx=0;
  double channely=0;
  double channelx_i=0;
  double channely_i=0;
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8811
  uint16_t q = quantize_subband_pmi(meas,eNB_id,7);
8812
  uint8_t qq;
8813 8814

  switch(transmission_mode) {
8815
  case 1:
8816
    for (count=0; count<frame_parms->N_RB_DL*12; count++) {
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8817
      for(a_tx=0; a_tx<frame_parms->nb_antenna_ports_eNB; a_tx++) {
8818 8819 8820 8821
        for (a_rx=0; a_rx<frame_parms->nb_antennas_rx; a_rx++) {
          s_dB[count] = 10*log10(pow(((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2],2) + pow(((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2],
                                 2)) - meas->n0_power_avg_dB;
        }
8822
      }
8823 8824
    }

8825
    break;
8826

8827
  case 2:
8828 8829 8830
    for (count=0; count<frame_parms->N_RB_DL*12; count++) {
      abs_channel=0;

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8831
      for(a_tx=0; a_tx<frame_parms->nb_antenna_ports_eNB; a_tx++) {
8832 8833 8834
        for (a_rx=0; a_rx<frame_parms->nb_antennas_rx; a_rx++) {
          abs_channel += (pow(((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2],2) + pow(((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2],2));
        }
8835
      }
8836 8837 8838 8839

      s_dB[count] = 10*log10(abs_channel/2) - meas->n0_power_avg_dB;
    }

8840
    break;
8841

8842
  case 5:
8843
    for (count=0; count<frame_parms->N_RB_DL*12; count++) {
8844 8845 8846 8847 8848
      channelx=0;
      channely=0;
      channelx_i=0;
      channely_i=0;
      qq = (q>>(((count/12)>>2)<<1))&3;
8849

8850
      //printf("pmi_alloc %d: rb %d, pmi %d\n",q,count/12,qq);
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8851
      for(a_tx=0; a_tx<frame_parms->nb_antenna_ports_eNB; a_tx++) {
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        for (a_rx=0; a_rx<frame_parms->nb_antennas_rx; a_rx++) {
          switch(qq) {
          case 0:
            if (channelx==0 || channely==0) {
              channelx = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channelx_i = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely_i = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            } else {
              channelx += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channelx_i -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely_i -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            }

            break;

          case 1:
            if (channelx==0 || channely==0) {
              channelx = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channelx_i = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely_i = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            } else {
              channelx -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channelx_i += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely_i += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            }

            break;

          case 2:
            if (channelx==0 || channely==0) {
              channelx = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channelx_i = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely_i = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            } else {
              channelx -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channely += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channelx_i += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channely_i -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
            }

            break;

          case 3:
            if (channelx==0 || channely==0) {
              channelx = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channelx_i = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely_i = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            } else {
              channelx += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channely -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channelx_i -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channely_i += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
            }

            break;

          default:
8915
            printf("Problem in SINR Calculation for TM5 \n");
8916 8917 8918 8919 8920
            break;
          }//switch(qq)
        }//a_rx
      }//a_tx

8921
      s_dB[count] =  10 * log10 ((pow(channelx,2) + pow(channely,2))/2) - 10 * log10 ((pow(channelx_i,2) + pow(channely_i,2))/2) - meas->n0_power_avg_dB;
8922
    }//count
8923

8924
    break;
8925

8926
  case 6:
8927
    for (count=0; count<frame_parms->N_RB_DL*12; count++) {
8928 8929 8930
      channelx=0;
      channely=0;
      qq = (q>>(((count/12)>>2)<<1))&3;
8931

8932
      //printf("pmi_alloc %d: rb %d, pmi %d\n",q,count/12,qq);
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8933
      for(a_tx=0; a_tx<frame_parms->nb_antenna_ports_eNB; a_tx++) {
8934 8935 8936 8937 8938 8939 8940 8941 8942 8943 8944 8945 8946 8947 8948 8949 8950 8951 8952 8953 8954 8955 8956 8957 8958 8959 8960 8961 8962 8963 8964 8965 8966 8967 8968 8969 8970 8971 8972 8973 8974 8975 8976 8977 8978 8979 8980
        for (a_rx=0; a_rx<frame_parms->nb_antennas_rx; a_rx++) {
          switch(qq) {
          case 0:
            if (channelx==0 || channely==0) {
              channelx = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            } else {
              channelx += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            }

            break;

          case 1:
            if (channelx==0 || channely==0) {
              channelx = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            } else {
              channelx -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            }

            break;

          case 2:
            if (channelx==0 || channely==0) {
              channelx = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            } else {
              channelx -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channely += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
            }

            break;

          case 3:
            if (channelx==0 || channely==0) {
              channelx = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
              channely = ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
            } else {
              channelx += ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
              channely -= ((int16_t *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
            }

            break;

          default:
8981
            printf("Problem in SINR Calculation for TM6 \n");
8982 8983 8984 8985 8986
            break;
          }//switch(qq)
        }//a_rx
      }//a_tx

8987
      s_dB[count] =  10 * log10 ((pow(channelx,2) + pow(channely,2))/2) - meas->n0_power_avg_dB;
8988
    }//count
8989

8990
    break;
8991

8992
  default:
8993
    printf("Problem in SINR Calculation for CQI \n");
8994
    break;
8995
  }
8996

8997
  int ii;
8998
  double sinr_eff = 0;
8999 9000 9001
  double sinr_eff_qpsk=0;
  double sinr_eff_qam16=0;
  double sinr_eff_qam64=0;
9002
  double x = 0;
9003 9004 9005 9006 9007 9008
  double I_qpsk=0;
  double I_qam16=0;
  double I_qam64=0;
  double I_qpsk_avg=0;
  double I_qam16_avg=0;
  double I_qam64_avg=0;
9009 9010 9011 9012 9013
  double qpsk_max=12.2;
  double qam16_max=19.2;
  double qam64_max=25.2;
  double sinr_min = -20;
  int offset=0;
9014 9015


9016
  for (offset = 0; offset <= 24; offset++) {
9017
    for(ii=0; ii<12; ii++) {
9018 9019
      //x is the sinr_dB in dB
      x = s_dB[(offset*12)+ii];
9020 9021 9022 9023 9024 9025 9026 9027 9028 9029 9030 9031 9032 9033 9034 9035 9036 9037 9038 9039 9040

      if(x<sinr_min) {
        I_qpsk +=0;
        I_qam16 +=0;
        I_qam64 +=0;
      } else {
        if(x>qpsk_max)
          I_qpsk += 1;
        else
          I_qpsk += (q_qpsk[0]*pow(x,7) + q_qpsk[1]*pow(x,6) + q_qpsk[2]*pow(x,5) + q_qpsk[3]*pow(x,4) + q_qpsk[4]*pow(x,3) + q_qpsk[5]*pow(x,2) + q_qpsk[6]*x + q_qpsk[7]);

        if(x>qam16_max)
          I_qam16 += 1;
        else
          I_qam16 += (q_qam16[0]*pow(x,7) + q_qam16[1]*pow(x,6) + q_qam16[2]*pow(x,5) + q_qam16[3]*pow(x,4) + q_qam16[4]*pow(x,3) + q_qam16[5]*pow(x,2) + q_qam16[6]*x + q_qam16[7]);

        if(x>qam64_max)
          I_qam64 += 1;
        else
          I_qam64 += (q_qam64[0]*pow(x,7) + q_qam64[1]*pow(x,6) + q_qam64[2]*pow(x,5) + q_qam64[3]*pow(x,4) + q_qam64[4]*pow(x,3) + q_qam64[5]*pow(x,2) + q_qam64[6]*x + q_qam64[7]);

9041 9042 9043
      }
    }
  }
9044 9045 9046 9047 9048 9049

  // averaging of accumulated MI
  I_qpsk_avg = I_qpsk/(12*frame_parms->N_RB_DL);
  I_qam16_avg = I_qam16/(12*frame_parms->N_RB_DL);
  I_qam64_avg = I_qam64/(12*frame_parms->N_RB_DL);

9050
  // I->SINR_effective Mapping
9051 9052 9053 9054 9055 9056 9057 9058 9059

  sinr_eff_qpsk = (p_qpsk[0]*pow(I_qpsk_avg,7) + p_qpsk[1]*pow(I_qpsk_avg,6) + p_qpsk[2]*pow(I_qpsk_avg,5) + p_qpsk[3]*pow(I_qpsk_avg,4) + p_qpsk[4]*pow(I_qpsk_avg,3) + p_qpsk[5]*pow(I_qpsk_avg,
                   2) + p_qpsk[6]*I_qpsk_avg + p_qpsk[7]);

  sinr_eff_qam16 = (p_qam16[0]*pow(I_qam16_avg,7) + p_qam16[1]*pow(I_qam16_avg,6) + p_qam16[2]*pow(I_qam16_avg,5) + p_qam16[3]*pow(I_qam16_avg,4) + p_qam16[4]*pow(I_qam16_avg,
                    3) + p_qam16[5]*pow(I_qam16_avg,2) + p_qam16[6]*I_qam16_avg + p_qam16[7]);

  sinr_eff_qam64 = (p_qam64[0]*pow(I_qam64_avg,7) + p_qam64[1]*pow(I_qam64_avg,6) + p_qam64[2]*pow(I_qam64_avg,5) + p_qam64[3]*pow(I_qam64_avg,4) + p_qam64[4]*pow(I_qam64_avg,
                    3) + p_qam64[5]*pow(I_qam64_avg,2) + p_qam64[6]*I_qam64_avg + p_qam64[7]);
9060
  sinr_eff = cmax3(sinr_eff_qpsk,sinr_eff_qam16,sinr_eff_qam64);
9061

9062
  //printf("SINR_Eff = %e\n",sinr_eff);
9063

9064 9065 9066 9067 9068
  return(sinr_eff);
}
//


9069

9070
#ifdef DEBUG_DLSCH_TOOLS
9071 9072
main()
{
9073 9074 9075 9076 9077 9078 9079 9080 9081

  int i;
  uint8_t rah;
  uint32_t rballoc;

  generate_RIV_tables();

  rah = 0;
  rballoc = 0x1fff;
9082
  printf("rballoc 0 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
9083 9084 9085
  rah = 1;

  rballoc = 0x1678;
9086
  printf("rballoc 1 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
9087 9088

  rballoc = 0xfffc;
9089
  printf("rballoc 1 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
9090
  rballoc = 0xfffd;
9091
  printf("rballoc 1 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
9092
  rballoc = 0xffff;
9093
  printf("rballoc 1 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
9094
  rballoc = 0xfffe;
9095
  printf("rballoc 1 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
9096 9097 9098 9099
}

#endif