Commit 0affd907 authored by Robert Schmidt's avatar Robert Schmidt

No dynamically alloced PUSCH, remove internal PDU

parent a6a7c7a3
dev 512-dataplane-bug-in-l2nfapi_nos1 FR2_NSA Fix_SA_SIB1 NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_2port_CSIRS NR_CSIRS_tomerge NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_F1C_F1U_extensions NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_RA NR_FR2_initsync_fixes NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_PUCCH_MultiUE NR_RA_cleanup NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS-USIM NR_SA_F1AP_5GRECORDS-wf-0623 NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_F1AP_dev NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs1 NR_SA_w5GCN_new_gtpu NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_UE_CONFIG_REQ_FIXES NR_UE_PUCCH_bugfixes NR_UE_SA NR_UE_dlsch_bugfix NR_UE_rework_test NR_UE_reworking_UCI_procedures NR_UL_SCFDMA_100MHz NR_UL_scheduler NR_Wireshark NR_beam_simulation NR_cleanup_PUCCH_resources NR_gNB_initial_MIB_fix NR_multiplexing_HARQ_CSI_PUCCH NR_phytest_bugfixes NR_reworking_UL_antennaports NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 PBCHNRTCFIX RFquality Saankhya_NRPRACH_HighSpeed Test_SA_5GREC add-dmrs-test add-ru-docker-image avxllr bandwidth-testing benetel_config_file_fix benetel_dpdk20 benetel_driver_uldl_pf_merge benetel_driver_update benetel_fixes bsr-fix bugfix-free-ra-process bugfix-nr-t-reordering bugfix-x2-SgNBAdditionRequest bugfix_gnb_rt_stats_html bupt-sa-merge ci-fix-module-ul-iperf ci-new-docker-pipeline ci-reduce-nb-vms ci-test ci_benetel_longrun_limits ci_benetel_test ci_fix_iperf_for_module ci_hotfix_module_ue_ip_address ci_improve_module_ctl ci_nsa_benetel ci_nsa_fixes ci_nsa_pipes_improve ci_nsa_test_integration_2021_wk19 ci_nsa_traces ci_nsa_uplink ci_phytest ci_quectel_support ci_sa_rfsim_test ci_solve_ul_for_module ci_test_5GREC ci_test_nsa_fix_quectel_nic ci_test_nsa_on_develop ci_test_ra_fr2 ci_testinfra_as_code ci_vm_resource_fix cleanup_softmodem_main debug-UL-5GRECORDS debug_UL_signal detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS-v3 develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts develop-SA-RA develop-SnT develop-aw2sori develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop-wf-du develop_stable disable_CSI_measrep docker-improvements-2021-april docker-no-cache-option dongzhanyi-zte-develop1 enhance-rfsim episys-merge episys/nsa_baseline episys/nsa_development fedora-gen-kernel-fix fft_bench_hotfix fix-check fix-compile fix-nr-pdcp-timer fix-nr-rlc-range-nack fix-physim-deploy fix-quectel fix-realtime fix-retransmission-rbg fix-x2-without-gnb fix_NR_DLUL_PF fix_NR_DLUL_PF_benchmark fix_coreset_dmrs_idx fix_do_ra_data fix_nr_ulsim fix_rb_corruption fix_reestablishment fixes-CE-RLC-PDU-size fixgtpu flexran-rtc-repo-is-public git-dashboard gnb-freerun-txru gnb-n300-fixes gnb-only-test gnb-realtime-hotfix gnb-realtime-quickfix gnb-threadpool hack-bch-no-sched-sf-0 hack-exit-gnb-when-no-enb-nsa integ-w13-test-rt-issue integration_2020_wk15 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 integration_2021_wk06 integration_2021_wk06_MR978 integration_2021_wk06_b integration_2021_wk06_c integration_2021_wk08 integration_2021_wk08_2 integration_2021_wk08_MR963 integration_2021_wk09 integration_2021_wk09_b integration_2021_wk10 integration_2021_wk10_b integration_2021_wk11 integration_2021_wk12 integration_2021_wk12_b integration_2021_wk13_a integration_2021_wk13_b integration_2021_wk13_b_fix_tdas integration_2021_wk13_b_fixed integration_2021_wk13_c integration_2021_wk14_a integration_2021_wk15_a integration_2021_wk16 integration_2021_wk17_a integration_2021_wk17_b integration_2021_wk18_a integration_2021_wk18_b integration_2021_wk19 integration_2021_wk20_a integration_2021_wk22 integration_2021_wk23 integration_2021_wk27 integration_w5GC_CBRA_test inter-RRU-final itti-enhancement ldpc_offload_t1 lte-ulsch-bugfix lte_uplink_improvement migrate-cpp-check-container migrate-vm-pipeline-to-bionic minor-fix-doc-basic-sim msg4_phy_0303_lfq multiple_ssb_sib1_bugfix nasmesh_kernel_5.8 new-gtpu nfapi_nr_arch_mod nfapi_nr_develop nfapi_nr_develop_new nr-bsr-fix nr-dl-mimo-2layer nr-dmrs-fixes nr-pdcp-benchmarking nr-pdcp-improvements nr-pdcp-nea2-security nr-pdcp-nia2-integrity nr-pdcp-small-bugfixes nr-pdcp-srb-integrity nr-ra-fix nr-stats-print nrPBCHTCFix nrPbchTcFix nr_improve_chanest nr_power_measurement_fixes nr_ue_pdcp_fix nr_ul_pf nr_ul_scfdma oairu oairu-dockerfile-support openxg/develop phy-asan-fixes physim-build-deploy physim-deploy-handle-error-cases prb_based_dl_channel_estimation ptrs_rrc_config pusch-retrans-fix-ue recursive-cmake rh-ci-add-ue-parallelization rh_ci_add_runtime_stats rh_ci_add_uldlharq_stats rh_ci_gsheet_rt_monitoring rh_ci_nsa2jenkins rh_ci_nsa_test_n310 rh_ci_phy_test_improve rh_ci_ra_fr2 rh_ci_test_benetel rh_ci_test_nsa rh_ci_test_nsa_wk16 rh_ci_test_nsa_wk17_b rh_ci_test_nsa_wk17b rh_ci_test_rfsim_sa rh_ci_ue_parallel rh_wk50_debug rohan_ulsim2RxFix s1-subnormal_rewrite s1_subnormal s1_subnormal-robert sa-merge-rrc-srb sa-msg4 sa-msg4-rrc sa-msg4-rrc-yihz sa-msg4-rrc-yihz-hs sa_rrc_yihz sanitize-address sanitize-v1 sanitize-v1-tmp sarma_pvnp_oai scs_60_iisc sim-channels small-config-change small_nr_bugfixes t-gnb-tracer test-5GREC test-nsa-benetel test-panos test_nsa_gtpu_fix test_rt-fix_phy-test ue-dci-false-detection ue-fixes ue-pdsch-pusch-parallel ue-race-fix ue_beam_selection usrp_stop_cleanly usrp_x400 wf-sa-rrc wf_testc wireshark-T-hack-ueid wireshark-log-scheduling-requests wk11-with-phytest x2_handle_sctp_shutdown xiangwab xiangwan xw2 2021.wk14_a 2021.wk13_d 2021.wk13_c 2021.w27 2021.w26 2021.w25 2021.w24 2021.w23 2021.w22 2021.w20 2021.w19 2021.w18_b 2021.w18_a 2021.w17_b 2021.w16 2021.w15 2021.w14 2021.w13_a 2021.w12 2021.w11 2021.w10 2021.w09 2021.w08 2021.w06 2021.w05 2021.w04 2021.w02 2020.w51_2 2020.w51 2020.w50 benetel_gnb_rel_2.0 benetel_gnb_rel_1.0 benetel_enb_rel_2.0 benetel_enb_rel_1.0
......@@ -407,9 +407,9 @@ void nr_ul_preprocessor_phytest(module_id_t module_id,
}
}
sched_ctrl->sched_pusch->time_domain_allocation = tda;
sched_ctrl->sched_pusch->slot = sched_slot;
sched_ctrl->sched_pusch->frame = sched_frame;
sched_ctrl->sched_pusch.time_domain_allocation = tda;
sched_ctrl->sched_pusch.slot = sched_slot;
sched_ctrl->sched_pusch.frame = sched_frame;
const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
sched_ctrl->search_space = get_searchspace(sched_ctrl->active_bwp, target_ss);
......@@ -435,9 +435,9 @@ void nr_ul_preprocessor_phytest(module_id_t module_id,
}
UE_info->num_pdcch_cand[UE_id][cid]++;
sched_ctrl->sched_pusch->mcs = 9;
sched_ctrl->sched_pusch->rbStart = rbStart;
sched_ctrl->sched_pusch->rbSize = rbSize;
sched_ctrl->sched_pusch.mcs = 9;
sched_ctrl->sched_pusch.rbStart = rbStart;
sched_ctrl->sched_pusch.rbSize = rbSize;
/* mark the corresponding RBs as used */
for (int rb = rbStart; rb < rbStart + rbSize; rb++)
......
......@@ -1799,7 +1799,6 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
UE_info->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch **)malloc(num_slots_ul*sizeof(NR_sched_pucch *));
for (int s=0; s<num_slots_ul;s++)
UE_info->UE_sched_ctrl[UE_id].sched_pucch[s] = (NR_sched_pucch *)malloc(2*sizeof(NR_sched_pucch));
UE_info->UE_sched_ctrl[UE_id].sched_pusch = calloc(num_slots_ul, sizeof(NR_sched_pusch_t));
for (int k=0; k<num_slots_ul; k++) {
for (int l=0; l<2; l++)
......@@ -1847,7 +1846,6 @@ void mac_remove_nr_ue(module_id_t mod_id, rnti_t rnti)
UE_info->rnti[UE_id] = 0;
remove_nr_ue_list(&UE_info->list, UE_id);
free(UE_info->UE_sched_ctrl[UE_id].sched_pucch);
free(UE_info->UE_sched_ctrl[UE_id].sched_pusch);
memset((void *) &UE_info->UE_sched_ctrl[UE_id],
0,
sizeof(NR_UE_sched_ctrl_t));
......
......@@ -506,9 +506,9 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
while (rbStart + rbSize < bwpSize && !vrb_map_UL[rbStart+rbSize])
rbSize++;
sched_ctrl->sched_pusch->time_domain_allocation = tda;
sched_ctrl->sched_pusch->slot = sched_slot;
sched_ctrl->sched_pusch->frame = sched_frame;
sched_ctrl->sched_pusch.time_domain_allocation = tda;
sched_ctrl->sched_pusch.slot = sched_slot;
sched_ctrl->sched_pusch.frame = sched_frame;
const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
sched_ctrl->search_space = get_searchspace(sched_ctrl->active_bwp, target_ss);
......@@ -534,13 +534,13 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
}
UE_info->num_pdcch_cand[UE_id][cid]++;
sched_ctrl->sched_pusch->mcs = 9;
sched_ctrl->sched_pusch->rbStart = rbStart;
sched_ctrl->sched_pusch->rbSize = rbSize;
sched_ctrl->sched_pusch.mcs = 9;
sched_ctrl->sched_pusch.rbStart = rbStart;
sched_ctrl->sched_pusch.rbSize = rbSize;
/* mark the corresponding RBs as used */
for (int rb = 0; rb < sched_ctrl->sched_pusch->rbSize; rb++)
vrb_map_UL[rb + sched_ctrl->sched_pusch->rbStart] = 1;
for (int rb = 0; rb < sched_ctrl->sched_pusch.rbSize; rb++)
vrb_map_UL[rb + sched_ctrl->sched_pusch.rbStart] = 1;
}
void nr_schedule_ulsch(module_id_t module_id,
......@@ -556,21 +556,21 @@ void nr_schedule_ulsch(module_id_t module_id,
const NR_UE_list_t *UE_list = &UE_info->list;
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
if (sched_ctrl->sched_pusch->rbSize <= 0)
if (sched_ctrl->sched_pusch.rbSize <= 0)
continue;
uint16_t rnti = UE_info->rnti[UE_id];
/* PUSCH in a later slot, but corresponding DCI now! */
nfapi_nr_ul_tti_request_t *future_ul_tti_req = &RC.nrmac[module_id]->UL_tti_req_ahead[0][sched_ctrl->sched_pusch->slot];
AssertFatal(future_ul_tti_req->SFN == sched_ctrl->sched_pusch->frame
&& future_ul_tti_req->Slot == sched_ctrl->sched_pusch->slot,
nfapi_nr_ul_tti_request_t *future_ul_tti_req = &RC.nrmac[module_id]->UL_tti_req_ahead[0][sched_ctrl->sched_pusch.slot];
AssertFatal(future_ul_tti_req->SFN == sched_ctrl->sched_pusch.frame
&& future_ul_tti_req->Slot == sched_ctrl->sched_pusch.slot,
"%d.%d future UL_tti_req's frame.slot %d.%d does not match PUSCH %d.%d\n",
frame, slot,
future_ul_tti_req->SFN,
future_ul_tti_req->Slot,
sched_ctrl->sched_pusch->frame,
sched_ctrl->sched_pusch->slot);
sched_ctrl->sched_pusch.frame,
sched_ctrl->sched_pusch.slot);
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
nfapi_nr_pusch_pdu_t *pusch_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pusch_pdu;
......@@ -587,7 +587,7 @@ void nr_schedule_ulsch(module_id_t module_id,
int rnti_types[2] = { NR_RNTI_C, 0 };
//Resource Allocation in time domain
const int tda = sched_ctrl->sched_pusch->time_domain_allocation;
const int tda = sched_ctrl->sched_pusch.time_domain_allocation;
const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList =
sched_ctrl->active_ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
const int startSymbolAndLength = tdaList->list.array[tda]->startSymbolAndLength;
......@@ -617,7 +617,7 @@ void nr_schedule_ulsch(module_id_t module_id,
else
pusch_pdu->data_scrambling_id = *scc->physCellId;
pusch_pdu->mcs_index = sched_ctrl->sched_pusch->mcs;
pusch_pdu->mcs_index = sched_ctrl->sched_pusch.mcs;
const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
if (pusch_pdu->transform_precoding)
pusch_pdu->mcs_table = get_pusch_mcs_table(pusch_Config->mcs_Table,
......@@ -650,8 +650,8 @@ void nr_schedule_ulsch(module_id_t module_id,
AssertFatal(pusch_Config->resourceAllocation == NR_PUSCH_Config__resourceAllocation_resourceAllocationType1,
"Only frequency resource allocation type 1 is currently supported\n");
pusch_pdu->resource_alloc = 1; //type 1
pusch_pdu->rb_start = sched_ctrl->sched_pusch->rbStart;
pusch_pdu->rb_size = sched_ctrl->sched_pusch->rbSize;
pusch_pdu->rb_start = sched_ctrl->sched_pusch.rbStart;
pusch_pdu->rb_size = sched_ctrl->sched_pusch.rbSize;
pusch_pdu->vrb_to_prb_mapping = 0;
if (pusch_Config->frequencyHopping==NULL)
......@@ -741,7 +741,7 @@ void nr_schedule_ulsch(module_id_t module_id,
pusch_pdu->pusch_data.rv_index = nr_rv_round_map[cur_harq->round];
cur_harq->state = ACTIVE_SCHED;
cur_harq->last_tx_slot = sched_ctrl->sched_pusch->slot;
cur_harq->last_tx_slot = sched_ctrl->sched_pusch.slot;
uint8_t num_dmrs_symb = 0;
for(int i = pusch_pdu->start_symbol_index; i < pusch_pdu->start_symbol_index + pusch_pdu->nr_of_symbols; i++)
......@@ -813,6 +813,6 @@ void nr_schedule_ulsch(module_id_t module_id,
pusch_pdu->bwp_size,
sched_ctrl->active_bwp->bwp_Id);
sched_ctrl->sched_pusch->rbSize = 0;
memset(&sched_ctrl->sched_pusch, 0, sizeof(sched_ctrl->sched_pusch));
}
}
......@@ -287,8 +287,6 @@ typedef struct NR_sched_pucch {
typedef struct NR_sched_pusch {
int frame;
int slot;
bool active;
nfapi_nr_pusch_pdu_t pusch_pdu;
/// RB allocation within active uBWP
uint16_t rbSize;
......@@ -364,7 +362,7 @@ typedef struct {
/// selected PUCCH index, if scheduled
int pucch_sched_idx;
int pucch_occ_idx;
NR_sched_pusch_t *sched_pusch;
NR_sched_pusch_t sched_pusch;
/// CCE index and aggregation, should be coherent with cce_list
NR_SearchSpace_t *search_space;
......
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