Commit 171f7842 authored by Robert Schmidt's avatar Robert Schmidt

Rewrite PUCCH allocation (simplified, restricted)

- No dynamic allocation of PUCCH structures
- Use first PUCCH for HARQ (can only allocate for up to two slots in
  single PUCCH, simplistic nr_acknack_scheduling!)
- Use second PUCCH for CSI, do not multiplex!
parent 4e91f448
dev 512-dataplane-bug-in-l2nfapi_nos1 FR2_NSA Fix_SA_SIB1 NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_2port_CSIRS NR_CSIRS_tomerge NR_DLUL_PF NR_DLUL_PF_4UL NR_DL_MIMO NR_F1C_F1U_extensions NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_initsync_fixes NR_MAC_Multi_Rach_GlobalEdge NR_MAC_SSB NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS-USIM NR_SA_F1AP_5GRECORDS-wf-0623 NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_w5GCN_new_gtpu NR_UE_CONFIG_REQ_FIXES NR_UE_PUCCH_bugfixes NR_UE_SA NR_UE_rework_test NR_UE_reworking_UCI_procedures NR_cleanup_PUCCH_resources NR_gNB_initial_MIB_fix NR_multiplexing_HARQ_CSI_PUCCH NR_phytest_bugfixes NR_reworking_UL_antennaports NR_scheduling_CSIRS NR_scheduling_request PBCHNRTCFIX RFquality Saankhya_NRPRACH_HighSpeed Test_SA_5GREC add-dmrs-test add-ru-docker-image avxllr bandwidth-testing benetel_config_file_fix benetel_dpdk20 benetel_driver_update benetel_fixes bsr-fix bugfix-free-ra-process bugfix-nr-t-reordering bugfix_gnb_rt_stats_html ci-fix-module-ul-iperf ci-new-docker-pipeline ci-reduce-nb-vms ci_benetel_longrun_limits ci_benetel_test ci_fix_iperf_for_module ci_hotfix_module_ue_ip_address ci_improve_module_ctl ci_nsa_benetel ci_nsa_fixes ci_nsa_pipes_improve ci_nsa_test_integration_2021_wk19 ci_nsa_traces ci_nsa_uplink ci_phytest ci_quectel_support ci_sa_rfsim_test ci_solve_ul_for_module ci_test_5GREC ci_test_nsa_fix_quectel_nic ci_test_nsa_on_develop ci_test_ra_fr2 ci_testinfra_as_code ci_vm_resource_fix debug-UL-5GRECORDS debug_UL_signal detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS-v3 develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts develop-SA-RA develop-aw2sori develop-wf-du disable_CSI_measrep docker-improvements-2021-april docker-no-cache-option dongzhanyi-zte-develop1 enhance-rfsim episys-merge episys/nsa_baseline episys/nsa_development fedora-gen-kernel-fix fft_bench_hotfix fix-check fix-compile fix-nr-pdcp-timer fix-nr-rlc-range-nack fix-physim-deploy fix-quectel fix-realtime fix-retransmission-rbg fix-x2-without-gnb fix_NR_DLUL_PF fix_NR_DLUL_PF_benchmark fix_coreset_dmrs_idx fix_nr_ulsim fix_rb_corruption fix_reestablishment fixgtpu flexran-rtc-repo-is-public git-dashboard gnb-freerun-txru gnb-n300-fixes gnb-realtime-hotfix gnb-realtime-quickfix gnb-threadpool hack-bch-no-sched-sf-0 hack-exit-gnb-when-no-enb-nsa integ-w13-test-rt-issue integration_2020_wk15 integration_2021_wk06 integration_2021_wk06_MR978 integration_2021_wk06_b integration_2021_wk06_c integration_2021_wk08 integration_2021_wk08_2 integration_2021_wk08_MR963 integration_2021_wk09 integration_2021_wk09_b integration_2021_wk10 integration_2021_wk10_b integration_2021_wk11 integration_2021_wk12 integration_2021_wk12_b integration_2021_wk13_a integration_2021_wk13_b integration_2021_wk13_b_fix_tdas integration_2021_wk13_b_fixed integration_2021_wk13_c integration_2021_wk14_a integration_2021_wk15_a integration_2021_wk16 integration_2021_wk17_a integration_2021_wk17_b integration_2021_wk18_a integration_2021_wk18_b integration_2021_wk19 integration_2021_wk20_a integration_2021_wk22 integration_2021_wk23 integration_2021_wk27 integration_w5GC_CBRA_test inter-RRU-final ldpc_offload_t1 migrate-cpp-check-container migrate-vm-pipeline-to-bionic msg4_phy_0303_lfq multiple_ssb_sib1_bugfix new-gtpu nfapi_nr_arch_mod nfapi_nr_develop_new nr-bsr-fix nr-dl-mimo-2layer nr-dmrs-fixes nr-pdcp-benchmarking nr-pdcp-improvements nr-pdcp-nea2-security nr-pdcp-nia2-integrity nr-pdcp-small-bugfixes nr-pdcp-srb-integrity nr-ra-fix nr-stats-print nrPBCHTCFix nrPbchTcFix nr_improve_chanest nr_power_measurement_fixes nr_ue_pdcp_fix oairu phy-asan-fixes physim-build-deploy physim-deploy-handle-error-cases prb_based_dl_channel_estimation ptrs_rrc_config recursive-cmake rh_ci_add_runtime_stats rh_ci_add_uldlharq_stats rh_ci_gsheet_rt_monitoring rh_ci_nsa2jenkins rh_ci_nsa_test_n310 rh_ci_phy_test_improve rh_ci_test_benetel rh_ci_test_nsa rh_ci_test_nsa_wk16 rh_ci_test_nsa_wk17_b rh_ci_test_nsa_wk17b rh_ci_test_rfsim_sa rohan_ulsim2RxFix s1_subnormal sanitize-address sanitize-v1 sanitize-v1-tmp sarma_pvnp_oai scs_60_iisc sim-channels small_nr_bugfixes t-gnb-tracer test-5GREC test-nsa-benetel test-panos test_nsa_gtpu_fix test_rt-fix_phy-test ue-dci-false-detection ue-pdsch-pusch-parallel ue-race-fix usrp_stop_cleanly usrp_x400 wf-sa-rrc wf_testc wk11-with-phytest x2_handle_sctp_shutdown xw2 2021.wk14_a 2021.wk13_d 2021.wk13_c 2021.w27 2021.w26 2021.w25 2021.w24 2021.w23 2021.w22 2021.w20 2021.w19 2021.w18_b 2021.w18_a 2021.w17_b 2021.w16 2021.w15 2021.w14 2021.w13_a 2021.w12 2021.w11 2021.w10 2021.w09 2021.w08 2021.w06 benetel_gnb_rel_2.0 benetel_gnb_rel_1.0 benetel_enb_rel_2.0 benetel_enb_rel_1.0
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......@@ -203,10 +203,6 @@ void nr_dlsim_preprocessor(module_id_t module_id,
sched_ctrl->active_bwp, sched_ctrl->search_space, 1 /* dedicated */);
sched_ctrl->cce_index = 0;
/* set "any" value for PUCCH (simulator evaluates PDSCH only) */
sched_ctrl->pucch_sched_idx = 0;
sched_ctrl->pucch_occ_idx = 0;
sched_ctrl->rbStart = g_rbStart;
sched_ctrl->rbSize = g_rbSize;
sched_ctrl->mcs = g_mcsIndex;
......
......@@ -442,15 +442,10 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
UE_info->num_pdcch_cand[UE_id][cid]++;
/* Find PUCCH occasion */
nr_acknack_scheduling(module_id,
UE_id,
frame,
slot,
num_slots_per_tdd,
&sched_ctrl->pucch_sched_idx,
&sched_ctrl->pucch_occ_idx);
AssertFatal(sched_ctrl->pucch_sched_idx >= 0, "no uplink slot for PUCCH found!\n");
const bool alloc = nr_acknack_scheduling(module_id, UE_id, frame, slot);
AssertFatal(alloc,
"could not find uplink slot for PUCCH (RNTI %04x@%d.%d)!\n",
rnti, frame, slot);
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
// for now HARQ PID is fixed and should be the same as in post-processor
......@@ -595,7 +590,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
const int current_harq_pid = slot % num_slots_per_tdd;
NR_UE_harq_t *harq = &sched_ctrl->harq_processes[current_harq_pid];
NR_sched_pucch_t *pucch = &sched_ctrl->sched_pucch[sched_ctrl->pucch_sched_idx][sched_ctrl->pucch_occ_idx];
NR_sched_pucch_t *pucch = &sched_ctrl->sched_pucch[0];
harq->feedback_slot = pucch->ul_slot;
harq->is_waiting = 1;
UE_info->mac_stats[UE_id].dlsch_rounds[harq->round]++;
......
......@@ -328,14 +328,10 @@ void nr_preprocessor_phytest(module_id_t module_id,
__func__,
UE_id);
nr_acknack_scheduling(module_id,
UE_id,
frame,
slot,
num_slots_per_tdd,
&sched_ctrl->pucch_sched_idx,
&sched_ctrl->pucch_occ_idx);
AssertFatal(sched_ctrl->pucch_sched_idx >= 0, "no uplink slot for PUCCH found!\n");
const bool alloc = nr_acknack_scheduling(module_id, UE_id, frame, slot);
AssertFatal(alloc,
"could not find uplink slot for PUCCH (RNTI %04x@%d.%d)!\n",
rnti, frame, slot);
sched_ctrl->rbStart = rbStart;
sched_ctrl->rbSize = rbSize;
......
......@@ -1894,16 +1894,6 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
UE_info->UE_sched_ctrl[UE_id].ul_rssi = 0;
/* set illegal time domain allocation to force recomputation of all fields */
UE_info->UE_sched_ctrl[UE_id].pusch_save.time_domain_allocation = -1;
UE_info->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch_t **)malloc(num_slots_ul*sizeof(NR_sched_pucch_t *));
for (int s=0; s<num_slots_ul;s++)
UE_info->UE_sched_ctrl[UE_id].sched_pucch[s] = (NR_sched_pucch_t *)malloc(2*sizeof(NR_sched_pucch_t));
for (int k=0; k<num_slots_ul; k++) {
for (int l=0; l<2; l++)
memset((void *) &UE_info->UE_sched_ctrl[UE_id].sched_pucch[k][l],
0,
sizeof(NR_sched_pucch_t));
}
LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n",
mod_idP,
UE_id,
......@@ -1943,7 +1933,6 @@ void mac_remove_nr_ue(module_id_t mod_id, rnti_t rnti)
UE_info->active[UE_id] = FALSE;
UE_info->rnti[UE_id] = 0;
remove_nr_ue_list(&UE_info->list, UE_id);
free(UE_info->UE_sched_ctrl[UE_id].sched_pucch);
memset((void *) &UE_info->UE_sched_ctrl[UE_id],
0,
sizeof(NR_UE_sched_ctrl_t));
......
......@@ -224,15 +224,10 @@ void nr_csi_meas_reporting(int Mod_idP,
int ul_slots,
int n_slots_frame);
void nr_acknack_scheduling(int Mod_idP,
bool nr_acknack_scheduling(int Mod_idP,
int UE_id,
frame_t frameP,
sub_frame_t slotP,
int slots_per_tdd,
int *pucch_id,
int *pucch_occ);
int get_pucch_resource(NR_UE_info_t *UE_info,int UE_id,int k,int l);
sub_frame_t slotP);
void get_pdsch_to_harq_feedback(int Mod_idP,
int UE_id,
......
......@@ -387,10 +387,12 @@ typedef struct {
/// the currently active BWP in UL
NR_BWP_Uplink_t *active_ubwp;
NR_sched_pucch_t **sched_pucch;
/// selected PUCCH index, if scheduled
int pucch_sched_idx;
int pucch_occ_idx;
/// PUCCH scheduling information. Array of two, we assume for the moment:
/// HARQ (and SR) in the first field, CSI in second (as fixed by RRC conf.,
/// i.e. if actually present). The order is important for
/// nr_acknack_scheduling()!
NR_sched_pucch_t sched_pucch[2];
NR_sched_pusch_save_t pusch_save;
NR_sched_pusch_t sched_pusch;
......
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