Commit 9ccb93a0 authored by Wang Tsu-Han's avatar Wang Tsu-Han

adding mask for feptx thread and VCD logging

parent 009bacc8
dev 1 128-ues 256_QAM_demod 459-pusch-based-ta-updates 464-ru_beamforming_in_gpu 464-ru_beamforming_in_gpu-CPUsubfunction 472-add-pusch-dmrs-modes 481-ldpc-decoder-on-gpu 512-dataplane-bug-in-l2nfapi_nos1 FR2_NSA Fix_SA_SIB1 LTE_TRX_on_single_port NCTU_CS_ISIP NCTU_CS_ISIP_CPU NCTU_CS_ISIP_GPU NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_2port_CSIRS NR_CSIRS_tomerge NR_CSI_reporting NR_DCI_01 NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_DL_sched_fixes NR_DL_scheduler NR_F1C_F1U_extensions NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_FR2_initsync_fixes NR_MAC_CE_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_NGAP NR_PDCP_noS1 NR_PUCCH_MultiUE NR_RA_cleanup NR_RA_updates NR_RRCConfiguragion_FR2 NR_RRCConfiguration NR_RRCConfiguration_FR2 NR_RRCConfiguration_S1U NR_RRCConfiguration_merge_develop NR_RRCConfiguration_sync_source NR_RRCConfiguration_trx_thread NR_RRC_CP_bugfix NR_RRC_PDCP NR_RRC_PRACH_procedures NR_RRC_PRACH_procedures_todevelop NR_RRC_PUSCH NR_RRC_TA NR_RRC_X2AP_AMBR_Change_Global_edge NR_RRC_X2AP_RemoveHardcodings_GlobalEdge NR_RRC_config_simplified NR_RRC_harq NR_RRC_harq_b NR_RRC_harq_hacks NR_RRC_harq_newdcipdu NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS-USIM NR_SA_F1AP_5GRECORDS-wf-0623 NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SA_w5GCN_new_gtpu NR_SCHED NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_TRX_on_single_port NR_TRX_on_single_port2 NR_UE_CONFIG_REQ_FIXES NR_UE_MAC_scheduler NR_UE_PUCCH_bugfixes NR_UE_RA_fixes NR_UE_SA NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_rework_test NR_UE_reworking_UCI_procedures NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_SCFDMA_100MHz NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_Wireshark NR_beam_simulation NR_beamforming_test NR_cleanup_PUCCH_resources NR_gNB_SCF_Indication NR_gNB_initial_MIB_fix NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_multiplexing_HARQ_CSI_PUCCH NR_phytest_bugfixes NR_reworking_UL_antennaports NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 NR_test_S1U_RRC_PRACH_procedures NR_ue_dlsch_dmrs_cdm OpInConnect_ISIP PBCHNRTCFIX PUSCH_TA_update RA_CI_test RFquality Saankhya_NRPRACH_HighSpeed Test_SA_5GREC UE_DL_DCI_hotfix add-dmrs-test add-ru-docker-image avxllr bandwidth-testing bch-fixes-bitmap benetel_5g_prach_fix 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ci_test_nsa_on_develop ci_test_ra_fr2 ci_testinfra_as_code ci_vm_resource_fix clean-5G-scope-round2 cleanup_softmodem_main constant_power debug-UL-5GRECORDS debug_UL_signal debug_branch_init_sync detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS-v3 develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts develop-SA-RA develop-SnT develop-aw2sori develop-nr develop-nr-fr2-rework develop-nr_cppcheck develop-oriecpriupdates develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop-wf-du develop_inria_ci_deployment develop_inria_ci_deployment_gp develop_integration_2020_w15 develop_integration_2020_w19 develop_integration_w08 develop_stable dfts_alternatives disable_CSI_measrep dlsch-all-dlslots dlsch_encode_mthread dlsch_parallel docker-improvements-2021-april docker-no-cache-option docupdate_tools dongzhanyi-zte-develop dongzhanyi-zte-develop1 dongzhanyi-zte-develop2 dreibh/apt-auth-fix dreibh/device-load-fix dreibh/device-load-fix-develop-branch edrx enhance-rfsim episys-merge episys/nsa_baseline episys/nsa_development extend_sharedlibusage extend_sharedlibusage2 fapi_for_dmrs_and_ptrs feature-4g-sched feature-support-clang-format feature/make-s1-mme-port-configurable feature/make-s1-mme-port-configurable-with-astyle-fixes fedora-gen-kernel-fix fembms-enb-ue fft_bench_hotfix finalize-oaicn-integration firas fix-check fix-ci-tun fix-clock-source fix-compile fix-itti-segv fix-l2-sim fix-limeSDR-compile fix-nr-pdcp-timer fix-nr-rlc-range-nack fix-physim-deploy fix-quectel fix-realtime fix-retransmission-rbg fix-softmodem-restart fix-warnings fix-x2-without-gnb fix_NR_DLUL_PF fix_NR_DLUL_PF_benchmark fix_coreset_dmrs_idx fix_do_ra_data fix_nr_ulsim fix_pdsch_low_prb fix_rb_corruption fix_reestablishment fix_rfsim_mimo fix_rrc_x2_ticking fixes-CE-RLC-PDU-size fixes-mac-sched-nfapi fixes-mac-sched-tun fixes-tun fixgtpu flexran-apps flexran-improvements flexran-repair-mme-mgmt flexran-rtc-repo-is-public fr2-hw-test fujitsu_lte_contribution fujitsu_lte_contribution-128 generate_push_ptrs git-dashboard gnb-freerun-txru gnb-n300-fixes gnb-only-test gnb-realtime-hotfix gnb-realtime-quickfix gnb-threadpool hack-bch-no-sched-sf-0 hack-exit-gnb-when-no-enb-nsa harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick hotfix-ocp-executable hotfix-ue-musim-compilation improve_build_nr_lte_merge improve_nr_modulation improve_ue_stability integ-w13-test-rt-issue integration_2020_wk15 integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 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integration_2021_wk18_b integration_2021_wk19 integration_2021_wk20_a integration_2021_wk22 integration_2021_wk23 integration_2021_wk27 integration_w5GC_CBRA_test inter-RRU-final inter-RRU-nr inter-RRU-oairu inter-rru-UE isip_nr itti-enhancement l2-fixes ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc-offload ldpc_offload_t1 ldpc_short_codeword_fixes load_gnb lte-ulsch-bugfix lte_uplink_improvement mac-fixes-wk45_2 mbms-fix-develop-nr merging-2019-w51-to-develop-nr migrate-cpp-check-container migrate-vm-pipeline-to-bionic minor-fix-doc-basic-sim mosaic5g-oai-ran mosaic5g-oai-sim msg4_phy_0303_lfq multiple_ssb_sib1_bugfix nasmesh_kernel_5.8 new-gtpu new_rlc_2020 nfapi-bugfix nfapi_nr_arch_mod nfapi_nr_develop nfapi_nr_develop_new ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1120-srb-gtp-yhz ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-bsr-fix nr-dl-mimo-2layer nr-dlsch-multi-thread nr-dlsch-thread nr-dmrs-fixes nr-dual-connectivity nr-ip-uplink-noS1 nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-pdcp nr-pdcp-benchmarking nr-pdcp-improvements nr-pdcp-nea2-security nr-pdcp-nia2-integrity nr-pdcp-small-bugfixes nr-pdcp-srb-integrity nr-ra-fix nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nr-stats-print nr-ue-buffer-status nrPBCHTCFix nrPbchTcFix nrUE nrUE-hs nrUE-upper-layer nr_beamforming nr_bsr nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_fdd_if_fix nr_fix_easycppcheck nr_improve_build_procedures nr_improve_chanest nr_increase_tp nr_polar_decoder_improvement nr_power_measurement_fixes nr_prach_fr2 nr_pucch nr_pucch2 nr_segmentation_fixes nr_tdd_configuration nr_ue_msg3 nr_ue_pdcp_fix nr_ue_tti_cleanup nr_ul_pf nr_ul_scfdma nrue-multi-thread nrue_msg2_reception nsa-ue nsa_remove_band_hardcodings oai-sim oai-ubuntu-docker oai-ubuntu-docker-for-lmssdr oairu oairu-dockerfile-support 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......@@ -247,7 +247,8 @@ const char* eurecomVariablesNames[] = {
"slot_number_TX0_gNB",
"slot_number_TX1_gNB",
"slot_number_RX0_gNB",
"slot_number_RX1_gNB"
"slot_number_RX1_gNB",
"ru_tx_ofdm_mask"
};
const char* eurecomFunctionsNames[] = {
......@@ -328,6 +329,13 @@ const char* eurecomFunctionsNames[] = {
"phy_procedures_ru_feptx_ofdm7",
"phy_procedures_ru_feptx_ofdm8",
"phy_procedures_ru_feptx_ofdm9",
"phy_procedures_ru_feptx_ofdm10",
"phy_procedures_ru_feptx_ofdm11",
"phy_procedures_ru_feptx_ofdm12",
"phy_procedures_ru_feptx_ofdm13",
"phy_procedures_ru_feptx_ofdm14",
"phy_procedures_ru_feptx_ofdm15",
"phy_procedures_ru_feptx_ofdm16",
"phy_procedures_ru_feptx_prec0",
"phy_procedures_ru_feptx_prec1",
"phy_procedures_ru_feptx_prec2",
......
......@@ -225,6 +225,7 @@ typedef enum {
VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_TX1_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_RX0_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_RX1_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_RU_TX_OFDM_MASK,
VCD_SIGNAL_DUMPER_VARIABLES_END
......@@ -309,6 +310,13 @@ typedef enum {
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM7,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM8,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM9,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM10,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM11,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM12,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM13,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM14,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM15,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM16,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC1,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_PREC2,
......
......@@ -73,10 +73,10 @@ typedef struct {
} T_cache_t;
/* number of VCD functions (to be kept up to date! see in T_messages.txt) */
#define VCD_NUM_FUNCTIONS (231)
#define VCD_NUM_FUNCTIONS (238)
/* number of VCD variables (to be kept up to date! see in T_messages.txt) */
#define VCD_NUM_VARIABLES (185)
#define VCD_NUM_VARIABLES (186)
/* first VCD function (to be kept up to date! see in T_messages.txt) */
#define VCD_FIRST_FUNCTION ((uintptr_t)T_VCD_FUNCTION_RT_SLEEP)
......
......@@ -2050,6 +2050,11 @@ ID = VCD_VARIABLE_SLOT_NUMBER_RX1_GNB
GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value
VCD_NAME = slot_number_RX1_gNB
ID = VCD_VARIABLE_RU_TX_OFDM_MASK
DESC = VCD variable RU_TX_OFDM_MASK
GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value
VCD_NAME = ru_tx_ofdm_mask
#functions
......@@ -2418,6 +2423,41 @@ ID = VCD_FUNCTION_PHY_PROCEDURES_RU_FEPTX_OFDM9
GROUP = ALL:VCD:ENB:VCD_FUNCTION
FORMAT = int,value
VCD_NAME = phy_procedures_ru_feptx_ofdm9
ID = VCD_FUNCTION_PHY_PROCEDURES_RU_FEPTX_OFDM10
DESC = VCD function PHY_PROCEDURES_RU_FEPTX_OFDM10
GROUP = ALL:VCD:ENB:VCD_FUNCTION
FORMAT = int,value
VCD_NAME = phy_procedures_ru_feptx_ofdm10
ID = VCD_FUNCTION_PHY_PROCEDURES_RU_FEPTX_OFDM11
DESC = VCD function PHY_PROCEDURES_RU_FEPTX_OFDM11
GROUP = ALL:VCD:ENB:VCD_FUNCTION
FORMAT = int,value
VCD_NAME = phy_procedures_ru_feptx_ofdm11
ID = VCD_FUNCTION_PHY_PROCEDURES_RU_FEPTX_OFDM12
DESC = VCD function PHY_PROCEDURES_RU_FEPTX_OFDM12
GROUP = ALL:VCD:ENB:VCD_FUNCTION
FORMAT = int,value
VCD_NAME = phy_procedures_ru_feptx_ofdm12
ID = VCD_FUNCTION_PHY_PROCEDURES_RU_FEPTX_OFDM13
DESC = VCD function PHY_PROCEDURES_RU_FEPTX_OFDM13
GROUP = ALL:VCD:ENB:VCD_FUNCTION
FORMAT = int,value
VCD_NAME = phy_procedures_ru_feptx_ofdm13
ID = VCD_FUNCTION_PHY_PROCEDURES_RU_FEPTX_OFDM14
DESC = VCD function PHY_PROCEDURES_RU_FEPTX_OFDM14
GROUP = ALL:VCD:ENB:VCD_FUNCTION
FORMAT = int,value
VCD_NAME = phy_procedures_ru_feptx_ofdm14
ID = VCD_FUNCTION_PHY_PROCEDURES_RU_FEPTX_OFDM15
DESC = VCD function PHY_PROCEDURES_RU_FEPTX_OFDM15
GROUP = ALL:VCD:ENB:VCD_FUNCTION
FORMAT = int,value
VCD_NAME = phy_procedures_ru_feptx_ofdm15
ID = VCD_FUNCTION_PHY_PROCEDURES_RU_FEPTX_OFDM16
DESC = VCD function PHY_PROCEDURES_RU_FEPTX_OFDM16
GROUP = ALL:VCD:ENB:VCD_FUNCTION
FORMAT = int,value
VCD_NAME = phy_procedures_ru_feptx_ofdm16
ID = VCD_FUNCTION_PHY_PROCEDURES_RU_FEPTX_PREC
DESC = VCD function PHY_PROCEDURES_RU_FEPTX_PREC
GROUP = ALL:VCD:ENB:VCD_FUNCTION
......
......@@ -1663,6 +1663,7 @@ void init_RU_proc(RU_t *ru) {
proc->frame_offset = 0;
proc->num_slaves = 0;
proc->frame_tx_unwrap = 0;
proc->feptx_mask = 0;
for (i=0; i<10; i++) proc->symbol_mask[i]=0;
......
......@@ -144,12 +144,12 @@ int nr_beam_precoding(int32_t **txdataF,
int32_t ***beam_weights,
int slot,
int symbol,
int aa)
int aa,
int nb_antenna_ports)
{
uint8_t p;
int nb_antenna_ports = frame_parms->Lmax; // for now logical antenna ports corresponds to SSB
// clear txdata_BF[aa][re] for each call of ue_spec_beamforming
memset(&txdataF_BF[aa][symbol*frame_parms->ofdm_symbol_size],0,sizeof(int32_t)*(frame_parms->ofdm_symbol_size));
......@@ -164,5 +164,5 @@ int nr_beam_precoding(int32_t **txdataF,
15);
}
}
return 0;
return 0;
}
......@@ -87,6 +87,8 @@ int nr_beam_precoding(int32_t **txdataF,
int32_t ***beam_weights,
int slot,
int symbol,
int aa);
int aa,
int nb_antenna_ports
);
#endif
......@@ -183,6 +183,8 @@ typedef struct RU_feptx_t_s{
int aa;//physical MAX nb_tx
int half_slot;//first or second half of a slot
int slot;//current slot
int nb_antenna_ports;//number of logical port
int index;
}RU_feptx_t;
typedef struct RU_proc_t_s {
......@@ -400,9 +402,12 @@ typedef struct RU_proc_t_s {
int ru_tx_ready;
int emulate_rf_busy;
/// structure for precoding thread
RU_prec_t prec[16];
/// structure for feptx thread
RU_feptx_t feptx[16];
/// mask for checking process finished
int feptx_mask;
} RU_proc_t;
typedef enum {
......
......@@ -121,6 +121,8 @@ void nr_feptx_ofdm_2thread(RU_t *ru,int frame_tx,int tti_tx) {
int slot = tti_tx;
int i = 0;
int ret = 0;
int nb_antenna_ports = 4;
int ofdm_mask_full = (1<<(ru->nb_tx*2))-1;
start_meas(&ru->total_precoding_stats);
......@@ -129,10 +131,11 @@ void nr_feptx_ofdm_2thread(RU_t *ru,int frame_tx,int tti_tx) {
cfg = &gNB->gNB_config;
if (nr_slot_select(cfg,tti_tx) == SF_UL) return;
for(i=0; i<fp->Lmax; ++i)
for(i=0; i<nb_antenna_ports; ++i){
memcpy((void*)ru->common.txdataF[i],
(void*)gNB->common_vars.txdataF[i],
fp->samples_per_slot_wCP*sizeof(int32_t));
}
}//num_gNB == 1
stop_meas(&ru->total_precoding_stats);
......@@ -148,21 +151,28 @@ void nr_feptx_ofdm_2thread(RU_t *ru,int frame_tx,int tti_tx) {
AssertFatal((ret=pthread_mutex_lock(&feptx[i].mutex_feptx))==0,"mutex_lock return %d\n",ret);
feptx[i].half_slot = i%2;
feptx[i].aa = i>>1;
feptx[i].index = i;
feptx[i].ru = ru;
feptx[i].slot = slot;
feptx[i].nb_antenna_ports = nb_antenna_ports;
feptx[i].instance_cnt_feptx = 0;
AssertFatal(pthread_cond_signal(&feptx[i].cond_feptx) == 0,"ERROR pthread_cond_signal for gNB_L1_thread\n");
AssertFatal(pthread_cond_signal(&feptx[i].cond_feptx) == 0,"ERROR pthread_cond_signal for feptx_ofdm_thread\n");
AssertFatal((ret=pthread_mutex_unlock(&feptx[i].mutex_feptx))==0,"mutex_lock returns %d\n",ret);
}
}
// call first half-slot in this thread
i = 0;
while(1){
if(feptx[i].instance_cnt_feptx == -1) ++i;
if(i == 16) break;
// wait all process to finish
AssertFatal((ret=pthread_mutex_lock(&proc->mutex_feptx))==0,"mutex_lock return %d\n",ret);
while (proc->feptx_mask != ofdm_mask_full) {
// most of the time the thread is waiting here
// proc->instance_cnt_rxtx is -1
pthread_cond_wait(&proc->cond_feptx,&proc->mutex_feptx); // this unlocks mutex_rxtx while waiting and then locks it again
}
proc->feptx_mask = 0;
AssertFatal((ret=pthread_mutex_unlock(&proc->mutex_feptx))==0,"mutex_lock return %d\n",ret);
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_RU_TX_OFDM_MASK, proc->feptx_mask );
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM , 0 );
//write_output
......@@ -175,19 +185,25 @@ static void *nr_feptx_thread(void *param) {
RU_feptx_t *feptx = (RU_feptx_t *)param;
RU_t *ru;
int aa, slot, start, l;
int aa, slot, start, l, nb_antenna_ports, ret;
int32_t ***bw;
NR_DL_FRAME_PARMS *fp;
int ofdm_mask_full;
while (!oai_exit) {
ret = 0;
if (wait_on_condition(&feptx->mutex_feptx,&feptx->cond_feptx,&feptx->instance_cnt_feptx,"NR feptx thread")<0) break;
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM+feptx->index+1 , 1 );
ru = feptx->ru;
slot = feptx->slot;
aa = feptx->aa;
fp = ru->nr_frame_parms;
start = (feptx->half_slot)? fp->symbols_per_slot>>1 : 0;
nb_antenna_ports = feptx->nb_antenna_ports;
ofdm_mask_full = (1<<(ru->nb_tx*2))-1;
bw = ru->beam_weights[0];
for (l=0;l<fp->symbols_per_slot>>1;l++) {
......@@ -197,18 +213,22 @@ static void *nr_feptx_thread(void *param) {
bw,
slot,
l+start,
aa);
aa,
nb_antenna_ports);
}// for (l=0;l<fp->symbols_per_slot;l++)
nr_feptx0(ru,slot,start,fp->symbols_per_slot>>1,aa);
if (pthread_cond_signal(&feptx->cond_feptx) != 0) {
LOG_E(PHY,"[gNB] ERROR pthread_cond_signal for NR feptx thread exit\n");
exit_fun( "ERROR pthread_cond_signal" );
return NULL;
}
if (release_thread(&feptx->mutex_feptx,&feptx->instance_cnt_feptx,"NR feptx thread")<0) break;
AssertFatal((ret=pthread_mutex_lock(&ru->proc.mutex_feptx))==0,"mutex_lock return %d\n",ret);
ru->proc.feptx_mask |= 1<<(feptx->index);
if(ru->proc.feptx_mask == ofdm_mask_full)
AssertFatal(pthread_cond_signal(&ru->proc.cond_feptx) == 0,"ERROR pthread_cond_signal for precoding and ofdm finish\n");
AssertFatal((ret=pthread_mutex_unlock(&ru->proc.mutex_feptx))==0,"mutex_lock returns %d\n",ret);
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_RU_TX_OFDM_MASK, ru->proc.feptx_mask );
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM+feptx->index+1 , 0 );
}
return(NULL);
}
......@@ -400,7 +420,8 @@ void nr_feptx_prec(RU_t *ru,int frame,int tti_tx) {
bw,
tti_tx,
l,
aa);
aa,
fp->Lmax);
}// for (aa=0;aa<ru->nb_tx;aa++)
}// for (l=0;l<fp->symbols_per_slot;l++)
}// if (ru->nb_tx == 1)
......
......@@ -70,7 +70,7 @@ gNBs =
UL_BWP_prefix_type = "NORMAL";
UL_timeAlignmentTimerCommon = "infinity";
ServingCellConfigCommon_n_TimingAdvanceOffset = "n0"
ServingCellConfigCommon_ssb_PositionsInBurst_PR = 0x01;
ServingCellConfigCommon_ssb_PositionsInBurst_PR = 0x0f;#####
ServingCellConfigCommon_ssb_periodicityServingCell = 10;
ServingCellConfigCommon_dmrs_TypeA_Position = 2;
NIA_SubcarrierSpacing = "kHz15";
......
[*]
[*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI
[*] Sat May 18 17:25:11 2019
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Fri Sep 6 15:01:30 2019
[*]
[dumpfile] "/tmp/openair_dump_gNB40.vcd"
[dumpfile_mtime] "Sat May 18 17:11:31 2019"
[dumpfile_size] 53148516
[savefile] "/home/caracal/raymond/openairinterface5g/targets/RT/USER/gNB_usrp.gtkw"
[timestart] 11552775390
[size] 1840 795
[dumpfile] "/tmp/gNB_prec.vcd"
[dumpfile_mtime] "Fri Sep 6 14:59:50 2019"
[dumpfile_size] 13106022
[savefile] "/homes/wangts/openairinterface5g/targets/RT/USER/gNB_usrp.gtkw"
[timestart] 2183320000
[size] 1920 1018
[pos] -1 -1
*-13.848083 11552814436 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-18.423141 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 386
[signals_width] 344
[sst_expanded] 1
[sst_vpaned_height] 197
[sst_vpaned_height] 267
@28
functions.trx_read
functions.trx_write
......@@ -24,9 +24,8 @@ variables.frame_number_TX1_UE[63:0]
functions.ue_gain_control
@420
variables.frame_number_RX1_UE[63:0]
@25
variables.trx_ts_ue[63:0]
@24
variables.trx_ts_ue[63:0]
variables.trx_ts[63:0]
variables.trx_tst[63:0]
variables.frame_number_RX0_RU[63:0]
......@@ -63,5 +62,7 @@ functions.phy_procedures_ru_feptx_ofdm0
functions.phy_procedures_ru_feptx_ofdm1
functions.phy_procedures_ru_feptx_prec0
functions.phy_procedures_ru_feptx_prec1
@23
variables.ru_tx_ofdm_mask[63:0]
[pattern_trace] 1
[pattern_trace] 0
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