Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
O
OpenXG-RAN
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Analytics
Analytics
CI / CD
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
常顺宇
OpenXG-RAN
Commits
c51cb3f4
Commit
c51cb3f4
authored
Jan 11, 2021
by
ChiehChun
Committed by
Robert Schmidt
Feb 07, 2021
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Enable 2 UL slots
parent
dcd591bd
Changes
3
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
6 additions
and
6 deletions
+6
-6
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+2
-2
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+2
-2
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+2
-2
No files found.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @
c51cb3f4
...
...
@@ -363,7 +363,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
#define BIT(x) (1 << (x))
const
uint64_t
dlsch_in_slot_bitmap
=
BIT
(
1
)
|
BIT
(
2
)
|
BIT
(
3
)
|
BIT
(
4
)
|
BIT
(
5
)
|
BIT
(
6
)
|
BIT
(
11
)
|
BIT
(
12
)
|
BIT
(
13
)
|
BIT
(
14
)
|
BIT
(
15
)
|
BIT
(
16
);
const
uint64_t
ulsch_in_slot_bitmap
=
BIT
(
8
);
const
uint64_t
ulsch_in_slot_bitmap
=
BIT
(
8
)
|
BIT
(
1
8
);
memset
(
RC
.
nrmac
[
module_idP
]
->
cce_list
[
bwp_id
][
0
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
// coreset0
memset
(
RC
.
nrmac
[
module_idP
]
->
cce_list
[
bwp_id
][
1
],
0
,
MAX_NUM_CCE
*
sizeof
(
int
));
// coresetid 1
...
...
@@ -425,7 +425,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
}
// This schedules the DCI for Uplink and subsequently PUSCH
if
(
slot
<
10
)
{
{
nr_schedule_ulsch
(
module_idP
,
frame
,
slot
,
num_slots_per_tdd
,
nr_ulmix_slots
,
ulsch_in_slot_bitmap
);
}
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @
c51cb3f4
...
...
@@ -401,8 +401,8 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id,
tda
,
tdaList
->
list
.
count
);
int
K2
=
get_K2
(
sched_ctrl
->
active_ubwp
,
tda
,
mu
);
const
int
sched_frame
=
frame
+
(
slot
+
K2
>=
n
um_slots_per_tdd
);
const
int
sched_slot
=
(
slot
+
K2
)
%
n
um_slots_per_tdd
;
const
int
sched_frame
=
frame
+
(
slot
+
K2
>=
n
r_slots_per_frame
[
mu
]
);
const
int
sched_slot
=
(
slot
+
K2
)
%
n
r_slots_per_frame
[
mu
]
;
/* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE
* limitations). Note that if K2 or the TDD configuration is changed, below
* conditions might exclude each other and never be true */
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @
c51cb3f4
...
...
@@ -781,8 +781,8 @@ bool nr_simple_ulsch_preprocessor(module_id_t module_id,
tdaList
->
list
.
count
);
int
K2
=
get_K2
(
sched_ctrl
->
active_ubwp
,
tda
,
mu
);
const
int
sched_frame
=
frame
+
(
slot
+
K2
>=
n
um_slots_per_tdd
);
const
int
sched_slot
=
(
slot
+
K2
)
%
n
um_slots_per_tdd
;
const
int
sched_frame
=
frame
+
(
slot
+
K2
>=
n
r_slots_per_frame
[
mu
]
);
const
int
sched_slot
=
(
slot
+
K2
)
%
n
r_slots_per_frame
[
mu
]
;
if
(
!
is_xlsch_in_slot
(
ulsch_in_slot_bitmap
,
sched_slot
))
return
false
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment