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Commit 0a8e1b49 authored by francescomani's avatar francescomani
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adapt VRB maps to multiple beams in a period

parent c31d250d
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Showing with 173 additions and 114 deletions
openair1/SIMULATION/NR_PHY/dlsim.c
View file @ 0a8e1b49
......@@ -153,6 +153,7 @@ void nr_dlsim_preprocessor(module_id_t module_id,
/* CC_id = */ 0,
sched_ctrl->aggregation_level,
nr_of_candidates,
0,
&sched_ctrl->sched_pdcch,
sched_ctrl->coreset,
Y);
......
openair2/LAYER2/NR_MAC_gNB/config.c
View file @ 0a8e1b49
......@@ -625,11 +625,16 @@ void nr_mac_config_scc(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, c
const int NTN_gNB_Koffset = get_NTN_Koffset(scc);
const int n = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
const int size = n << (int)ceil(log2((NTN_gNB_Koffset + 13) / n + 1)); // 13 is upper limit for max_fb_time
nrmac->vrb_map_UL_size = size;
nrmac->common_channels[0].vrb_map_UL = calloc(size * MAX_BWP_SIZE, sizeof(uint16_t));
AssertFatal(nrmac->common_channels[0].vrb_map_UL,
"could not allocate memory for RC.nrmac[]->common_channels[0].vrb_map_UL\n");
int num_beams = 1;
if(nrmac->beam_info.beam_allocation)
num_beams = nrmac->beam_info.beams_per_period;
for (int i = 0; i < num_beams; i++) {
nrmac->common_channels[0].vrb_map_UL[i] = calloc(size * MAX_BWP_SIZE, sizeof(uint16_t));
AssertFatal(nrmac->common_channels[0].vrb_map_UL[i],
"could not allocate memory for RC.nrmac[]->common_channels[0].vrb_map_UL[%d]\n", i);
}
nrmac->UL_tti_req_ahead_size = size;
nrmac->UL_tti_req_ahead[0] = calloc(size, sizeof(nfapi_nr_ul_tti_request_t));
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @ 0a8e1b49
......@@ -234,17 +234,20 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_
}
for (int CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
//mbsfn_status[CC_id] = 0;
int num_beams = 1;
if(gNB->beam_info.beam_allocation)
num_beams = gNB->beam_info.beams_per_period;
// clear vrb_maps
memset(cc[CC_id].vrb_map, 0, sizeof(uint16_t) * MAX_BWP_SIZE);
for (int i = 0; i < num_beams; i++)
memset(cc[CC_id].vrb_map[i], 0, sizeof(uint16_t) * MAX_BWP_SIZE);
// clear last scheduled slot's content (only)!
const int num_slots = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
const int size = gNB->vrb_map_UL_size;
const int prev_slot = frame * num_slots + slot + size - 1;
uint16_t *vrb_map_UL = cc[CC_id].vrb_map_UL;
memcpy(&vrb_map_UL[prev_slot % size * MAX_BWP_SIZE], &gNB->ulprbbl, sizeof(uint16_t) * MAX_BWP_SIZE);
for (int i = 0; i < num_beams; i++) {
uint16_t *vrb_map_UL = cc[CC_id].vrb_map_UL[i];
memcpy(&vrb_map_UL[prev_slot % size * MAX_BWP_SIZE], &gNB->ulprbbl, sizeof(uint16_t) * MAX_BWP_SIZE);
}
clear_nr_nfapi_information(gNB, CC_id, frame, slot, &sched_info->DL_req, &sched_info->TX_req, &sched_info->UL_dci_req);
}
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
View file @ 0a8e1b49
......@@ -89,13 +89,18 @@ static void schedule_ssb(frame_t frame,
LOG_D(MAC,"Scheduling ssb %d at frame %d and slot %d\n",i_ssb,frame,slot);
}
static void fill_ssb_vrb_map(NR_COMMON_channels_t *cc, int rbStart, int ssb_subcarrier_offset, uint16_t symStart, int CC_id)
static void fill_ssb_vrb_map(NR_COMMON_channels_t *cc,
int rbStart,
int ssb_subcarrier_offset,
uint16_t symStart,
int CC_id,
int beam)
{
AssertFatal(*cc->ServingCellConfigCommon->ssbSubcarrierSpacing !=
NR_SubcarrierSpacing_kHz240,
"240kHZ subcarrier won't work with current VRB map because a single SSB might be across 2 slots\n");
uint16_t *vrb_map = cc[CC_id].vrb_map;
uint16_t *vrb_map = cc[CC_id].vrb_map[beam];
const int extra_prb = ssb_subcarrier_offset > 0;
for (int rb = 0; rb < 20 + extra_prb; rb++)
vrb_map[rbStart + rb] = SL_to_bitmap(symStart % NR_NUMBER_OF_SYMBOLS_PER_SLOT, 4);
......@@ -181,7 +186,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
AssertFatal(beam.idx >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb);
const int prb_offset = offset_pointa >> scs;
schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, ssbSubcarrierOffset, offset_pointa, mib_pdu);
fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset, ssb_start_symbol, CC_id);
fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset, ssb_start_symbol, CC_id, beam.idx);
if (get_softmodem_params()->sa == 1) {
get_type0_PDCCH_CSS_config_parameters(&gNB->type0_PDCCH_CSS_config[i_ssb],
frameP,
......@@ -212,7 +217,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
AssertFatal(beam.idx >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb);
const int prb_offset = offset_pointa >> scs;
schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, ssbSubcarrierOffset, offset_pointa, mib_pdu);
fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset, ssb_start_symbol, CC_id);
fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset, ssb_start_symbol, CC_id, beam.idx);
if (get_softmodem_params()->sa == 1) {
get_type0_PDCCH_CSS_config_parameters(&gNB->type0_PDCCH_CSS_config[i_ssb],
frameP,
......@@ -243,7 +248,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
AssertFatal(beam.idx >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb);
const int prb_offset = offset_pointa >> (scs-2); // reference 60kHz
schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, ssbSubcarrierOffset, offset_pointa, mib_pdu);
fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset >> (scs - 2), ssb_start_symbol, CC_id);
fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset >> (scs - 2), ssb_start_symbol, CC_id, beam.idx);
if (get_softmodem_params()->sa == 1) {
get_type0_PDCCH_CSS_config_parameters(&gNB->type0_PDCCH_CSS_config[i_ssb],
frameP,
......@@ -278,12 +283,13 @@ static uint32_t schedule_control_sib1(module_id_t module_id,
NR_pdsch_dmrs_t *dmrs_parms,
NR_tda_info_t *tda_info,
uint8_t candidate_idx,
int beam,
uint16_t num_total_bytes)
{
gNB_MAC_INST *gNB_mac = RC.nrmac[module_id];
NR_COMMON_channels_t *cc = &gNB_mac->common_channels[CC_id];
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
uint16_t *vrb_map = cc->vrb_map;
uint16_t *vrb_map = cc->vrb_map[beam];
if (gNB_mac->sched_ctrlCommon == NULL){
LOG_D(NR_MAC,"schedule_control_common: Filling nr_mac->sched_ctrlCommon\n");
......@@ -322,6 +328,7 @@ static uint32_t schedule_control_sib1(module_id_t module_id,
CC_id,
gNB_mac->sched_ctrlCommon->aggregation_level,
nr_of_candidates,
beam,
&gNB_mac->sched_ctrlCommon->sched_pdcch,
gNB_mac->sched_ctrlCommon->coreset,
0);
......@@ -383,7 +390,8 @@ static uint32_t schedule_control_sib1(module_id_t module_id,
CC_id,
&gNB_mac->sched_ctrlCommon->sched_pdcch,
gNB_mac->sched_ctrlCommon->cce_index,
gNB_mac->sched_ctrlCommon->aggregation_level);
gNB_mac->sched_ctrlCommon->aggregation_level,
beam);
for (int rb = 0; rb < pdsch->rbSize; rb++) {
vrb_map[rb + rbStart] |= SL_to_bitmap(tda_info->startSymbolIndex, tda_info->nrOfSymbols);
}
......@@ -601,6 +609,7 @@ void schedule_nr_sib1(module_id_t module_idP,
&dmrs_parms,
&tda_info,
candidate_idx,
beam.idx,
cc->sib1_bcch_length);
nfapi_nr_dl_tti_request_body_t *dl_req = &DL_req->dl_tti_request_body;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @ 0a8e1b49
......@@ -543,10 +543,14 @@ static bool allocate_dl_retransmission(module_id_t module_id,
retInfo->tda_info = temp_tda;
}
// TODO properly set the beam index (currently only done for RA)
int beam = 0;
/* Find a free CCE */
int CCEIndex = get_cce_index(nr_mac,
CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level,
beam,
sched_ctrl->search_space,
sched_ctrl->coreset,
&sched_ctrl->sched_pdcch,
......@@ -565,8 +569,7 @@ static bool allocate_dl_retransmission(module_id_t module_id,
int alloc = -1;
if (!get_FeedbackDisabled(UE->sc_info.downlinkHARQ_FeedbackDisabled_r17, current_harq_pid)) {
int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, ul_bwp->pucch_Config, CCEIndex);
// TODO properly set the beam index (currently only done for RA)
alloc = nr_acknack_scheduling(nr_mac, UE, frame, slot, 0, r_pucch, 0);
alloc = nr_acknack_scheduling(nr_mac, UE, frame, slot, beam, r_pucch, 0);
if (alloc < 0) {
LOG_D(NR_MAC, "[UE %04x][%4d.%2d] could not find PUCCH for DL DCI retransmission\n",
UE->rnti,
......@@ -581,7 +584,8 @@ static bool allocate_dl_retransmission(module_id_t module_id,
/* CC_id = */ 0,
&sched_ctrl->sched_pdcch,
CCEIndex,
sched_ctrl->aggregation_level);
sched_ctrl->aggregation_level,
beam);
/* just reuse from previous scheduling opportunity, set new start RB */
sched_ctrl->sched_pdsch = *retInfo;
sched_ctrl->sched_pdsch.rbStart = rbStart;
......@@ -737,9 +741,13 @@ static void pf_dl(module_id_t module_id,
NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
sched_pdsch->dl_harq_pid = sched_ctrl->available_dl_harq.head;
// TODO properly set the beam index (currently only done for RA)
int beam = 0;
int CCEIndex = get_cce_index(mac,
CC_id, slot, iterator->UE->rnti,
&sched_ctrl->aggregation_level,
beam,
sched_ctrl->search_space,
sched_ctrl->coreset,
&sched_ctrl->sched_pdcch,
......@@ -759,8 +767,7 @@ static void pf_dl(module_id_t module_id,
int alloc = -1;
if (!get_FeedbackDisabled(iterator->UE->sc_info.downlinkHARQ_FeedbackDisabled_r17, sched_pdsch->dl_harq_pid)) {
int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, ul_bwp->pucch_Config, CCEIndex);
// TODO properly set the beam index (currently only done for RA)
alloc = nr_acknack_scheduling(mac, iterator->UE, frame, slot, 0, r_pucch, 0);
alloc = nr_acknack_scheduling(mac, iterator->UE, frame, slot, beam, r_pucch, 0);
if (alloc < 0) {
LOG_D(NR_MAC, "[UE %04x][%4d.%2d] could not find PUCCH for DL DCI\n",
rnti,
......@@ -776,7 +783,8 @@ static void pf_dl(module_id_t module_id,
/* CC_id = */ 0,
&sched_ctrl->sched_pdcch,
CCEIndex,
sched_ctrl->aggregation_level);
sched_ctrl->aggregation_level,
beam);
/* MCS has been set above */
sched_pdsch->time_domain_allocation = get_dl_tda(mac, scc, slot);
......@@ -876,7 +884,8 @@ static void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_
const uint16_t BWPStart = current_BWP->BWPStart;
const uint16_t slbitmap = SL_to_bitmap(startSymbolIndex, nrOfSymbols);
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
// TODO improve handling of beam in vrb_map (for now just using 0)
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map[0];
uint16_t rballoc_mask[bwpSize];
int n_rb_sched = 0;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @ 0a8e1b49
......@@ -85,11 +85,14 @@ void nr_preprocessor_phytest(module_id_t module_id,
const int bwpSize = dl_bwp->BWPSize;
const int BWPStart = dl_bwp->BWPStart;
// TODO implement beam procedures for phy-test mode
int beam = 0;
int rbStart = 0;
int rbSize = 0;
if (target_dl_bw>bwpSize)
target_dl_bw = bwpSize;
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map[beam];
/* loop ensures that we allocate exactly target_dl_bw, or return */
while (true) {
/* advance to first free RB */
......@@ -133,6 +136,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
int CCEIndex = get_cce_index(RC.nrmac[module_id],
CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level,
beam,
sched_ctrl->search_space,
sched_ctrl->coreset,
&sched_ctrl->sched_pdcch,
......@@ -166,7 +170,8 @@ void nr_preprocessor_phytest(module_id_t module_id,
CC_id,
&sched_ctrl->sched_pdcch,
CCEIndex,
sched_ctrl->aggregation_level);
sched_ctrl->aggregation_level,
beam);
//AssertFatal(alloc,
// "could not find uplink slot for PUCCH (RNTI %04x@%d.%d)!\n",
......@@ -282,8 +287,12 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
return false;
sched_ctrl->sched_pusch.tda_info = tda_info;
sched_ctrl->sched_pusch.time_domain_allocation = tda;
// TODO implement beam procedures for phy-test mode
int beam = 0;
const int buffer_index = ul_buffer_index(sched_frame, sched_slot, mu, nr_mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[buffer_index * MAX_BWP_SIZE];
uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[beam][buffer_index * MAX_BWP_SIZE];
for (int i = rbStart; i < rbStart + rbSize; ++i) {
if ((vrb_map_UL[i+BWPStart] & SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols)) != 0) {
LOG_E(MAC, "%4d.%2d RB %d is already reserved, cannot schedule UE\n", frame, slot, i);
......@@ -297,6 +306,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
int CCEIndex = get_cce_index(nr_mac,
CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level,
beam,
sched_ctrl->search_space,
sched_ctrl->coreset,
&sched_ctrl->sched_pdcch,
......@@ -348,7 +358,8 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
CC_id,
&sched_ctrl->sched_pdcch,
CCEIndex,
sched_ctrl->aggregation_level);
sched_ctrl->aggregation_level,
beam);
for (int rb = rbStart; rb < rbStart + rbSize; rb++)
vrb_map_UL[rb+BWPStart] |= SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols);
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ 0a8e1b49
......@@ -501,11 +501,12 @@ int find_pdcch_candidate(const gNB_MAC_INST *mac,
int cc_id,
int aggregation,
int nr_of_candidates,
int beam_idx,
const NR_sched_pdcch_t *pdcch,
const NR_ControlResourceSet_t *coreset,
uint32_t Y)
{
const uint16_t *vrb_map = mac->common_channels[cc_id].vrb_map;
const uint16_t *vrb_map = mac->common_channels[cc_id].vrb_map[beam_idx];
const int N_ci = 0;
const int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol
......@@ -546,6 +547,7 @@ int get_cce_index(const gNB_MAC_INST *nrmac,
const int slot,
const rnti_t rnti,
uint8_t *aggregation_level,
int beam_idx,
const NR_SearchSpace_t *ss,
const NR_ControlResourceSet_t *coreset,
NR_sched_pdcch_t *sched_pdcch,
......@@ -567,6 +569,7 @@ int get_cce_index(const gNB_MAC_INST *nrmac,
CC_id,
*aggregation_level,
nr_of_candidates,
beam_idx,
sched_pdcch,
coreset,
Y);
......@@ -577,9 +580,10 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
int CC_id,
NR_sched_pdcch_t *pdcch,
int first_cce,
int aggregation){
uint16_t *vrb_map = mac->common_channels[CC_id].vrb_map;
int aggregation,
int beam)
{
uint16_t *vrb_map = mac->common_channels[CC_id].vrb_map[beam];
int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol
int L = pdcch->RegBundleSize;
......@@ -2725,7 +2729,9 @@ void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, int n_slo
NR_SCHED_ENSURE_LOCKED(&gNB_mac->sched_lock);
uint16_t *vrb_map = gNB_mac->common_channels[CC_id].vrb_map;
// TODO implement beam procedures
int beam = 0;
uint16_t *vrb_map = gNB_mac->common_channels[CC_id].vrb_map[beam];
UE_info->sched_csirs = 0;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_srs.c
View file @ 0a8e1b49
......@@ -470,7 +470,8 @@ static void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu,
srs_pdu->beamforming.prg_size = 1;
}
uint16_t *vrb_map_UL = &RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[buffer_index * MAX_BWP_SIZE];
// TODO properly use beam allocation
uint16_t *vrb_map_UL = &RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[0][buffer_index * MAX_BWP_SIZE];
uint64_t mask = SL_to_bitmap(13 - srs_pdu->time_start_position, srs_pdu->num_symbols);
for (int i = 0; i < srs_pdu->bwp_size; ++i)
vrb_map_UL[i + srs_pdu->bwp_start] |= mask;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c
View file @ 0a8e1b49
......@@ -279,8 +279,9 @@ void nr_csi_meas_reporting(int Mod_idP,
int bwp_start = ul_bwp->BWPStart;
// going through the list of PUCCH resources to find the one indexed by resource_id
int beam_idx = 0; // TODO proper beam allocation
const int index = ul_buffer_index(sched_frame, sched_slot, ul_bwp->scs, nrmac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nrmac->common_channels[0].vrb_map_UL[index * MAX_BWP_SIZE];
uint16_t *vrb_map_UL = &nrmac->common_channels[0].vrb_map_UL[beam_idx][index * MAX_BWP_SIZE];
const int m = pucch_Config->resourceToAddModList->list.count;
for (int j = 0; j < m; j++) {
NR_PUCCH_Resource_t *pucchres = pucch_Config->resourceToAddModList->list.array[j];
......@@ -1329,24 +1330,27 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac,
else { // unoccupied occasion
// checking if in ul_slot the resources potentially to be assigned to this PUCCH are available
set_pucch_allocation(ul_bwp, r_pucch, bwp_size, curr_pucch);
const int index = ul_buffer_index(pucch_frame, pucch_slot, ul_bwp->scs, mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &mac->common_channels[CC_id].vrb_map_UL[index * MAX_BWP_SIZE];
bool ret = test_pucch0_vrb_occupation(curr_pucch,
vrb_map_UL,
bwp_start,
bwp_size);
if(!ret) {
LOG_D(NR_MAC,
"DL %4d.%2d, UL_ACK %4d.%2d PRB resources for this occasion are already occupied, move to the following occasion\n",
frame, slot, pucch_frame, pucch_slot);
continue;
}
NR_beam_alloc_t beam = beam_allocation_procedure(&mac->beam_info, pucch_frame, pucch_slot, beam_index, n_slots_frame);
if (beam.idx < 0) {
LOG_D(NR_MAC,
"DL %4d.%2d, UL_ACK %4d.%2d beam resources for this occasion are already occupied, move to the following occasion\n",
frame, slot, pucch_frame, pucch_slot);
// TODO add reset beam status
frame,
slot,
pucch_frame,
pucch_slot);
continue;
}
const int index = ul_buffer_index(pucch_frame, pucch_slot, ul_bwp->scs, mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &mac->common_channels[CC_id].vrb_map_UL[beam.idx][index * MAX_BWP_SIZE];
bool ret = test_pucch0_vrb_occupation(curr_pucch, vrb_map_UL, bwp_start, bwp_size);
if(!ret) {
LOG_D(NR_MAC,
"DL %4d.%2d, UL_ACK %4d.%2d PRB resources for this occasion are already occupied, move to the following occasion\n",
frame,
slot,
pucch_frame,
pucch_slot);
reset_beam_status(&mac->beam_info, pucch_frame, pucch_slot, beam_index, n_slots_frame, beam.new_beam);
continue;
}
// allocating a new PUCCH structure for this occasion
......@@ -1438,8 +1442,9 @@ void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t SFN, sub_frame_t slot)
continue;
}
else {
int beam_idx = 0; // TODO proper beam allocation
const int index = ul_buffer_index(SFN, slot, ul_bwp->scs, nrmac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nrmac->common_channels[CC_id].vrb_map_UL[index * MAX_BWP_SIZE];
uint16_t *vrb_map_UL = &nrmac->common_channels[CC_id].vrb_map_UL[beam_idx][index * MAX_BWP_SIZE];
const int bwp_start = ul_bwp->BWPStart;
const int bwp_size = ul_bwp->BWPSize;
set_pucch_allocation(ul_bwp, -1, bwp_size, curr_pucch);
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @ 0a8e1b49
......@@ -1708,6 +1708,7 @@ static bool allocate_ul_retransmission(gNB_MAC_INST *nrmac,
int CCEIndex = get_cce_index(nrmac,
CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level,
0, // TODO use beam index
sched_ctrl->search_space,
sched_ctrl->coreset,
&sched_ctrl->sched_pdcch,
......@@ -1725,7 +1726,8 @@ static bool allocate_ul_retransmission(gNB_MAC_INST *nrmac,
CC_id,
&sched_ctrl->sched_pdcch,
CCEIndex,
sched_ctrl->aggregation_level);
sched_ctrl->aggregation_level,
0); // TODO use beam index when implemented
/* frame/slot in sched_pusch has been set previously. In the following, we
* overwrite the information in the retransmission information before storing
......@@ -1866,6 +1868,7 @@ static void pf_ul(module_id_t module_id,
int CCEIndex = get_cce_index(nrmac,
CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level,
0, // TODO use beam index
sched_ctrl->search_space,
sched_ctrl->coreset,
&sched_ctrl->sched_pdcch,
......@@ -1912,7 +1915,8 @@ static void pf_ul(module_id_t module_id,
CC_id,
&sched_ctrl->sched_pdcch,
CCEIndex,
sched_ctrl->aggregation_level);
sched_ctrl->aggregation_level,
0); // TODO use beam index);
NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
sched_pusch->mcs = min(nrmac->min_grant_mcs, sched_pusch->mcs);
......@@ -1983,6 +1987,7 @@ static void pf_ul(module_id_t module_id,
int CCEIndex = get_cce_index(nrmac,
CC_id, slot, iterator->UE->rnti,
&sched_ctrl->aggregation_level,
0, // TODO use beam index
sched_ctrl->search_space,
sched_ctrl->coreset,
&sched_ctrl->sched_pdcch,
......@@ -2089,7 +2094,8 @@ static void pf_ul(module_id_t module_id,
CC_id,
&sched_ctrl->sched_pdcch,
CCEIndex,
sched_ctrl->aggregation_level);
sched_ctrl->aggregation_level,
0); // TODO use beam index);
n_rb_sched -= sched_pusch->rbSize;
for (int rb = 0; rb < sched_ctrl->sched_pusch.rbSize; rb++)
......@@ -2155,7 +2161,8 @@ static bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_
* vrb_map_UL) overlap with the "default" tda and exclude those RBs.
* Calculate largest contiguous RBs */
const int index = ul_buffer_index(sched_frame, sched_slot, mu, nr_mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[index * MAX_BWP_SIZE];
// TODO improve handling of beam in vrb_map (for now just using 0)
uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[0][index * MAX_BWP_SIZE];
const uint16_t bwpSize = current_BWP->BWPSize;
const uint16_t bwpStart = current_BWP->BWPStart;
......
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @ 0a8e1b49
......@@ -215,6 +215,7 @@ int find_pdcch_candidate(const gNB_MAC_INST *mac,
int cc_id,
int aggregation,
int nr_of_candidates,
int beam_idx,
const NR_sched_pdcch_t *pdcch,
const NR_ControlResourceSet_t *coreset,
uint32_t Y);
......@@ -223,7 +224,8 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
int CC_id,
NR_sched_pdcch_t *pdcch,
int first_cce,
int aggregation);
int aggregation,
int beam);
void fill_dci_pdu_rel15(const NR_UE_ServingCell_Info_t *servingCellInfo,
const NR_UE_DL_BWP_t *current_DL_BWP,
......@@ -397,6 +399,7 @@ int get_cce_index(const gNB_MAC_INST *nrmac,
const int slot,
const rnti_t rnti,
uint8_t *aggregation_level,
int beam_idx,
const NR_SearchSpace_t *ss,
const NR_ControlResourceSet_t *coreset,
NR_sched_pdcch_t *sched_pdcch,
......
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @ 0a8e1b49
......@@ -100,6 +100,7 @@
#define MAX_NUM_OF_SSB 64
#define MAX_NUM_NR_PRACH_PREAMBLES 64
#define MIN_NUM_PRBS_TO_SCHEDULE 5
#define MAX_NUM_BEAM_PERIODS 4
extern const uint8_t nr_rv_round_map[4];
......@@ -270,10 +271,10 @@ typedef struct {
/// Template for RA computations
NR_RA_t ra[NR_NB_RA_PROC_MAX];
/// VRB map for common channels
uint16_t vrb_map[275];
uint16_t vrb_map[MAX_NUM_BEAM_PERIODS][275];
/// VRB map for common channels and PUSCH, dynamically allocated because
/// length depends on number of slots and RBs
uint16_t *vrb_map_UL;
uint16_t *vrb_map_UL[MAX_NUM_BEAM_PERIODS];
///Number of active SSBs
int num_active_ssb;
//Total available prach occasions per configuration period
......
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