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OpenXG-RAN
Commits
82c4380a
Commit
82c4380a
authored
Nov 20, 2020
by
Francesco Mani
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uci mac functions in a new file
parent
40141270
Changes
6
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6 changed files
with
585 additions
and
545 deletions
+585
-545
cmake_targets/CMakeLists.txt
cmake_targets/CMakeLists.txt
+1
-0
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+0
-55
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+0
-94
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+0
-396
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c
+581
-0
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+3
-0
No files found.
cmake_targets/CMakeLists.txt
View file @
82c4380a
...
...
@@ -2031,6 +2031,7 @@ set (MAC_NR_SRC
${
NR_GNB_MAC_DIR
}
/gNB_scheduler_ulsch.c
${
NR_GNB_MAC_DIR
}
/gNB_scheduler_primitives.c
${
NR_GNB_MAC_DIR
}
/gNB_scheduler_phytest.c
${
NR_GNB_MAC_DIR
}
/gNB_scheduler_uci.c
${
NR_GNB_MAC_DIR
}
/gNB_scheduler_RA.c
)
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @
82c4380a
...
...
@@ -337,61 +337,6 @@ void nr_schedule_pusch(int Mod_idP,
}
}
void
nr_schedule_pucch
(
int
Mod_idP
,
int
UE_id
,
int
nr_ulmix_slots
,
frame_t
frameP
,
sub_frame_t
slotP
)
{
uint16_t
O_csi
,
O_ack
,
O_uci
;
uint8_t
O_sr
=
0
;
// no SR in PUCCH implemented for now
NR_ServingCellConfigCommon_t
*
scc
=
RC
.
nrmac
[
Mod_idP
]
->
common_channels
->
ServingCellConfigCommon
;
NR_UE_info_t
*
UE_info
=
&
RC
.
nrmac
[
Mod_idP
]
->
UE_info
;
AssertFatal
(
UE_info
->
active
[
UE_id
],
"Cannot find UE_id %d is not active
\n
"
,
UE_id
);
NR_CellGroupConfig_t
*
secondaryCellGroup
=
UE_info
->
secondaryCellGroup
[
UE_id
];
int
bwp_id
=
1
;
NR_BWP_Uplink_t
*
ubwp
=
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
->
uplinkBWP_ToAddModList
->
list
.
array
[
bwp_id
-
1
];
nfapi_nr_ul_tti_request_t
*
UL_tti_req
=
&
RC
.
nrmac
[
Mod_idP
]
->
UL_tti_req
[
0
];
NR_sched_pucch
*
curr_pucch
;
for
(
int
k
=
0
;
k
<
nr_ulmix_slots
;
k
++
)
{
for
(
int
l
=
0
;
l
<
2
;
l
++
)
{
curr_pucch
=
&
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pucch
[
k
][
l
];
O_ack
=
curr_pucch
->
dai_c
;
O_csi
=
curr_pucch
->
csi_bits
;
O_uci
=
O_ack
+
O_csi
+
O_sr
;
if
((
O_uci
>
0
)
&&
(
frameP
==
curr_pucch
->
frame
)
&&
(
slotP
==
curr_pucch
->
ul_slot
))
{
UL_tti_req
->
SFN
=
curr_pucch
->
frame
;
UL_tti_req
->
Slot
=
curr_pucch
->
ul_slot
;
UL_tti_req
->
pdus_list
[
UL_tti_req
->
n_pdus
].
pdu_type
=
NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE
;
UL_tti_req
->
pdus_list
[
UL_tti_req
->
n_pdus
].
pdu_size
=
sizeof
(
nfapi_nr_pucch_pdu_t
);
nfapi_nr_pucch_pdu_t
*
pucch_pdu
=
&
UL_tti_req
->
pdus_list
[
UL_tti_req
->
n_pdus
].
pucch_pdu
;
memset
(
pucch_pdu
,
0
,
sizeof
(
nfapi_nr_pucch_pdu_t
));
UL_tti_req
->
n_pdus
+=
1
;
LOG_D
(
MAC
,
"Scheduling pucch reception for frame %d slot %d with (%d, %d, %d) (SR ACK, CSI) bits
\n
"
,
frameP
,
slotP
,
O_sr
,
O_ack
,
curr_pucch
->
csi_bits
);
nr_configure_pucch
(
pucch_pdu
,
scc
,
ubwp
,
UE_info
->
rnti
[
UE_id
],
curr_pucch
->
resource_indicator
,
O_csi
,
O_ack
,
O_sr
);
memset
((
void
*
)
&
UE_info
->
UE_sched_ctrl
[
UE_id
].
sched_pucch
[
k
][
l
],
0
,
sizeof
(
NR_sched_pucch
));
}
}
}
}
bool
is_xlsch_in_slot
(
uint64_t
bitmap
,
sub_frame_t
slot
)
{
return
(
bitmap
>>
slot
)
&
0x01
;
}
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @
82c4380a
...
...
@@ -343,100 +343,6 @@ int nr_generate_dlsch_pdu(module_id_t module_idP,
return
offset
;
}
void
nr_rx_acknack
(
nfapi_nr_uci_pusch_pdu_t
*
uci_pusch
,
nfapi_nr_uci_pucch_pdu_format_0_1_t
*
uci_01
,
nfapi_nr_uci_pucch_pdu_format_2_3_4_t
*
uci_234
,
NR_UL_IND_t
*
UL_info
,
NR_UE_sched_ctrl_t
*
sched_ctrl
,
NR_mac_stats_t
*
stats
)
{
// TODO
int
max_harq_rounds
=
4
;
// TODO define macro
if
(
uci_01
!=
NULL
)
{
// handle harq
int
harq_idx_s
=
0
;
// iterate over received harq bits
for
(
int
harq_bit
=
0
;
harq_bit
<
uci_01
->
harq
->
num_harq
;
harq_bit
++
)
{
// search for the right harq process
for
(
int
harq_idx
=
harq_idx_s
;
harq_idx
<
NR_MAX_NB_HARQ_PROCESSES
;
harq_idx
++
)
{
// if the gNB received ack with a good confidence
if
((
UL_info
->
slot
-
1
)
==
sched_ctrl
->
harq_processes
[
harq_idx
].
feedback_slot
)
{
if
((
uci_01
->
harq
->
harq_list
[
harq_bit
].
harq_value
==
1
)
&&
(
uci_01
->
harq
->
harq_confidence_level
==
0
))
{
// toggle NDI and reset round
sched_ctrl
->
harq_processes
[
harq_idx
].
ndi
^=
1
;
sched_ctrl
->
harq_processes
[
harq_idx
].
round
=
0
;
}
else
sched_ctrl
->
harq_processes
[
harq_idx
].
round
++
;
sched_ctrl
->
harq_processes
[
harq_idx
].
is_waiting
=
0
;
harq_idx_s
=
harq_idx
+
1
;
// if the max harq rounds was reached
if
(
sched_ctrl
->
harq_processes
[
harq_idx
].
round
==
max_harq_rounds
)
{
sched_ctrl
->
harq_processes
[
harq_idx
].
ndi
^=
1
;
sched_ctrl
->
harq_processes
[
harq_idx
].
round
=
0
;
stats
->
dlsch_errors
++
;
}
break
;
}
// if feedback slot processing is aborted
else
if
(((
UL_info
->
slot
-
1
)
>
sched_ctrl
->
harq_processes
[
harq_idx
].
feedback_slot
)
&&
(
sched_ctrl
->
harq_processes
[
harq_idx
].
is_waiting
))
{
sched_ctrl
->
harq_processes
[
harq_idx
].
round
++
;
if
(
sched_ctrl
->
harq_processes
[
harq_idx
].
round
==
max_harq_rounds
)
{
sched_ctrl
->
harq_processes
[
harq_idx
].
ndi
^=
1
;
sched_ctrl
->
harq_processes
[
harq_idx
].
round
=
0
;
}
sched_ctrl
->
harq_processes
[
harq_idx
].
is_waiting
=
0
;
}
}
}
}
if
(
uci_234
!=
NULL
)
{
int
harq_idx_s
=
0
;
int
acknack
;
// iterate over received harq bits
for
(
int
harq_bit
=
0
;
harq_bit
<
uci_234
->
harq
.
harq_bit_len
;
harq_bit
++
)
{
acknack
=
((
uci_234
->
harq
.
harq_payload
[
harq_bit
>>
3
])
>>
harq_bit
)
&
0x01
;
for
(
int
harq_idx
=
harq_idx_s
;
harq_idx
<
NR_MAX_NB_HARQ_PROCESSES
-
1
;
harq_idx
++
)
{
// if the gNB received ack with a good confidence or if the max harq rounds was reached
if
((
UL_info
->
slot
-
1
)
==
sched_ctrl
->
harq_processes
[
harq_idx
].
feedback_slot
)
{
// TODO add some confidence level for when there is no CRC
if
((
uci_234
->
harq
.
harq_crc
!=
1
)
&&
acknack
)
{
// toggle NDI and reset round
sched_ctrl
->
harq_processes
[
harq_idx
].
ndi
^=
1
;
sched_ctrl
->
harq_processes
[
harq_idx
].
round
=
0
;
}
else
sched_ctrl
->
harq_processes
[
harq_idx
].
round
++
;
sched_ctrl
->
harq_processes
[
harq_idx
].
is_waiting
=
0
;
harq_idx_s
=
harq_idx
+
1
;
// if the max harq rounds was reached
if
(
sched_ctrl
->
harq_processes
[
harq_idx
].
round
==
max_harq_rounds
)
{
sched_ctrl
->
harq_processes
[
harq_idx
].
ndi
^=
1
;
sched_ctrl
->
harq_processes
[
harq_idx
].
round
=
0
;
stats
->
dlsch_errors
++
;
}
break
;
}
// if feedback slot processing is aborted
else
if
(((
UL_info
->
slot
-
1
)
>
sched_ctrl
->
harq_processes
[
harq_idx
].
feedback_slot
)
&&
(
sched_ctrl
->
harq_processes
[
harq_idx
].
is_waiting
))
{
sched_ctrl
->
harq_processes
[
harq_idx
].
round
++
;
if
(
sched_ctrl
->
harq_processes
[
harq_idx
].
round
==
max_harq_rounds
)
{
sched_ctrl
->
harq_processes
[
harq_idx
].
ndi
^=
1
;
sched_ctrl
->
harq_processes
[
harq_idx
].
round
=
0
;
}
sched_ctrl
->
harq_processes
[
harq_idx
].
is_waiting
=
0
;
}
}
}
}
}
int
getNrOfSymbols
(
NR_BWP_Downlink_t
*
bwp
,
int
tda
)
{
struct
NR_PDSCH_TimeDomainResourceAllocationList
*
tdaList
=
bwp
->
bwp_Common
->
pdsch_ConfigCommon
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
;
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
82c4380a
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c
0 → 100644
View file @
82c4380a
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @
82c4380a
...
...
@@ -183,6 +183,9 @@ void nr_schedule_pucch(int Mod_idP,
frame_t
frameP
,
sub_frame_t
slotP
);
void
csi_period_offset
(
NR_CSI_ReportConfig_t
*
csirep
,
int
*
period
,
int
*
offset
);
void
nr_csi_meas_reporting
(
int
Mod_idP
,
int
UE_id
,
frame_t
frameP
,
...
...
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