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Commit a0746181 authored by Laurent THOMAS's avatar Laurent THOMAS Committed by Robert Schmidt
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NR UE: Implement DCI format 11 type0 for contiguous allocations

parent 74977924
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Showing with 71 additions and 37 deletions
common/utils/nr/nr_common.h
View file @ a0746181
...@@ -176,7 +176,16 @@ static inline int get_num_dmrs(uint16_t dmrs_mask ) ...@@ -176,7 +176,16 @@ static inline int get_num_dmrs(uint16_t dmrs_mask )
return(num_dmrs); return(num_dmrs);
} }
static __attribute__((always_inline)) inline int count_bits_set(uint64_t v) static inline int count_bits(uint8_t *arr, int sz)
{
AssertFatal(sz % sizeof(int) == 0, "to implement if needed\n");
int ret = 0;
for (uint *ptr = (uint *)arr; (uint8_t *)ptr < arr + sz; ptr++)
ret += __builtin_popcount(*ptr);
return ret;
}
static __attribute__((always_inline)) inline int count_bits64(uint64_t v)
{ {
return __builtin_popcountll(v); return __builtin_popcountll(v);
} }
......
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
View file @ a0746181
...@@ -494,19 +494,25 @@ static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, ...@@ -494,19 +494,25 @@ static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue,
// We handle only one CW now // We handle only one CW now
if (!(NR_MAX_NB_LAYERS>4)) { if (!(NR_MAX_NB_LAYERS>4)) {
NR_UE_DLSCH_t *dlsch0 = &dlsch[0]; NR_UE_DLSCH_t *dlsch0 = &dlsch[0];
int harq_pid = dlsch0->dlsch_config.harq_process_nbr; fapi_nr_dl_config_dlsch_pdu_rel15_t *dlschCfg = &dlsch0->dlsch_config;
int harq_pid = dlschCfg->harq_process_nbr;
// dlsch0_harq contains the previous transmissions data for this harq pid
NR_DL_UE_HARQ_t *dlsch0_harq = &ue->dl_harq_processes[0][harq_pid]; NR_DL_UE_HARQ_t *dlsch0_harq = &ue->dl_harq_processes[0][harq_pid];
uint16_t BWPStart = dlsch0->dlsch_config.BWPStart;
uint16_t pdsch_start_rb = dlsch0->dlsch_config.start_rb;
uint16_t pdsch_nb_rb = dlsch0->dlsch_config.number_rbs;
uint16_t s0 = dlsch0->dlsch_config.start_symbol;
uint16_t s1 = dlsch0->dlsch_config.number_symbols;
AssertFatal(dlsch0->dlsch_config.resource_alloc == 1, LOG_D(PHY,
"DLSCH resource allocation type0 not supported at PHY\n"); "[UE %d] nr_slot_rx %d, harq_pid %d (%d), BWP start %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask "
"%x, Nl %d\n",
LOG_D(PHY,"[UE %d] nr_slot_rx %d, harq_pid %d (%d), BWP start %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask %x, Nl %d\n", ue->Mod_id,
ue->Mod_id,nr_slot_rx,harq_pid,dlsch0_harq->status,BWPStart,pdsch_start_rb,pdsch_nb_rb,s0,s1,dlsch0->dlsch_config.dlDmrsSymbPos, dlsch0->Nl); nr_slot_rx,
harq_pid,
dlsch0_harq->status,
dlschCfg->BWPStart,
dlschCfg->start_rb,
dlschCfg->number_rbs,
dlschCfg->start_symbol,
dlschCfg->number_symbols,
dlschCfg->dlDmrsSymbPos,
dlsch0->Nl);
const uint32_t pdsch_est_size = ((ue->frame_parms.symbols_per_slot * ue->frame_parms.ofdm_symbol_size + 15) / 16) * 16; const uint32_t pdsch_est_size = ((ue->frame_parms.symbols_per_slot * ue->frame_parms.ofdm_symbol_size + 15) / 16) * 16;
__attribute__((aligned(32))) int32_t pdsch_dl_ch_estimates[ue->frame_parms.nb_antennas_rx * dlsch0->Nl][pdsch_est_size]; __attribute__((aligned(32))) int32_t pdsch_dl_ch_estimates[ue->frame_parms.nb_antennas_rx * dlsch0->Nl][pdsch_est_size];
...@@ -522,25 +528,26 @@ static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, ...@@ -522,25 +528,26 @@ static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue,
__attribute__((aligned(32))) int32_t rxdataF_comp[dlsch[0].Nl][ue->frame_parms.nb_antennas_rx][rx_size_symbol * NR_SYMBOLS_PER_SLOT]; __attribute__((aligned(32))) int32_t rxdataF_comp[dlsch[0].Nl][ue->frame_parms.nb_antennas_rx][rx_size_symbol * NR_SYMBOLS_PER_SLOT];
memset(rxdataF_comp, 0, sizeof(rxdataF_comp)); memset(rxdataF_comp, 0, sizeof(rxdataF_comp));
for (int m = s0; m < (s0 +s1); m++) { for (int m = dlschCfg->start_symbol; m < (dlschCfg->start_symbol + dlschCfg->number_symbols); m++) {
if (dlsch0->dlsch_config.dlDmrsSymbPos & (1 << m)) { if (dlschCfg->dlDmrsSymbPos & (1 << m)) {
for (int nl = 0; nl < dlsch0->Nl; nl++) { //for MIMO Config: it shall loop over no_layers for (int nl = 0; nl < dlsch0->Nl; nl++) { //for MIMO Config: it shall loop over no_layers
LOG_D(PHY,"PDSCH Channel estimation layer %d, slot %d, symbol %d\n", nl, nr_slot_rx, m); LOG_D(PHY,"PDSCH Channel estimation layer %d, slot %d, symbol %d\n", nl, nr_slot_rx, m);
nr_pdsch_channel_estimation(ue, nr_pdsch_channel_estimation(ue,
proc, proc,
nl, nl,
get_dmrs_port(nl,dlsch0->dlsch_config.dmrs_ports), get_dmrs_port(nl, dlschCfg->dmrs_ports),
m, m,
dlsch0->dlsch_config.nscid, dlschCfg->nscid,
dlsch0->dlsch_config.dlDmrsScramblingId, dlschCfg->dlDmrsScramblingId,
BWPStart, dlschCfg->BWPStart,
dlsch0->dlsch_config.dmrsConfigType, dlschCfg->dmrsConfigType,
dlsch0->dlsch_config.rb_offset, dlschCfg->rb_offset,
ue->frame_parms.first_carrier_offset+(BWPStart + pdsch_start_rb)*12, ue->frame_parms.first_carrier_offset + (dlschCfg->BWPStart + dlschCfg->start_rb) * 12,
pdsch_nb_rb, dlschCfg->number_rbs,
pdsch_est_size, pdsch_est_size,
pdsch_dl_ch_estimates, pdsch_dl_ch_estimates,
ue->frame_parms.samples_per_slot_wCP, rxdataF); ue->frame_parms.samples_per_slot_wCP,
rxdataF);
#if 0 #if 0
///LOG_M: the channel estimation ///LOG_M: the channel estimation
int nr_frame_rx = proc->frame_rx; int nr_frame_rx = proc->frame_rx;
...@@ -558,22 +565,22 @@ static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, ...@@ -558,22 +565,22 @@ static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue,
if (ue->chest_time == 1) { // averaging time domain channel estimates if (ue->chest_time == 1) { // averaging time domain channel estimates
nr_chest_time_domain_avg(&ue->frame_parms, nr_chest_time_domain_avg(&ue->frame_parms,
(int32_t **) pdsch_dl_ch_estimates, (int32_t **)pdsch_dl_ch_estimates,
dlsch0->dlsch_config.number_symbols, dlschCfg->number_symbols,
dlsch0->dlsch_config.start_symbol, dlschCfg->start_symbol,
dlsch0->dlsch_config.dlDmrsSymbPos, dlschCfg->dlDmrsSymbPos,
pdsch_nb_rb); dlschCfg->number_rbs);
} }
uint16_t first_symbol_with_data = s0; uint16_t first_symbol_with_data = dlschCfg->start_symbol;
uint32_t dmrs_data_re; uint32_t dmrs_data_re;
if (dlsch0->dlsch_config.dmrsConfigType == NFAPI_NR_DMRS_TYPE1) if (dlschCfg->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)
dmrs_data_re = 12 - 6 * dlsch0->dlsch_config.n_dmrs_cdm_groups; dmrs_data_re = 12 - 6 * dlschCfg->n_dmrs_cdm_groups;
else else
dmrs_data_re = 12 - 4 * dlsch0->dlsch_config.n_dmrs_cdm_groups; dmrs_data_re = 12 - 4 * dlschCfg->n_dmrs_cdm_groups;
while ((dmrs_data_re == 0) && (dlsch0->dlsch_config.dlDmrsSymbPos & (1 << first_symbol_with_data))) { while ((dmrs_data_re == 0) && (dlschCfg->dlDmrsSymbPos & (1 << first_symbol_with_data))) {
first_symbol_with_data++; first_symbol_with_data++;
} }
...@@ -582,7 +589,7 @@ static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, ...@@ -582,7 +589,7 @@ static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue,
int32_t log2_maxh = 0; int32_t log2_maxh = 0;
start_meas(&ue->rx_pdsch_stats); start_meas(&ue->rx_pdsch_stats);
for (int m = s0; m < (s1 + s0); m++) { for (int m = dlschCfg->start_symbol; m < (dlschCfg->number_symbols + dlschCfg->start_symbol); m++) {
bool first_symbol_flag = false; bool first_symbol_flag = false;
if (m == first_symbol_with_data) if (m == first_symbol_with_data)
first_symbol_flag = true; first_symbol_flag = true;
......
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
View file @ a0746181
...@@ -1694,7 +1694,7 @@ int get_nr_prach_occasion_info_from_index(uint8_t index, ...@@ -1694,7 +1694,7 @@ int get_nr_prach_occasion_info_from_index(uint8_t index,
if (pointa > 2016666) { //FR2 if (pointa > 2016666) { //FR2
x = table_6_3_3_2_4_prachConfig_Index[index][2]; x = table_6_3_3_2_4_prachConfig_Index[index][2];
s_map = table_6_3_3_2_4_prachConfig_Index[index][5]; s_map = table_6_3_3_2_4_prachConfig_Index[index][5];
*N_RA_sfn += count_bits_set(s_map); *N_RA_sfn += count_bits64(s_map);
*N_RA_slot = table_6_3_3_2_4_prachConfig_Index[index][7]; // Number of RACH slots within a subframe *N_RA_slot = table_6_3_3_2_4_prachConfig_Index[index][7]; // Number of RACH slots within a subframe
*max_association_period = 160/(x * 10); *max_association_period = 160/(x * 10);
if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){
...@@ -1721,7 +1721,7 @@ int get_nr_prach_occasion_info_from_index(uint8_t index, ...@@ -1721,7 +1721,7 @@ int get_nr_prach_occasion_info_from_index(uint8_t index,
if (unpaired) { if (unpaired) {
x = table_6_3_3_2_3_prachConfig_Index[index][2]; x = table_6_3_3_2_3_prachConfig_Index[index][2];
s_map = table_6_3_3_2_3_prachConfig_Index[index][4]; s_map = table_6_3_3_2_3_prachConfig_Index[index][4];
*N_RA_sfn += count_bits_set(s_map); *N_RA_sfn += count_bits64(s_map);
*N_RA_slot = table_6_3_3_2_3_prachConfig_Index[index][6]; // Number of RACH slots within a subframe *N_RA_slot = table_6_3_3_2_3_prachConfig_Index[index][6]; // Number of RACH slots within a subframe
*max_association_period = 160/(x * 10); *max_association_period = 160/(x * 10);
if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){
...@@ -1746,7 +1746,7 @@ int get_nr_prach_occasion_info_from_index(uint8_t index, ...@@ -1746,7 +1746,7 @@ int get_nr_prach_occasion_info_from_index(uint8_t index,
else { // FDD else { // FDD
x = table_6_3_3_2_2_prachConfig_Index[index][2]; x = table_6_3_3_2_2_prachConfig_Index[index][2];
s_map = table_6_3_3_2_2_prachConfig_Index[index][4]; s_map = table_6_3_3_2_2_prachConfig_Index[index][4];
*N_RA_sfn += count_bits_set(s_map); *N_RA_sfn += count_bits64(s_map);
*N_RA_slot = table_6_3_3_2_2_prachConfig_Index[index][6]; *N_RA_slot = table_6_3_3_2_2_prachConfig_Index[index][6];
if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){ if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){
*start_symbol = table_6_3_3_2_2_prachConfig_Index[index][5]; *start_symbol = table_6_3_3_2_2_prachConfig_Index[index][5];
......
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @ a0746181
...@@ -293,6 +293,7 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *p ...@@ -293,6 +293,7 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *p
pdsch_Config->resourceAllocation == NR_PDSCH_Config__resourceAllocation_resourceAllocationType0) { pdsch_Config->resourceAllocation == NR_PDSCH_Config__resourceAllocation_resourceAllocationType0) {
// TS 38.214 subclause 5.1.2.2.1 Downlink resource allocation type 0 // TS 38.214 subclause 5.1.2.2.1 Downlink resource allocation type 0
dlsch_config_pdu->resource_alloc = 0; dlsch_config_pdu->resource_alloc = 0;
memset(dlsch_config_pdu->rb_bitmap, 0, sizeof(dlsch_config_pdu->rb_bitmap));
int P = getRBGSize(n_RB_DLBWP, pdsch_Config->rbg_Size); int P = getRBGSize(n_RB_DLBWP, pdsch_Config->rbg_Size);
int n_RBG = frequency_domain_assignment.nbits; int n_RBG = frequency_domain_assignment.nbits;
int index = 0; int index = 0;
...@@ -312,6 +313,23 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *p ...@@ -312,6 +313,23 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *p
dlsch_config_pdu->rb_bitmap[j / 8] |= bit_rbg << (j % 8); dlsch_config_pdu->rb_bitmap[j / 8] |= bit_rbg << (j % 8);
index += size_RBG; index += size_RBG;
} }
dlsch_config_pdu->number_rbs = count_bits(dlsch_config_pdu->rb_bitmap, sizeofArray(dlsch_config_pdu->rb_bitmap));
// Temporary code to process type0 as type1 when the RB allocation is contiguous
int state = 0;
for (int i = 0; i < sizeof(dlsch_config_pdu->rb_bitmap) * 8; i++) {
int allocated = dlsch_config_pdu->rb_bitmap[i / 8] & (1 << (i % 8));
if (allocated) {
if (state == 0) {
dlsch_config_pdu->start_rb = i;
state = 1;
} else
AssertFatal(state == 1, "hole, not implemented\n");
} else {
if (state == 1) {
state = 2;
}
}
}
} }
else if (pdsch_Config && else if (pdsch_Config &&
pdsch_Config->resourceAllocation == NR_PDSCH_Config__resourceAllocation_dynamicSwitch) pdsch_Config->resourceAllocation == NR_PDSCH_Config__resourceAllocation_dynamicSwitch)
......
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