Merge branch 'NR_RRC_harq_newdcipdu' into NR_RRC_harq

openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c

@@ -517,11 +517,44 @@ int get_num_dmrs(uint16_t dmrs_mask ) {
   return(num_dmrs);
 }
 
-uint16_t nr_dci_size(nr_dci_format_t format,
+// Table 5.1.2.2.1-1 38.214
+uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) {
+  
+  AssertFatal(bwp_size<276,"BWP Size > 275\n");
+  
+  if (bwp_size < 37)  return (rbg_size_config ? 4 : 2);
+  if (bwp_size < 73)  return (rbg_size_config ? 8 : 4);
+  if (bwp_size < 145) return (rbg_size_config ? 16 : 8);
+  if (bwp_size < 276) return 16;
+}
+
+uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) {
+
+  uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config);
+
+  return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size);
+}
+
+uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) {
+
+  uint8_t nbitsA, nbitsB, nbits = 0;
+  if (typeA != NULL) nbitsA = (typeA->choice.setup->maxLength[0]==0) ? 4 : 5;
+  if (typeB != NULL) nbitsB = (typeB->choice.setup->maxLength[0]==0) ? 5 : 6;
+  if ((typeA != NULL) && (typeB != NULL)) nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB;
+
+  return nbits;
+}
+
+uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
+         dci_pdu_rel15_t *dci_pdu,
+         nr_dci_format_t format,
 		     nr_rnti_type_t rnti_type,
 		     uint16_t N_RB) {
 
+  NR_PDSCH_Config_t *pdsch_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup;
   uint16_t size = 0;
+  int bwp_id = 1;
+  NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
 
   switch(format) {
     /*Only sizes for 0_0 and 1_0 are correct at the moment*/
@@ -529,7 +562,7 @@ uint16_t nr_dci_size(nr_dci_format_t format,
       /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20
       size += 20;
       size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated
-      size += nr_dci_size(NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size
+      size += nr_dci_size(secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size
       // UL/SUL indicator assumed to be 0
       break;
 
@@ -562,29 +595,112 @@ uint16_t nr_dci_size(nr_dci_format_t format,
       break;
 
     case NR_DL_DCI_FORMAT_1_1:
+      // Format identifier
+      size = 1;
       // Carrier indicator
-      size += 1; // Format identifier
+      if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) {
+        dci_pdu->carrier_indicator.nbits=3;
+        size += dci_pdu->carrier_indicator.nbits;
+      }
       // BWP Indicator
+      uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count;
+      dci_pdu->bwp_indicator.nbits = (uint8_t)((n_dl_bwp < 4) ? ceil(log2(n_dl_bwp+1)) : ceil(log2(n_dl_bwp))); 
+      size += dci_pdu->bwp_indicator.nbits;
       // Freq domain assignment
+      long rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size;
+      uint16_t numRBG = getNRBG(NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
+                                NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
+                                rbg_size_config);
+      if (pdsch_config->resourceAllocation == 0)
+        dci_pdu->frequency_domain_assignment.nbits = numRBG;
+      else if (pdsch_config->resourceAllocation == 1)
+        dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
+      else
+        dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
+      size += dci_pdu->frequency_domain_assignment.nbits;
       // Time domain assignment
+      NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_timeDomList = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
+      int num_entries;
+      if (pdsch_timeDomList != NULL)
+        num_entries = pdsch_timeDomList->list.count;
+      else
+        num_entries = 16; // num of entries in default table
+      dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries));
+      size += dci_pdu->time_domain_assignment.nbits;
       // VRB to PRB mapping
+      if (pdsch_config->resourceAllocation == 1) {
+        dci_pdu->vrb_to_prb_mapping.nbits = 1;
+        size += dci_pdu->vrb_to_prb_mapping.nbits;
+      }
       // PRB bundling size indicator
+      if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present == 2) {
+        dci_pdu->prb_bundling_size_indicator.nbits = 1;
+        size += dci_pdu->prb_bundling_size_indicator.nbits;
+      }
       // Rate matching indicator
+      NR_RateMatchPatternGroup_t *group1 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1;
+      NR_RateMatchPatternGroup_t *group2 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2; 
+      if ((group1 != NULL) && (group2 != NULL))
+        dci_pdu->rate_matching_indicator.nbits = 2;
+      if ((group1 != NULL) != (group2 != NULL))
+        dci_pdu->rate_matching_indicator.nbits = 1;
+      size += dci_pdu->rate_matching_indicator.nbits;
       // ZP CSI-RS trigger
-      /// TB1- MCS 5, NDI 1, RV 2
+      uint8_t nZP = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count; 
+      dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1));
+      size += dci_pdu->zp_csi_rs_trigger.nbits;
+      // TB1- MCS 5, NDI 1, RV 2
       size += 8;
       // TB2
-      size += 4 ;  // HARQ PID
+      long *maxCWperDCI = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI;
+      if ((maxCWperDCI != NULL) && (*maxCWperDCI == 2)) {
+        size += 8;
+      }
+      // HARQ PID
+      size += 4;
       // DAI
-      size += 2; // TPC PUCCH
-      size += 3; // PUCCH resource indicator
-      size += 3; // PDSCH to HARQ timing indicator
+      if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells
+        dci_pdu->dai[0].nbits = 4;
+        size += dci_pdu->dai[0].nbits;
+      }
+      // TPC PUCCH
+      size += 2;
+      // PUCCH resource indicator
+      size += 3;
+      // PDSCH to HARQ timing indicator
+      uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count;
+      dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I));
+      size += dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits;
       // Antenna ports
+      NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA;
+      NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeB;
+      dci_pdu->antenna_ports.nbits = getAntPortBitWidth(typeA,typeB);
+      size += dci_pdu->antenna_ports.nbits; 
       // Tx Config Indication
-      size += 2; // SRS request
+      long *isTciEnable = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI;
+      if (isTciEnable != NULL) {
+        dci_pdu->transmission_configuration_indication.nbits = 3;
+        size += dci_pdu->transmission_configuration_indication.nbits;
+      }
+      // SRS request
+      if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig==NULL)
+        dci_pdu->srs_request.nbits = 2;
+      else
+        dci_pdu->srs_request.nbits = 3;
+      size += dci_pdu->srs_request.nbits;
       // CBGTI
+      uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2;
+      long *maxCWperDCI_rrc = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI;
+      uint8_t maxCW = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc;
+      dci_pdu->cbgti.nbits = maxCBGperTB * maxCW;
+      size += dci_pdu->cbgti.nbits;
       // CBGFI
-      size += 1; // DMRS sequence init
+      if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->codeBlockGroupFlushIndicator) {
+        dci_pdu->cbgfi.nbits = 1;
+        size += dci_pdu->cbgfi.nbits;
+      }
+      // DMRS sequence init
+      size += 1;
       break;
 
     case NR_DL_DCI_FORMAT_2_0:

openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c

@@ -341,13 +341,13 @@ int configure_fapi_dl_pdu(int Mod_idP,
 						     scc->dmrs_TypeA_Position,
 						     pdsch_pdu_rel15->NrOfSymbols);
 
-  dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
+  dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15));
   
-  dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, 
+  dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, 
 										   pdsch_pdu_rel15->rbStart, 
 										   NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
-  dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV;
-  dci_pdu_rel15[0].vrb_to_prb_mapping = 1;
+  dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV;
+  dci_pdu_rel15[0].vrb_to_prb_mapping.val = 1;
   dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0];
   dci_pdu_rel15[0].tb_scaling = 1;
   
@@ -356,18 +356,19 @@ int configure_fapi_dl_pdu(int Mod_idP,
   dci_pdu_rel15[0].ndi = 1;
   dci_pdu_rel15[0].rv = 0;
   dci_pdu_rel15[0].harq_pid = 0;
-  dci_pdu_rel15[0].dai = (pucch_sched->dai_c-1)&3;
+  dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3;
   dci_pdu_rel15[0].tpc = 2;
   dci_pdu_rel15[0].pucch_resource_indicator = pucch_sched->resource_indicator;
-  dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = pucch_sched->timing_indicator;
+  dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = pucch_sched->timing_indicator;
+
   
   LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
-	dci_pdu_rel15[0].frequency_domain_assignment,
+	dci_pdu_rel15[0].frequency_domain_assignment.val,
 	pdsch_pdu_rel15->rbStart, 
 	pdsch_pdu_rel15->rbSize,	
 	NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
-	dci_pdu_rel15[0].time_domain_assignment,
-	dci_pdu_rel15[0].vrb_to_prb_mapping,
+	dci_pdu_rel15[0].time_domain_assignment.val,
+	dci_pdu_rel15[0].vrb_to_prb_mapping.val,
 	dci_pdu_rel15[0].mcs,
 	dci_pdu_rel15[0].tb_scaling,
 	dci_pdu_rel15[0].ndi, 
@@ -391,8 +392,7 @@ int configure_fapi_dl_pdu(int Mod_idP,
   dci_formats[0]  = NR_DL_DCI_FORMAT_1_0;
   rnti_types[0]   = NR_RNTI_C;
 
-  pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
-  fill_dci_pdu_rel15(secondaryCellGroup,pdsch_pdu_rel15,pdcch_pdu_rel15,NULL,&dci_pdu_rel15[0],dci_formats,rnti_types);
+  fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types);
 
   LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
 	                      coreset params: FreqDomainResource %llx, start_symbol %d  n_symb %d\n",
@@ -424,12 +424,12 @@ int configure_fapi_dl_pdu(int Mod_idP,
 
 void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) {
 
-  dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, 
+  dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, 
 										 pusch_pdu->rb_start, 
 										 NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
 
-  dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV;
-  dci_pdu_rel15->frequency_hopping_flag = 0;
+  dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV;
+  dci_pdu_rel15->frequency_hopping_flag.val = 0;
   dci_pdu_rel15->mcs = 9;
   
   dci_pdu_rel15->format_indicator = 0;
@@ -440,9 +440,9 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr
   
   LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
 	pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci],
-	dci_pdu_rel15->frequency_domain_assignment,
-	dci_pdu_rel15->time_domain_assignment,
-	dci_pdu_rel15->frequency_hopping_flag,
+	dci_pdu_rel15->frequency_domain_assignment.val,
+	dci_pdu_rel15->time_domain_assignment.val,
+	dci_pdu_rel15->frequency_hopping_flag.val,
 	dci_pdu_rel15->mcs,
 	dci_pdu_rel15->tpc,
 	dci_pdu_rel15->ndi, 
@@ -838,8 +838,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
 
   config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
   
-  pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
-  fill_dci_pdu_rel15(secondaryCellGroup,NULL,pdcch_pdu_rel15,pusch_pdu,&dci_pdu_rel15[0],dci_formats,rnti_types);
+  fill_dci_pdu_rel15(secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types);
   
 }
 

openair2/LAYER2/NR_MAC_gNB/mac_proto.h

@@ -148,9 +148,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
                         NR_BWP_Downlink_t *bwp);
 
 void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
-                        nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15,
                         nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
-                        nfapi_nr_pusch_pdu_t  *pusch_pdu,
                         dci_pdu_rel15_t *dci_pdu_rel15,
                         int *dci_formats,
                         int *rnti_types);
@@ -192,9 +190,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP);
 
 int get_num_dmrs(uint16_t dmrs_mask );
 
-uint16_t nr_dci_size(nr_dci_format_t format,
-                         nr_rnti_type_t rnti_type,
-                         uint16_t N_RB);
+uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
+                     dci_pdu_rel15_t *dci_pdu,
+                     nr_dci_format_t format,
+                     nr_rnti_type_t rnti_type,
+                     uint16_t N_RB);
 
 int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
                      int bwp_id,

openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h

@@ -203,7 +203,7 @@ typedef struct gNB_MAC_INST_s {
   int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE];
 } gNB_MAC_INST;
 
-typedef struct {
+/*typedef struct {
 
 
 uint8_t format_indicator; //1 bit
@@ -263,8 +263,71 @@ uint8_t antenna_ports;
 uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
 uint16_t padding;
 
-} dci_pdu_rel15_t;
+} dci_pdu_rel15_t;*/
 
+typedef struct {
+  uint16_t val;
+  uint8_t nbits;
+} dci_field_t;
+
+typedef struct {
+
+
+uint8_t     format_indicator; //1 bit
+uint8_t     ra_preamble_index; //6 bits
+uint8_t     ss_pbch_index; //6 bits
+uint8_t     prach_mask_index; //4 bits
+uint8_t     mcs; //5 bits
+uint8_t     ndi; //1 bit
+uint8_t     rv; //2 bits
+uint8_t     harq_pid; //4 bits
+uint8_t     tpc; //2 bits
+uint8_t     short_messages_indicator; //2 bits
+uint8_t     short_messages; //8 bits
+uint8_t     tb_scaling; //2 bits
+uint8_t     pucch_resource_indicator; //3 bits
+uint8_t     dmrs_sequence_initialization; //1 bit
+uint8_t     system_info_indicator; //1 bit
+
+uint8_t     slot_format_indicator_count;
+uint8_t     *slot_format_indicators;
+ 
+uint8_t     pre_emption_indication_count;
+uint16_t    *pre_emption_indications; //14 bit each
+ 
+uint8_t     block_number_count;
+uint8_t     *block_numbers;
+uint8_t     padding;
+
+dci_field_t mcs2; //variable
+dci_field_t ndi2; //variable
+dci_field_t rv2; //variable
+dci_field_t frequency_domain_assignment; //variable
+dci_field_t time_domain_assignment; //variable
+dci_field_t frequency_hopping_flag; //variable
+dci_field_t vrb_to_prb_mapping; //variable
+dci_field_t dai[2]; //variable
+dci_field_t pdsch_to_harq_feedback_timing_indicator; //variable
+dci_field_t carrier_indicator; //variable
+dci_field_t bwp_indicator; //variable
+dci_field_t prb_bundling_size_indicator; //variable
+dci_field_t rate_matching_indicator; //variable
+dci_field_t zp_csi_rs_trigger; //variable
+dci_field_t transmission_configuration_indication; //variable
+dci_field_t srs_request; //variable
+dci_field_t cbgti; //variable
+dci_field_t cbgfi; //variable
+dci_field_t srs_resource_indicator; //variable
+dci_field_t precoding_information; //variable
+dci_field_t csi_request; //variable
+dci_field_t ptrs_dmrs_association; //variable
+dci_field_t beta_offset_indicator; //variable
+dci_field_t cloded_loop_indicator; //variable
+dci_field_t ul_sul_indicator; //variable
+dci_field_t antenna_ports; //variable
+dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
+
+} dci_pdu_rel15_t;
 
 
 #endif /*__LAYER2_NR_MAC_GNB_H__ */