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OpenXG-RAN
Commits
e5226adc
Commit
e5226adc
authored
Mar 13, 2021
by
Raymond Knopp
Browse files
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Plain Diff
Merge branch 'oairu' of
https://gitlab.eurecom.fr/oai/openairinterface5g
into oairu
parents
d72b9c4e
28f65fb2
Changes
3
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3 changed files
with
36 additions
and
30 deletions
+36
-30
openair1/PHY/INIT/lte_init_ru.c
openair1/PHY/INIT/lte_init_ru.c
+1
-0
openair1/SCHED/ru_procedures.c
openair1/SCHED/ru_procedures.c
+23
-22
targets/RT/USER/lte-ru.c
targets/RT/USER/lte-ru.c
+12
-8
No files found.
openair1/PHY/INIT/lte_init_ru.c
View file @
e5226adc
...
...
@@ -45,6 +45,7 @@ int phy_init_RU(RU_t *ru) {
if
(
ru
->
is_slave
==
1
)
{
generate_ul_ref_sigs_rx
();
}
else
generate_ul_ref_sigs
();
if
(
ru
->
if_south
<=
REMOTE_IF5
)
{
// this means REMOTE_IF5 or LOCAL_RF, so allocate memory for time-domain signals
// Time-domain signals
...
...
openair1/SCHED/ru_procedures.c
View file @
e5226adc
...
...
@@ -139,27 +139,26 @@ void feptx0(RU_t *ru,
int
num_symb
=
7
;
if
(
subframe_select
(
fp
,
subframe
)
==
SF_S
)
num_symb
=
fp
->
dl_symbols_in_S_subframe
+
1
;
num_symb
=
fp
->
dl_symbols_in_S_subframe
+
1
;
if
(
ru
->
generate_dmrs_sync
==
1
&&
slot
==
0
&&
subframe
==
1
&&
aa
==
0
)
{
if
(
ru
->
generate_dmrs_sync
==
1
&&
slot
==
2
&&
aa
==
0
)
{
//int32_t dmrs[ru->frame_parms.ofdm_symbol_size*14] __attribute__((aligned(32)));
//int32_t *dmrsp[2] ={dmrs,NULL}; //{&dmrs[(3-ru->frame_parms.Ncp)*ru->frame_parms.ofdm_symbol_size],NULL};
generate_drs_pusch
((
PHY_VARS_UE
*
)
NULL
,
(
UE_rxtx_proc_t
*
)
NULL
,
fp
,
ru
->
common
.
txdataF_BF
,
0
,
AMP
,
0
,
0
,
fp
->
N_RB_DL
,
aa
);
generate_drs_pusch
((
PHY_VARS_UE
*
)
NULL
,
(
UE_rxtx_proc_t
*
)
NULL
,
fp
,
ru
->
common
.
txdataF_BF
,
0
,
AMP
,
0
,
0
,
fp
->
N_RB_DL
,
aa
);
}
normal_prefix_mod
(
&
ru
->
common
.
txdataF_BF
[
aa
][(
slot
&
1
)
*
slot_sizeF
],
(
int
*
)
&
ru
->
common
.
txdata
[
aa
][
slot_offset
],
num_symb
,
fp
);
normal_prefix_mod
(
&
ru
->
common
.
txdataF_BF
[
aa
][(
slot
&
1
)
*
slot_sizeF
],
(
int
*
)
&
ru
->
common
.
txdata
[
aa
][
slot_offset
],
num_symb
,
fp
);
}
}
...
...
@@ -658,7 +657,7 @@ void ru_fep_full_2thread(RU_t *ru,
struct
timespec
wait
;
if
((
fp
->
frame_type
==
TDD
)
&&
(
subframe_select
(
fp
,
subframe
)
!=
SF_U
L
))
return
;
if
((
fp
->
frame_type
==
TDD
)
&&
(
subframe_select
(
fp
,
subframe
)
==
SF_D
L
))
return
;
if
(
ru
->
idx
==
0
)
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME
(
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPRX
,
1
);
...
...
@@ -705,7 +704,7 @@ void ru_fep_full_2thread(RU_t *ru,
if
(
proc
->
tti_rx
/*proc->subframe_rx*/
==
1
&&
ru
->
is_slave
==
1
/* && ru->state == RU_CHECK_SYNC*/
)
{
//
LOG_I(PHY,"Running check synchronization procedure for frame %d\n", proc->frame_rx);
LOG_I
(
PHY
,
"Running check synchronization procedure for frame %d
\n
"
,
proc
->
frame_rx
);
ulsch_extract_rbs_single
(
ru
->
common
.
rxdataF
,
calibration
->
rxdataF_ext
,
0
,
...
...
@@ -731,9 +730,10 @@ void ru_fep_full_2thread(RU_t *ru,
check_sync_pos
=
lte_est_timing_advance_pusch
(
ru
->
frame_parms
,
ru
->
calibration
.
drs_ch_estimates_time
);
if
(
ru
->
state
==
RU_CHECK_SYNC
)
{
if
((
check_sync_pos
>=
0
&&
check_sync_pos
<
8
)
||
(
check_sync_pos
<
0
&&
check_sync_pos
>-
8
))
{
LOG_I
(
PHY
,
"~~~~~~~~~~~ check_sync_pos %d, frame %d, cnt %d
\n
"
,
check_sync_pos
,
proc
->
frame_rx
,
ru
->
wait_check
);
//
LOG_I(PHY,"~~~~~~~~~~~ check_sync_pos %d, frame %d, cnt %d\n",check_sync_pos,proc->frame_rx,ru->wait_check);
ru
->
wait_check
++
;
}
LOG_I
(
PHY
,
"~~~~~~~~~~~ check_sync_pos %d, frame %d, cnt %d
\n
"
,
check_sync_pos
,
proc
->
frame_rx
,
ru
->
wait_check
);
if
(
ru
->
wait_check
==
20
)
{
ru
->
state
=
RU_RUN
;
...
...
@@ -743,10 +743,11 @@ void ru_fep_full_2thread(RU_t *ru,
rru_config_msg
.
len
=
sizeof
(
RRU_CONFIG_msg_t
);
// TODO: set to correct msg len
LOG_I
(
PHY
,
"Sending RRU_sync_ok to RAU
\n
"
);
AssertFatal
((
ru
->
ifdevice
.
trx_ctlsend_func
(
&
ru
->
ifdevice
,
&
rru_config_msg
,
rru_config_msg
.
len
)
!=-
1
),
"Failed to send msg to RAU %d
\n
"
,
ru
->
idx
);
/*
//LOG_I(PHY,"~~~~~~~~~ RU_RUN\n");
/*
LOG_M("dmrs_time.m","dmrstime",calibration->drs_ch_estimates_time[0], (fp->ofdm_symbol_size),1,1);
LOG_M("dmrs_time.m","dmrstime",calibration->drs_ch_estimates_time[0], (fp->ofdm_symbol_size),1,1);
LOG_M("rxdataF_ext.m","rxdataFext",&calibration->rxdataF_ext[0][36*fp->N_RB_DL], 12*(fp->N_RB_DL),1,1);
LOG_M("drs_seq0.m","drsseq0",ul_ref_sigs_rx[0][0][23],600,1,1);
//
LOG_M("drs_seq0.m","drsseq0",ul_ref_sigs_rx[0][0][23],600,1,1);
LOG_M("rxdata.m","rxdata",&ru->common.rxdata[0][0], fp->samples_per_tti*2,1,1);
exit(-1);*/
}
...
...
targets/RT/USER/lte-ru.c
View file @
e5226adc
...
...
@@ -1721,7 +1721,7 @@ static void *ru_thread( void *param ) {
// if this is a slave RRU, try to synchronize on the DL frequency
if
((
ru
->
is_slave
==
1
)
&&
(
ru
->
if_south
==
LOCAL_RF
))
do_ru_synch
(
ru
);
LOG_D
(
PHY
,
"RU %d Starting steady-state operation
\n
"
,
ru
->
idx
);
if
(
ru
->
state
==
RU_RUN
||
ru
->
state
==
RU_CHECK_SYNC
)
LOG_I
(
PHY
,
"RU %d Starting steady-state operation
\n
"
,
ru
->
idx
);
// This is a forever while loop, it loops over subframes which are scheduled by incoming samples from HW devices
while
(
ru
->
state
==
RU_RUN
||
ru
->
state
==
RU_CHECK_SYNC
)
{
...
...
@@ -1918,7 +1918,7 @@ static void *ru_thread( void *param ) {
// This thread run the initial synchronization like a UE
void
*
ru_thread_synch
(
void
*
arg
)
{
RU_t
*
ru
=
(
RU_t
*
)
arg
;
LTE_DL_FRAME_PARMS
*
fp
=
ru
->
frame_parms
;
LTE_DL_FRAME_PARMS
*
fp
;
int64_t
peak_val
,
avg
;
static
int
ru_thread_synch_status
=
0
;
int
cnt
=
0
;
...
...
@@ -1927,6 +1927,8 @@ void *ru_thread_synch(void *arg) {
// initialize variables for PSS detection
ru_sync_time_init
(
ru
);
//lte_sync_time_init(ru->frame_parms);
fp
=
ru
->
frame_parms
;
int
last_rxoff
=
0
;
while
(
!
oai_exit
)
{
// wait to be woken up
if
(
wait_on_condition
(
&
ru
->
proc
.
mutex_synch
,
&
ru
->
proc
.
cond_synch
,
&
ru
->
proc
.
instance_cnt_synch
,
"ru_thread_synch"
)
<
0
)
break
;
...
...
@@ -1940,17 +1942,18 @@ void *ru_thread_synch(void *arg) {
&
avg
);
LOG_I
(
PHY
,
"RU synch cnt %d: %d, val %llu (%d dB,%d dB)
\n
"
,
cnt
,
ru
->
rx_offset
,(
unsigned
long
long
)
peak_val
,
dB_fixed64
(
peak_val
),
dB_fixed64
(
avg
));
cnt
++
;
//if (/*ru->rx_offset >= 0*/dB_fixed(peak_val)>=85 && cnt>10) {
if
(
ru
->
rx_offset
>=
0
&&
avg
>
0
&&
dB_fixed
(
peak_val
/
avg
)
>=
15
&&
cnt
>
10
)
{
int
abs_diff
=
ru
->
rx_offset
-
last_rxoff
;
if
(
abs_diff
<
0
)
abs_diff
=-
abs_diff
;
if
(
ru
->
rx_offset
>=
0
&&
a
bs_diff
<
6
&&
a
vg
>
0
&&
dB_fixed
(
peak_val
/
avg
)
>=
15
&&
cnt
>
10
)
{
LOG_I
(
PHY
,
"Estimated peak_val %d dB, avg %d => timing offset %llu
\n
"
,
dB_fixed
(
peak_val
),
dB_fixed
(
avg
),(
unsigned
long
long
int
)
ru
->
rx_offset
);
ru
->
in_synch
=
1
;
/*
/*
LOG_M("ru_sync_rx.m","rurx",&ru->common.rxdata[0][0],LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*fp->samples_per_tti,1,1);
LOG_M("ru_sync_corr.m","sync_corr",ru->dmrs_corr,LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*fp->samples_per_tti,1,6);
LOG_M("ru_dmrs.m","rudmrs",&ru->dmrssync[0],fp->ofdm_symbol_size,1,1);
*/
//exit(-1);
exit(-1);
*/
}
// sync_pos > 0
else
{
//AssertFatal(cnt<1000,"Cannot find synch reference\n");
if
(
cnt
>
200
)
{
...
...
@@ -1960,6 +1963,7 @@ void *ru_thread_synch(void *arg) {
exit
(
-
1
);
}
}
last_rxoff
=
ru
->
rx_offset
;
}
// ru->in_synch==0
if
(
release_thread
(
&
ru
->
proc
.
mutex_synch
,
&
ru
->
proc
.
instance_cnt_synch
,
"ru_synch_thread"
)
<
0
)
break
;
...
...
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