- 24 Oct, 2018 4 commits
- 23 Oct, 2018 7 commits
- 22 Oct, 2018 19 commits
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
Modify not to assert a part in L2 FAPI simulator because it's possible to differ timing(frame, subframe) between eNB and UE.
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Y_Tomita authored
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Y_Tomita authored
Change not to watch timing in MSG2 and MSG4 procedure in L2 FAPI simulator because it's possible to differ timing(frame, subframe) between eNB and UE.
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
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- 17 Oct, 2018 6 commits
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Y_Tomita authored
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Y_Tomita authored
Fix for problems that L2sim finishes in case of multiple UEs and UE L2sim keeps wating for a signal.
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Y_Tomita authored
Fix for problems that eNB keeps waiting for signal of unused thread and eNB_thread_rxtx isn't created.
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Y_Tomita authored
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Y_Tomita authored
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Y_Tomita authored
Change type for 256UEs test , abnormal exit and add definition of UE's thread ID for multiple UEs simulation.
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- 16 Oct, 2018 4 commits
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Raphael Defosseux authored
also adding TDD IF4p5 testing removing basic-sim TDD 5MHz DL iperf test Signed-off-by: Raphael Defosseux <raphael.defosseux@eurecom.fr>
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Raphael Defosseux authored
--> currently only FDD 5MHz Signed-off-by: Raphael Defosseux <raphael.defosseux@eurecom.fr>
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Raphael Defosseux authored
Signed-off-by: Raphael Defosseux <raphael.defosseux@eurecom.fr>
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Raphael Defosseux authored
Signed-off-by: Raphael Defosseux <raphael.defosseux@eurecom.fr>
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