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  1. 10 Jun, 2024 2 commits
  2. 07 Jun, 2024 2 commits
  3. 22 May, 2024 1 commit
  4. 26 Mar, 2024 1 commit
  5. 07 Mar, 2024 1 commit
  6. 12 Feb, 2024 1 commit
    • Raymond Knopp's avatar
      Introduce separate thread to handle gNB TX processing · d52b8179
      Raymond Knopp authored
      This commit introduces a separate thread (l1_tx_thread) that processes
      gNB DL/TX slots. It receives a message from the ru_thread when a new
      slot started, and starts processing.
      
      The DL part of the scheduler is run in the l1_tx_thread.  Therefore,
      only call UL indication (for scheduler) in UL slots.  The UL indication
      previously triggered the DL scheduler -- hence, it had to be called in
      every slot. Now, since the DL scheduler is moved into the DL thread, we
      don't have to call the scheduler in every slot anymore.
      
      The reorder thread is removed, as reordering with this scheme is not
      necessary anymore.
      
      The main advantage of this version is that the TX can be scheduled
      earlier (sl_ahead). Further, there can no longer be race conditions in
      the TX path, since the scheduler/L2, TX L1 processing and the RU tx
      function are all execute in the same thread (L1_tX_thread).
      
      Also, the scheduler prepares PRACH/PUSCH/PUCCH FAPI PDUs. As of this
      commit, the scheduler runs in the TX processing chain, whereas these
      PDUs are destined for RX processing.  Thus, too avoid data races,
      instead of triggering the RX processing at the same time as TX
      processing in the RU thread, this commit changes the code to trigger RX
      processing after the scheduler has been run in TX processing to avoid
      data races.
      
      Finally, we synchronize RU and L1 threads. This is important for
      rfsimulator, since unlike most radios, rfsimulator can run slower or
      faster, depending on I/O and CPU (it does not have a stable "tick").
      Co-authored-by: default avatarkiran <saikiran@iitj.ac.in>
      d52b8179
  7. 03 Nov, 2023 1 commit
  8. 06 Oct, 2023 1 commit
  9. 25 Sep, 2023 13 commits
  10. 13 Sep, 2023 1 commit
    • Raymond Knopp's avatar
      First-level of support for new aarch64 machines · a7bc2823
      Raymond Knopp authored
      Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.
      
      - Changes:
      - use SIMDE consistently
      - adaptations of LDPC decoder generator for ARMv8 performance
      - SIMDe modifications of Intel CRC to allow for aarch64 build.
        optimizations for 128-bit to improve performance of LDPC encode/decode
        on aarch64 (Neoverse 1)
      - added BG2 files for 128-bit ldpc encoder (aarch64)
      - testing on Xeon
      - testing on x86
      - minor changes to build/run on x86
      - change in crc.h after returning to aarch64
      - removed some warning in ldpc decoder generator for x86_64
      - char
      - Delete irrelevant constants
      - Correctly declare variables
      - Define stdbool for all architectures
      - Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
      - Remove commented code
      - Fix CMakeLists.txt
      - Include SIMDE avx2 functions in tools_defs.h
      a7bc2823
  11. 25 Jul, 2023 2 commits
  12. 26 Jun, 2023 4 commits
  13. 01 Jun, 2023 1 commit
    • Vijay Chadachan's avatar
      CPPCHECK fixes for printf issues · 836469e8
      Vijay Chadachan authored
      Fix for following CPPCheck warnings
      - invalidPrintfArgType
      Rebased with latest develop branch w21.
      Reverted modifications unrelated to printf issues.
      836469e8
  14. 19 Apr, 2023 2 commits
  15. 17 Apr, 2023 2 commits
  16. 10 Apr, 2023 2 commits
  17. 27 Mar, 2023 3 commits