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wangwenhui
OpenXG-RAN
Commits
98efcd52
Commit
98efcd52
authored
Mar 21, 2017
by
Calisson
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Plain Diff
fixing a bug related to SRS procedures
parent
1677e8f8
Changes
2
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2 changed files
with
8 additions
and
7 deletions
+8
-7
openair1/SCHED/phy_procedures_lte_eNb.c
openair1/SCHED/phy_procedures_lte_eNb.c
+3
-2
targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band38.tm1.usrpb210.conf
...ROJECTS/GENERIC-LTE-EPC/CONF/enb.band38.tm1.usrpb210.conf
+5
-5
No files found.
openair1/SCHED/phy_procedures_lte_eNb.c
View file @
98efcd52
...
...
@@ -843,6 +843,7 @@ void generate_eNB_ulsch_params(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC
1
<<
dci_alloc
->
L
);
is_srs_pos
=
is_srs_occasion_common
(
fp
,
pdcch_alloc2ul_frame
(
fp
,
frame
,
subframe
),
pdcch_alloc2ul_subframe
(
fp
,
subframe
));
/*
if (is_srs_pos && eNB->soundingrs_ul_config_dedicated[UE_id].srsConfigDedicatedSetup) {
srsConfigIndex = eNB->soundingrs_ul_config_dedicated[UE_id].srs_ConfigIndex;
compute_srs_pos(fp->frame_type, srsConfigIndex, &srsPeriodicity, &srsOffset);
...
...
@@ -850,10 +851,10 @@ void generate_eNB_ulsch_params(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC
do_srs = 1;
}
}
LOG_D(PHY,"frame %d (%d), subframe %d (%d), UE_id %d: is_srs_pos %d, do_SRS %d, index %d, period %d, offset %d \n",
frame,pdcch_alloc2ul_frame(fp,frame,subframe),subframe,pdcch_alloc2ul_subframe(fp,subframe),
UE_id,is_srs_pos,do_srs,srsConfigIndex,srsPeriodicity,srsOffset);
*/
generate_eNB_ulsch_params_from_dci
(
eNB
,
proc
,
...
...
@@ -865,7 +866,7 @@ void generate_eNB_ulsch_params(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC
0
,
P_RNTI
,
CBA_RNTI
,
do_srs
);
// do_srs
is_srs_pos
);
LOG_T
(
PHY
,
"[eNB %"
PRIu8
"] Frame %d subframe %d : CCE resources for UE spec DCI (PUSCH %"
PRIx16
") => %d
\n
"
,
eNB
->
Mod_id
,
frame
,
subframe
,
dci_alloc
->
rnti
,
...
...
targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band38.tm1.usrpb210.conf
View file @
98efcd52
...
...
@@ -62,11 +62,11 @@ eNBs =
pusch_nDMRS1
=
1
;
phich_duration
=
"NORMAL"
;
phich_resource
=
"ONESIXTH"
;
srs_enable
=
"
DIS
ABLE"
;
/*
srs_BandwidthConfig
=
;
srs_SubframeConfig
=;
srs_ackNackST
=;
srs_MaxUpPts
=
;*/
srs_enable
=
"
EN
ABLE"
;
srs_BandwidthConfig
=
2
;
srs_SubframeConfig
=
7
;
srs_ackNackST
=
"DISABLE"
;
srs_MaxUpPts
=
"DISABLE"
;
pusch_p0_Nominal
= -
90
;
pusch_alpha
=
"AL1"
;
...
...
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