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zzha zzha
OpenXG-RAN
Commits
3387a94a
Commit
3387a94a
authored
Mar 23, 2022
by
francescomani
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fix for fr2 sl_ahead
parent
d840ca0d
Changes
5
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5 changed files
with
11 additions
and
7 deletions
+11
-7
ci-scripts/conf_files/gnb.band261.tm1.32PRB.usrpn300.conf
ci-scripts/conf_files/gnb.band261.tm1.32PRB.usrpn300.conf
+1
-0
openair1/PHY/NR_UE_TRANSPORT/nr_prach.c
openair1/PHY/NR_UE_TRANSPORT/nr_prach.c
+6
-3
openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
+1
-1
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
+1
-1
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+2
-2
No files found.
ci-scripts/conf_files/gnb.band261.tm1.32PRB.usrpn300.conf
View file @
3387a94a
...
...
@@ -227,6 +227,7 @@ RUs = (
att_tx
=
0
;
att_rx
=
0
;
bands
= [
7
];
sl_ahead
=
12
;
max_pdschReferenceSignalPower
= -
27
;
max_rxgain
=
75
;
eNB_instances
= [
0
];
...
...
openair1/PHY/NR_UE_TRANSPORT/nr_prach.c
View file @
3387a94a
...
...
@@ -57,7 +57,7 @@ extern const char *prachfmt[];
// - idft for short sequence assumes we are transmitting starting in symbol 0 of a PRACH slot
// - Assumes that PRACH SCS is same as PUSCH SCS @ 30 kHz, take values for formats 0-2 and adjust for others below
// - Preamble index different from 0 is not detected by gNB
int32_t
generate_nr_prach
(
PHY_VARS_NR_UE
*
ue
,
uint8_t
gNB_id
,
uint8_t
slot
){
int32_t
generate_nr_prach
(
PHY_VARS_NR_UE
*
ue
,
uint8_t
gNB_id
,
int
frame
,
uint8_t
slot
){
NR_DL_FRAME_PARMS
*
fp
=&
ue
->
frame_parms
;
fapi_nr_config_request_t
*
nrUE_config
=
&
ue
->
nrUE_config
;
...
...
@@ -190,8 +190,9 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){
// now generate PRACH signal
#ifdef NR_PRACH_DEBUG
if
(
NCS
>
0
)
LOG_I
(
PHY
,
"PRACH [UE %d] generate PRACH in
slot
%d for RootSeqIndex %d, Preamble Index %d, PRACH Format %s, NCS %d (N_ZC %d): Preamble_offset %d, Preamble_shift %d msg1 frequency start %d
\n
"
,
LOG_I
(
PHY
,
"PRACH [UE %d] generate PRACH in
frame.slot %d.
%d for RootSeqIndex %d, Preamble Index %d, PRACH Format %s, NCS %d (N_ZC %d): Preamble_offset %d, Preamble_shift %d msg1 frequency start %d
\n
"
,
Mod_id
,
frame
,
slot
,
rootSequenceIndex
,
preamble_index
,
...
...
@@ -221,7 +222,9 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){
k
+=
kbar
;
k
*=
2
;
LOG_I
(
PHY
,
"PRACH [UE %d] in slot %d, placing PRACH in position %d, msg1 frequency start %d (k1 %d), preamble_offset %d, first_nonzero_root_idx %d
\n
"
,
Mod_id
,
LOG_I
(
PHY
,
"PRACH [UE %d] in frame.slot %d.%d, placing PRACH in position %d, msg1 frequency start %d (k1 %d), preamble_offset %d, first_nonzero_root_idx %d
\n
"
,
Mod_id
,
frame
,
slot
,
k
,
n_ra_prb
,
...
...
openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
View file @
3387a94a
...
...
@@ -1704,7 +1704,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
unsigned
char
i_mod
,
unsigned
char
harq_pid
);
int32_t
generate_nr_prach
(
PHY_VARS_NR_UE
*
ue
,
uint8_t
gNB_id
,
uint8_t
subframe
);
int32_t
generate_nr_prach
(
PHY_VARS_NR_UE
*
ue
,
uint8_t
gNB_id
,
int
frame
,
uint8_t
slot
);
void
dump_nrdlsch
(
PHY_VARS_NR_UE
*
ue
,
uint8_t
gNB_id
,
uint8_t
nr_slot_rx
,
unsigned
int
*
coded_bits_per_codeword
,
int
round
,
unsigned
char
harq_pid
);
/**@}*/
...
...
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
View file @
3387a94a
...
...
@@ -1801,7 +1801,7 @@ void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME
(
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH
,
VCD_FUNCTION_IN
);
prach_power
=
generate_nr_prach
(
ue
,
gNB_id
,
nr_slot_tx
);
prach_power
=
generate_nr_prach
(
ue
,
gNB_id
,
frame_tx
,
nr_slot_tx
);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME
(
VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH
,
VCD_FUNCTION_OUT
);
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @
3387a94a
...
...
@@ -466,12 +466,12 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
uint8_t
start_next_period
=
(
rach_slot
-
(
rach_slot
%
tdd_period_slot
)
+
tdd_period_slot
)
%
nr_slots_per_frame
[
mu
];
*
msg2_slot
=
start_next_period
+
last_dl_slot_period
;
// initializing scheduling of slot to next mixed (or last dl) slot
*
msg2_frame
=
((
*
msg2_slot
>
(
rach_slot
))
?
rach_frame
:
(
rach_frame
+
1
))
%
1024
;
// we can't schedule msg2 before sl_ahead since prach
int
eff_slot
=
*
msg2_slot
+
(
*
msg2_frame
-
rach_frame
)
*
nr_slots_per_frame
[
mu
];
if
((
eff_slot
-
rach_slot
)
<=
sl_ahead
)
{
while
((
eff_slot
-
rach_slot
)
<=
sl_ahead
)
{
*
msg2_slot
=
(
*
msg2_slot
+
tdd_period_slot
)
%
nr_slots_per_frame
[
mu
];
*
msg2_frame
=
((
*
msg2_slot
>
(
rach_slot
))
?
rach_frame
:
(
rach_frame
+
1
))
%
1024
;
eff_slot
=
*
msg2_slot
+
(
*
msg2_frame
-
rach_frame
)
*
nr_slots_per_frame
[
mu
];
}
if
(
FR
==
nr_FR2
)
{
int
num_tdd_period
=
*
msg2_slot
/
tdd_period_slot
;
...
...
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