Skip to content

O
OpenXG-RAN
Commit 3a434370 authored by Raymond Knopp's avatar Raymond Knopp
Browse files
Options

modifications for MPDCCH

parent c8070607
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 8184 additions and 9010 deletions
openair1/PHY/INIT/lte_init.c
View file @ 3a434370
This source diff could not be displayed because it is too large. You can view the blob instead.
openair1/PHY/LTE_TRANSPORT/dci_tools.c
View file @ 3a434370
This diff is collapsed.
openair1/PHY/LTE_TRANSPORT/edci.c
View file @ 3a434370
......@@ -37,10 +37,10 @@
#include "PHY/defs.h"
#include "PHY/extern.h"
#include "SCHED/defs.h"
#include "SIMULATION/TOOLS/defs.h" // for taus
#include "SIMULATION/TOOLS/defs.h" // for taus
#include "PHY/sse_intrin.h"
#include "assertions.h"
#include "assertions.h"
#include "T.h"
#include "UTIL/LOG/log.h"
......@@ -49,50 +49,51 @@
//#define DEBUG_PHY
#ifdef Rel14
void generate_edci_top(PHY_VARS_eNB *eNB, int frame, int subframe) {
void
generate_edci_top (PHY_VARS_eNB * eNB, int frame, int subframe)
{
}
void mpdcch_scrambling(LTE_DL_FRAME_PARMS *frame_parms,
mDCI_ALLOC_t *mdci,
uint16_t i,
uint8_t *e,
uint32_t length)
void
mpdcch_scrambling (LTE_DL_FRAME_PARMS * frame_parms, mDCI_ALLOC_t * mdci, uint16_t i, uint8_t * e, uint32_t length)
{
int n;
uint8_t reset;
uint32_t x1, x2, s=0;
uint8_t Nacc=4;
uint16_t j0,j,idelta;
uint16_t i0 = mdci->i0;
int n;
uint8_t reset;
uint32_t x1, x2, s = 0;
uint8_t Nacc = 4;
uint16_t j0, j, idelta;
uint16_t i0 = mdci->i0;
// Note: we could actually not do anything if i-i0 < Nacc, save it for later
reset = 1;
// x1 is set in lte_gold_generic
if ((mdci->rnti == 0xFFFE) ||
(mdci->ce_mode == 2)) // CEModeB Note: also for mdci->rnti==SC_RNTI
Nacc=frame_parms->frame_type == FDD ? 4 : 10;
else Nacc=1;
if (frame_parms->frame_type == FDD || Nacc == 1) idelta = 0;
else idelta = Nacc-2;
j0 = (i0+idelta)/Nacc;
j = (i - i0)/Nacc;
if ((mdci->rnti == 0xFFFE) || (mdci->ce_mode == 2)) // CEModeB Note: also for mdci->rnti==SC_RNTI
Nacc = frame_parms->frame_type == FDD ? 4 : 10;
else
Nacc = 1;
if (frame_parms->frame_type == FDD || Nacc == 1)
idelta = 0;
else
idelta = Nacc - 2;
j0 = (i0 + idelta) / Nacc;
j = (i - i0) / Nacc;
// rule for BL/CE UEs from Section 6.8.B2 in 36.211
x2= ((((j0+j)*Nacc)%10)<<9) + mdci->dmrs_scrambling_init;
for (n=0; n<length; n++) {
if ((i&0x1f)==0) {
s = lte_gold_generic(&x1, &x2, reset);
x2 = ((((j0 + j) * Nacc) % 10) << 9) + mdci->dmrs_scrambling_init;
for (n = 0; n < length; n++) {
if ((i & 0x1f) == 0) {
s = lte_gold_generic (&x1, &x2, reset);
//printf("lte_gold[%d]=%x\n",i,s);
reset = 0;
}
e[i] = (e[i]&1) ^ ((s>>(i&0x1f))&1);
e[i] = (e[i] & 1) ^ ((s >> (i & 0x1f)) & 1);
}
}
......@@ -101,81 +102,70 @@ void mpdcch_scrambling(LTE_DL_FRAME_PARMS *frame_parms,
// For format 5 there are 6 PRB pairs => 864 REs for 24 total ECCE
static uint16_t mpdcch5tab[864];
void init_mpdcch5tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB) {
int l,k,kmod,re;
LOG_I(PHY,"Inititalizing mpdcch5tab for normal prefix, normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
for (l=0,re=0;l<14;l++) {
for (k=0;k<72;k++){
kmod = k % 12;
if (((l!=5) && (l!=6) && (l!=12) && (l!=13)) ||
(((l==5)||(l==6)||(l==12)||(l==13))&&(kmod!=0)&&(kmod!=5)&&(kmod!=10)))
mpdcch5tab[re++]=(l*eNB->frame_parms.ofdm_symbol_size)+k;
void
init_mpdcch5tab_normal_regular_subframe_evenNRBDL (PHY_VARS_eNB * eNB,int l_MPDCCH_start)
{
int l, k, kmod, re;
LOG_I (PHY, "Inititalizing mpdcch5tab for normal prefix, no PSS/SSS/PBCH, even N_RB_DL\n");
for (l = l_MPDCCH_start, re = 0; l < 14; l++) {
for (k = 0; k < 72; k++) {
kmod = k % 12;
if (((l != 5) && (l != 6) && (l != 12) && (l != 13)) || (((l == 5) || (l == 6) || (l == 12) || (l == 13)) && (kmod != 0) && (kmod != 5) && (kmod != 10)))
mpdcch5tab[re++] = (l * eNB->frame_parms.ofdm_symbol_size) + k;
}
}
AssertFatal(re==864,"RE count not equal to 864\n");
AssertFatal (re == 720, "RE count %d not equal to 864, l_MPDCCH_start %d\n",re,l_MPDCCH_start);
}
extern uint8_t *generate_dci0(uint8_t *dci,
uint8_t *e,
uint8_t DCI_LENGTH,
uint8_t aggregation_level,
uint16_t rnti);
extern uint8_t *generate_dci0 (uint8_t * dci, uint8_t * e, uint8_t DCI_LENGTH, uint8_t aggregation_level, uint16_t rnti);
void generate_mdci_top(PHY_VARS_eNB *eNB, int frame, int subframe,int16_t amp,int32_t **txdataF) {
void
generate_mdci_top (PHY_VARS_eNB * eNB, int frame, int subframe, int16_t amp, int32_t ** txdataF)
{
LTE_eNB_MPDCCH *mpdcch= &eNB->mpdcch_vars[subframe&2];
mDCI_ALLOC_t *mdci;
int coded_bits;
LTE_DL_FRAME_PARMS *fp=&eNB->frame_parms;
int i;
int gain_lin_QPSK;
LTE_eNB_MPDCCH *mpdcch = &eNB->mpdcch_vars[subframe & 2];
mDCI_ALLOC_t *mdci;
int coded_bits;
LTE_DL_FRAME_PARMS *fp = &eNB->frame_parms;
int i;
int gain_lin_QPSK;
for (i=0;i<mpdcch->num_dci;i++) {
for (i = 0; i < mpdcch->num_dci; i++) {
mdci = &mpdcch->mdci_alloc[i];
AssertFatal(fp->frame_type==FDD,"TDD is not yet supported for MPDCCH\n");
AssertFatal(fp->Ncp == NORMAL,"Extended Prefix not yet supported for MPDCCH\n");
AssertFatal(mdci->L<=24,"L is %d\n",mdci->L);
AssertFatal(fp->N_RB_DL==50 || fp->N_RB_DL==100,"Only N_RB_DL=50,100 for MPDCCH\n");
AssertFatal (fp->frame_type == FDD, "TDD is not yet supported for MPDCCH\n");
AssertFatal (fp->Ncp == NORMAL, "Extended Prefix not yet supported for MPDCCH\n");
AssertFatal (mdci->L <= 24, "L is %d\n", mdci->L);
AssertFatal (fp->N_RB_DL == 50 || fp->N_RB_DL == 100, "Only N_RB_DL=50,100 for MPDCCH\n");
// Force MPDDCH format 5
AssertFatal(mdci->number_of_prb_pairs==6,"2 or 4 PRB pairs not support yet for MPDCCH\n");
AssertFatal(mdci->reps>0,"mdci->reps==0\n");
AssertFatal (mdci->number_of_prb_pairs == 6, "2 or 4 PRB pairs not support yet for MPDCCH\n");
AssertFatal (mdci->reps > 0, "mdci->reps==0\n");
// 9 REs/EREG * 4 EREG/ECCE => 36 REs/ECCE => 72 bits/ECCE, so same as regular PDCCH channel encoding
// Note: We only have to run this every Nacc subframes during repetitions, data and scrambling are constant, but we do it for now to simplify during testing
generate_dci0(mdci->dci_pdu,
mpdcch->e+(72*mdci->firstCCE),
mdci->dci_length,
mdci->L,
mdci->rnti);
generate_dci0 (mdci->dci_pdu, mpdcch->e + (72 * mdci->firstCCE), mdci->dci_length, mdci->L, mdci->rnti);
coded_bits = 72 * mdci->L;
// scrambling
uint16_t absSF = (frame*10)+subframe;
uint16_t absSF = (frame * 10) + subframe;
AssertFatal(absSF < 1024,
"Absolute subframe %d = %d*10 + %d > 1023\n",
absSF,frame,subframe);
AssertFatal (absSF < 1024, "Absolute subframe %d = %d*10 + %d > 1023\n", absSF, frame, subframe);
mpdcch_scrambling(fp,
mdci,
absSF,
mpdcch->e+(72*mdci->firstCCE),
coded_bits);
mpdcch_scrambling (fp, mdci, absSF, mpdcch->e + (72 * mdci->firstCCE), coded_bits);
// Modulation for PDCCH
if (fp->nb_antenna_ports_eNB==1)
gain_lin_QPSK = (int16_t)((amp*ONE_OVER_SQRT2_Q15)>>15);
if (fp->nb_antenna_ports_eNB == 1)
gain_lin_QPSK = (int16_t) ((amp * ONE_OVER_SQRT2_Q15) >> 15);
else
gain_lin_QPSK = amp/2;
gain_lin_QPSK = amp / 2;
uint8_t *e_ptr = mpdcch->e;
uint8_t *e_ptr = mpdcch->e;
// if (mdci->transmission_type==0) nprime=mdci->rnti&3; // for Localized 2+4 we use 6.8B.5 rule
// map directly to one antenna port for now
......@@ -185,19 +175,22 @@ void generate_mdci_top(PHY_VARS_eNB *eNB, int frame, int subframe,int16_t amp,in
// mpdcchtab5 below contains the mapping from each coded symbol to relative RE avoiding the DMRS
int re_offset = fp->first_carrier_offset + 1 + ((fp->N_RB_DL==100)?1:0) + mdci->narrowband*12*6;
if (re_offset>fp->ofdm_symbol_size) re_offset-=(fp->ofdm_symbol_size-1);
int32_t *txF = &txdataF[0][re_offset];
int32_t yIQ;
int re_offset = fp->first_carrier_offset + 1 + ((fp->N_RB_DL == 100) ? 1 : 0) + mdci->narrowband * 12 * 6;
if (re_offset > fp->ofdm_symbol_size)
re_offset -= (fp->ofdm_symbol_size - 1);
int32_t *txF = &txdataF[0][re_offset];
int32_t yIQ;
for (i=0; i<(coded_bits>>1); i++) {
for (i = 0; i < (coded_bits >> 1); i++) {
// QPSK modulation to yIQ
((int16_t*)&yIQ)[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK; e_ptr++;
((int16_t*)&yIQ)[1] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK; e_ptr++;
txF[mpdcch5tab[i+(36*mdci->firstCCE)]] = yIQ;
((int16_t *) & yIQ)[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
e_ptr++;
((int16_t *) & yIQ)[1] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
e_ptr++;
txF[mpdcch5tab[i + (36 * mdci->firstCCE)]] = yIQ;
}
}
}
}
#endif
openair1/PHY/LTE_TRANSPORT/proto.h
View file @ 3a434370
......@@ -1677,6 +1677,10 @@ void init_ul_hopping(LTE_DL_FRAME_PARMS *frame_parms);
@param nB nB from 36.304 (0=4T,1=2T,2=T,3=T/2,4=T/4,5=T/8,6=T/16,7=T/32*/
int init_ue_paging_info(PHY_VARS_UE *ue, long defaultPagingCycle, long nB);
#ifdef Rel14
void init_mpdcch5tab_normal_regular_subframe_evenNRBDL(PHY_VARS_eNB *eNB,int l_MPDCCH_start);
#endif
int32_t compareints (const void * a, const void * b);
......
openair1/SCHED/fapi_l1.c
View file @ 3a434370
......@@ -59,7 +59,7 @@ void handle_nfapi_mpdcch_pdu(PHY_VARS_eNB *eNB,
LTE_eNB_MPDCCH *mpdcch_vars = &eNB->mpdcch_vars[idx];
nfapi_dl_config_mpdcch_pdu *pdu = &dl_config_pdu->mpdcch_pdu;
LOG_D(PHY,"Frame %d, Subframe %d: MDCI processing\n",proc->frame_tx,proc->subframe_tx);
LOG_I(PHY,"Frame %d, Subframe %d: MDCI processing\n",proc->frame_tx,proc->subframe_tx);
// copy dci configuration into eNB structure
fill_mdci_and_dlsch(eNB,proc,&mpdcch_vars->mdci_alloc[mpdcch_vars->num_dci],pdu);
......@@ -147,7 +147,7 @@ void handle_nfapi_dlsch_pdu(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,
dlsch0_harq = dlsch0->harq_processes[0];
dlsch0_harq->pdu = sdu;
if (proc->frame_tx < 200) LOG_I(PHY,"NFAPI: frame %d, subframe %d: Programming SI-BR (%d) => %d\n",proc->frame_tx,proc->subframe_tx,rel13->pdsch_payload_type,UE_id);
if (proc->frame_tx < 200) LOG_D(PHY,"NFAPI: frame %d, subframe %d: Programming SI-BR (%d) => %d\n",proc->frame_tx,proc->subframe_tx,rel13->pdsch_payload_type,UE_id);
dlsch0->rnti = 0xFFFF;
dlsch0->Kmimo = 1;
......@@ -156,6 +156,8 @@ void handle_nfapi_dlsch_pdu(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,
dlsch0->i0 = rel13->initial_transmission_sf_io;
dlsch0_harq->pdsch_start = rel10->pdsch_start;
dlsch0->harq_ids[proc->subframe_tx] = 0;
dlsch0_harq->frame = proc->frame_tx;
dlsch0_harq->subframe = proc->subframe_tx;
if (rel13->pdsch_payload_type == 0) dlsch0->sib1_br_flag=1;
......
openair1/SCHED/phy_procedures_lte_eNb.c
View file @ 3a434370
This source diff could not be displayed because it is too large. You can view the blob instead.
openair2/LAYER2/MAC/eNB_scheduler_RA.c
View file @ 3a434370
This source diff could not be displayed because it is too large. You can view the blob instead.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment