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zzha zzha
OpenXG-RAN
Commits
82df0e51
Commit
82df0e51
authored
Aug 10, 2020
by
Sakthivel Velumani
Browse files
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Plain Diff
updated tables and 64qam mod
parent
f8675c25
Changes
7
Expand all
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Showing
7 changed files
with
113 additions
and
44 deletions
+113
-44
cmake_targets/CMakeLists.txt
cmake_targets/CMakeLists.txt
+1
-0
openair1/PHY/INIT/nr_init.c
openair1/PHY/INIT/nr_init.c
+1
-0
openair1/PHY/MODULATION/nr_modulation.c
openair1/PHY/MODULATION/nr_modulation.c
+83
-24
openair1/PHY/NR_REFSIG/nr_mod_table.h
openair1/PHY/NR_REFSIG/nr_mod_table.h
+8
-3
openair1/PHY/NR_REFSIG/nr_refsig.h
openair1/PHY/NR_REFSIG/nr_refsig.h
+2
-0
openair1/PHY/NR_TRANSPORT/nr_dlsch.c
openair1/PHY/NR_TRANSPORT/nr_dlsch.c
+1
-1
openair1/SIMULATION/NR_PHY/dlsim.c
openair1/SIMULATION/NR_PHY/dlsim.c
+17
-16
No files found.
cmake_targets/CMakeLists.txt
View file @
82df0e51
...
@@ -1543,6 +1543,7 @@ set(PHY_SRC_UE
...
@@ -1543,6 +1543,7 @@ set(PHY_SRC_UE
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/nr_dmrs_rx.c
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/nr_dmrs_rx.c
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/nr_gold.c
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/nr_gold.c
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/scrambling_luts.c
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/scrambling_luts.c
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/nr_gen_mod_table.c
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/dmrs_nr.c
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/dmrs_nr.c
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/ptrs_nr.c
${
OPENAIR1_DIR
}
/PHY/NR_REFSIG/ptrs_nr.c
${
OPENAIR1_DIR
}
/PHY/NR_UE_ESTIMATION/filt16a_32.c
${
OPENAIR1_DIR
}
/PHY/NR_UE_ESTIMATION/filt16a_32.c
...
...
openair1/PHY/INIT/nr_init.c
View file @
82df0e51
...
@@ -132,6 +132,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
...
@@ -132,6 +132,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
}
}
}
}
nr_generate_modulation_table
();
nr_init_pdcch_dmrs
(
gNB
,
cfg
->
cell_config
.
phy_cell_id
.
value
);
nr_init_pdcch_dmrs
(
gNB
,
cfg
->
cell_config
.
phy_cell_id
.
value
);
nr_init_pbch_interleaver
(
gNB
->
nr_pbch_interleaver
);
nr_init_pbch_interleaver
(
gNB
->
nr_pbch_interleaver
);
//PDSCH DMRS init
//PDSCH DMRS init
...
...
openair1/PHY/MODULATION/nr_modulation.c
View file @
82df0e51
...
@@ -34,64 +34,123 @@ void nr_modulation(uint32_t *in,
...
@@ -34,64 +34,123 @@ void nr_modulation(uint32_t *in,
int32_t
*
nr_mod_table32
;
int32_t
*
nr_mod_table32
;
int32_t
*
out32
=
(
int32_t
*
)
out
;
int32_t
*
out32
=
(
int32_t
*
)
out
;
uint8_t
*
in_bytes
=
(
uint8_t
*
)
in
;
uint8_t
*
in_bytes
=
(
uint8_t
*
)
in
;
uint64_t
*
in64
=
(
uint64_t
*
)
in
;
int64_t
*
out64
=
(
int64_t
*
)
out
;
uint8_t
idx
;
uint8_t
idx
;
uint16_t
u
=
1
;
uint32_t
i
,
j
;
uint8_t
shift_lut
[
3
]
=
{
0
,
2
,
4
};
uint32_t
bit_cnt
;
uint64_t
x
,
x1
,
x2
;
#if defined(__SSE2__)
#if defined(__AVX2__)
uint16_t
*
in_2bytes
=
(
uint16_t
*
)
in
;
__m256i
*
nr_mod_table256
;
__m256i
*
out256
;
#elif defined(__SSE2__)
__m128i
*
nr_mod_table128
;
__m128i
*
nr_mod_table128
;
__m128i
*
out128
;
__m128i
*
out128
;
__m64
*
nr_mod_table64
;
__m64
*
out64
;
#endif
#endif
offset
=
(
mod_order
==
2
)
?
NR_MOD_TABLE_QPSK_OFFSET
:
(
mod_order
==
4
)
?
NR_MOD_TABLE_QAM16_OFFSET
:
\
offset
=
(
mod_order
==
2
)
?
NR_MOD_TABLE_QPSK_OFFSET
:
(
mod_order
==
4
)
?
NR_MOD_TABLE_QAM16_OFFSET
:
\
(
mod_order
==
6
)
?
NR_MOD_TABLE_QAM64_OFFSET
:
(
mod_order
==
8
)
?
NR_MOD_TABLE_QAM256_OFFSET
:
0
;
(
mod_order
==
6
)
?
NR_MOD_TABLE_QAM64_OFFSET
:
(
mod_order
==
8
)
?
NR_MOD_TABLE_QAM256_OFFSET
:
0
;
LOG_
D
(
PHY
,
"nr_modulation: length %d, mod_order %d
\n
"
,
length
,
mod_order
);
LOG_
I
(
PHY
,
"nr_modulation: length %d, mod_order %d
\n
"
,
length
,
mod_order
);
switch
(
mod_order
)
{
switch
(
mod_order
)
{
case
6
:
case
6
:
nr_mod_table32
=
(
int32_t
*
)
nr_mod_table
;
j
=
0
;
for
(
int
i
=
0
;
i
<
length
/
mod_order
;
i
++
)
for
(
i
=
0
;
i
<
length
/
192
;
i
++
)
{
{
x
=
in64
[
i
*
3
];
idx
=
((
in
[
i
*
mod_order
/
32
]
>>
((
i
*
mod_order
)
&
0x1f
))
&
mask
);
x1
=
x
&
4095
;
if
((((
i
+
1
)
*
mod_order
)
>
32
*
u
)
&&
(
i
!=
0
))
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
idx
|=
(
in
[(
i
*
mod_order
/
32
)
+
1
]
<<
shift_lut
[(
u
++
)
%
3
])
&
0x3f
;
x1
=
(
x
>>
12
)
&
4095
;
else
if
(((
i
+
1
)
*
mod_order
)
==
32
*
u
)
u
++
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x
>>
24
)
&
4095
;
out32
[
i
]
=
nr_mod_table32
[(
offset
+
idx
)];
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x
>>
36
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x
>>
48
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x2
=
(
x
>>
60
);
x
=
in64
[
i
*
3
+
1
];
x2
|=
x
<<
4
;
x1
=
x2
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x2
>>
12
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x2
>>
24
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x2
>>
36
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x2
>>
48
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x2
=
((
x
>>
56
)
&
0xf0
)
|
(
x2
>>
60
);
x
=
in64
[
i
*
3
+
2
];
x2
|=
x
<<
8
;
x1
=
x2
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x2
>>
12
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x2
>>
24
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x2
>>
36
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x2
>>
48
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x2
=
((
x
>>
52
)
&
0xff0
)
|
(
x2
>>
60
);
out64
[
j
++
]
=
nr_64qam_mod_table
[
x2
];
}
i
*=
24
;
bit_cnt
=
i
*
8
;
while
(
bit_cnt
<
length
)
{
x
=
*
((
uint32_t
*
)(
in_bytes
+
i
));
x1
=
x
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
x1
=
(
x
>>
12
)
&
4095
;
out64
[
j
++
]
=
nr_64qam_mod_table
[
x1
];
i
+=
3
;
bit_cnt
+=
24
;
}
}
return
;
return
;
case
8
:
case
8
:
nr_mod_table32
=
(
int32_t
*
)
nr_mod_table
;
nr_mod_table32
=
(
int32_t
*
)
nr_mod_table
;
for
(
i
nt
i
=
0
;
i
<
length
/
8
;
i
++
)
for
(
i
=
0
;
i
<
length
/
8
;
i
++
)
out32
[
i
]
=
nr_mod_table32
[(
offset
+
in_bytes
[
i
])];
out32
[
i
]
=
nr_mod_table32
[(
offset
+
in_bytes
[
i
])];
return
;
return
;
#if defined(__SSE2__)
#if defined(__AVX2__)
case
2
:
nr_mod_table256
=
(
__m256i
*
)
nr_qpsk_2byte_mod_table
;
out256
=
(
__m256i
*
)
out
;
for
(
i
=
0
;
i
<
length
/
16
;
i
++
)
out256
[
i
]
=
nr_mod_table256
[
in_2bytes
[
i
]];
if
(
length
%
16
)
out256
[
i
+
1
]
=
nr_mod_table256
[
in_2bytes
[
i
]];
return
;
#elif defined(__SSE2__)
case
2
:
case
2
:
nr_mod_table128
=
(
__m128i
*
)
nr_qpsk_byte_mod_table
;
nr_mod_table128
=
(
__m128i
*
)
nr_qpsk_byte_mod_table
;
out128
=
(
__m128i
*
)
out
;
out128
=
(
__m128i
*
)
out
;
for
(
i
nt
i
=
0
;
i
<
length
/
8
;
i
++
)
for
(
i
=
0
;
i
<
length
/
8
;
i
++
)
out128
[
i
]
=
nr_mod_table128
[
in_bytes
[
i
]];
out128
[
i
]
=
nr_mod_table128
[
in_bytes
[
i
]];
if
(
length
%
8
)
out128
[
i
+
1
]
=
nr_mod_table128
[
in_bytes
[
i
]];
return
;
return
;
#endif
case
4
:
case
4
:
nr_mod_table64
=
(
__m64
*
)
nr_qam16_byte_mod_table
;
out64
=
(
int64_t
*
)
out
;
out64
=
(
__m64
*
)
out
;
for
(
int
i
=
0
;
i
<
length
/
8
;
i
++
)
for
(
int
i
=
0
;
i
<
length
/
8
;
i
++
)
out64
[
i
]
=
nr_
mod_table64
[
in_bytes
[
i
]];
out64
[
i
]
=
nr_
16qam_byte_mod_table
[
in_bytes
[
i
]];
return
;
return
;
#endif
default:
default:
break
;
break
;
}
}
nr_mod_table32
=
(
int32_t
*
)
nr_mod_table
;
nr_mod_table32
=
(
int32_t
*
)
nr_
qpsk_
mod_table
;
for
(
int
i
=
0
;
i
<
length
/
mod_order
;
i
++
)
for
(
int
i
=
0
;
i
<
length
/
mod_order
;
i
++
)
{
{
idx
=
((
in
[
i
*
mod_order
/
32
]
>>
((
i
*
mod_order
)
&
0x1f
))
&
mask
);
idx
=
((
in
[
i
*
mod_order
/
32
]
>>
((
i
*
mod_order
)
&
0x1f
))
&
mask
);
...
...
openair1/PHY/NR_REFSIG/nr_mod_table.h
View file @
82df0e51
This diff is collapsed.
Click to expand it.
openair1/PHY/NR_REFSIG/nr_refsig.h
View file @
82df0e51
...
@@ -53,6 +53,8 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB,
...
@@ -53,6 +53,8 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB,
void
init_scrambling_luts
(
void
);
void
init_scrambling_luts
(
void
);
void
nr_generate_modulation_table
(
void
);
extern
__m64
byte2m64_re
[
256
];
extern
__m64
byte2m64_re
[
256
];
extern
__m64
byte2m64_im
[
256
];
extern
__m64
byte2m64_im
[
256
];
...
...
openair1/PHY/NR_TRANSPORT/nr_dlsch.c
View file @
82df0e51
...
@@ -150,7 +150,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
...
@@ -150,7 +150,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
nb_re
=
((
12
*
rel15
->
NrOfSymbols
)
-
nb_re_dmrs
-
xOverhead
)
*
rel15
->
rbSize
*
rel15
->
NrOfCodewords
;
nb_re
=
((
12
*
rel15
->
NrOfSymbols
)
-
nb_re_dmrs
-
xOverhead
)
*
rel15
->
rbSize
*
rel15
->
NrOfCodewords
;
uint8_t
Qm
=
rel15
->
qamModOrder
[
0
];
uint8_t
Qm
=
rel15
->
qamModOrder
[
0
];
uint32_t
encoded_length
=
nb_re
*
Qm
;
uint32_t
encoded_length
=
nb_re
*
Qm
;
int16_t
mod_dmrs
[
n_dmrs
<<
1
];
int16_t
mod_dmrs
[
n_dmrs
<<
1
]
__attribute__
((
aligned
(
256
)))
;
/// CRC, coding, interleaving and rate matching
/// CRC, coding, interleaving and rate matching
AssertFatal
(
harq
->
pdu
!=
NULL
,
"harq->pdu is null
\n
"
);
AssertFatal
(
harq
->
pdu
!=
NULL
,
"harq->pdu is null
\n
"
);
...
...
openair1/SIMULATION/NR_PHY/dlsim.c
View file @
82df0e51
...
@@ -926,22 +926,6 @@ int main(int argc, char **argv)
...
@@ -926,22 +926,6 @@ int main(int argc, char **argv)
printf
(
"SNR %f : n_errors (negative CRC) = %d/%d, Avg round %.2f, Channel BER %e, Eff Rate %.4f bits/slot, Eff Throughput %.2f, TBS %d bits/slot
\n
"
,
SNR
,
n_errors
,
n_trials
,
roundStats
[
snrRun
],(
double
)
errors_scrambling
/
available_bits
/
n_trials
,
effRate
,
effRate
/
TBS
*
100
,
TBS
);
printf
(
"SNR %f : n_errors (negative CRC) = %d/%d, Avg round %.2f, Channel BER %e, Eff Rate %.4f bits/slot, Eff Throughput %.2f, TBS %d bits/slot
\n
"
,
SNR
,
n_errors
,
n_trials
,
roundStats
[
snrRun
],(
double
)
errors_scrambling
/
available_bits
/
n_trials
,
effRate
,
effRate
/
TBS
*
100
,
TBS
);
printf
(
"
\n
"
);
printf
(
"
\n
"
);
if
(
n_trials
==
1
)
{
LOG_M
(
"rxsig0.m"
,
"rxs0"
,
UE
->
common_vars
.
rxdata
[
0
],
frame_length_complex_samples
,
1
,
1
);
if
(
UE
->
frame_parms
.
nb_antennas_rx
>
1
)
LOG_M
(
"rxsig1.m"
,
"rxs1"
,
UE
->
common_vars
.
rxdata
[
1
],
frame_length_complex_samples
,
1
,
1
);
LOG_M
(
"chestF0.m"
,
"chF0"
,
UE
->
pdsch_vars
[
0
][
0
]
->
dl_ch_estimates_ext
,
N_RB_DL
*
12
*
14
,
1
,
1
);
write_output
(
"rxF_comp.m"
,
"rxFc"
,
&
UE
->
pdsch_vars
[
0
][
0
]
->
rxdataF_comp0
[
0
][
0
],
N_RB_DL
*
12
*
14
,
1
,
1
);
break
;
}
//if ((float)n_errors/(float)n_trials <= target_error_rate) {
if
(
effRate
>=
(
eff_tp_check
*
TBS
))
{
printf
(
"PDSCH test OK
\n
"
);
break
;
}
if
(
print_perf
==
1
)
{
if
(
print_perf
==
1
)
{
printf
(
"
\n
gNB TX function statistics (per %d us slot, NPRB %d, mcs %d, TBS %d, Kr %d (Zc %d))
\n
"
,
printf
(
"
\n
gNB TX function statistics (per %d us slot, NPRB %d, mcs %d, TBS %d, Kr %d (Zc %d))
\n
"
,
1000
>>*
scc
->
ssbSubcarrierSpacing
,
dlsch_config
.
rbSize
,
dlsch_config
.
mcsIndex
[
0
],
1000
>>*
scc
->
ssbSubcarrierSpacing
,
dlsch_config
.
rbSize
,
dlsch_config
.
mcsIndex
[
0
],
...
@@ -992,6 +976,23 @@ int main(int argc, char **argv)
...
@@ -992,6 +976,23 @@ int main(int argc, char **argv)
printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC");
printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC");
*/
*/
}
}
if
(
n_trials
==
1
)
{
LOG_M
(
"rxsig0.m"
,
"rxs0"
,
UE
->
common_vars
.
rxdata
[
0
],
frame_length_complex_samples
,
1
,
1
);
if
(
UE
->
frame_parms
.
nb_antennas_rx
>
1
)
LOG_M
(
"rxsig1.m"
,
"rxs1"
,
UE
->
common_vars
.
rxdata
[
1
],
frame_length_complex_samples
,
1
,
1
);
LOG_M
(
"chestF0.m"
,
"chF0"
,
UE
->
pdsch_vars
[
0
][
0
]
->
dl_ch_estimates_ext
,
N_RB_DL
*
12
*
14
,
1
,
1
);
write_output
(
"rxF_comp.m"
,
"rxFc"
,
&
UE
->
pdsch_vars
[
0
][
0
]
->
rxdataF_comp0
[
0
][
0
],
N_RB_DL
*
12
*
14
,
1
,
1
);
break
;
}
//if ((float)n_errors/(float)n_trials <= target_error_rate) {
if
(
effRate
>=
(
eff_tp_check
*
TBS
))
{
printf
(
"PDSCH test OK
\n
"
);
break
;
}
snrRun
++
;
snrRun
++
;
}
// NSR
}
// NSR
...
...
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