Commit b9eb6c98 authored by Robert Schmidt's avatar Robert Schmidt

Use vrb_map in in DL for NSA mode

parent ce2dd17e
...@@ -444,8 +444,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -444,8 +444,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
//mbsfn_status[CC_id] = 0; //mbsfn_status[CC_id] = 0;
// clear vrb_maps // clear vrb_maps
memset(cc[CC_id].vrb_map, 0, 100); memset(cc[CC_id].vrb_map, 0, 275);
memset(cc[CC_id].vrb_map_UL, 0, 100); memset(cc[CC_id].vrb_map_UL, 0, 275);
clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame, slot); clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame, slot);
} }
......
...@@ -550,7 +550,6 @@ void nr_generate_Msg2(module_id_t module_idP, ...@@ -550,7 +550,6 @@ void nr_generate_Msg2(module_id_t module_idP,
uint16_t RA_rnti = ra->RA_rnti; uint16_t RA_rnti = ra->RA_rnti;
long locationAndBandwidth; long locationAndBandwidth;
// uint8_t *vrb_map = cc[CC_id].vrb_map, CC_id;
// check if UE is doing RA on CORESET0 , InitialBWP or configured BWP from SCD // check if UE is doing RA on CORESET0 , InitialBWP or configured BWP from SCD
// get the BW of the PDCCH for PDCCH size and RAR PDSCH size // get the BW of the PDCCH for PDCCH size and RAR PDSCH size
...@@ -740,6 +739,11 @@ void nr_generate_Msg2(module_id_t module_idP, ...@@ -740,6 +739,11 @@ void nr_generate_Msg2(module_id_t module_idP,
nr_mac->TX_req[CC_id].Number_of_PDUs++; nr_mac->TX_req[CC_id].Number_of_PDUs++;
nr_mac->TX_req[CC_id].Slot = slotP; nr_mac->TX_req[CC_id].Slot = slotP;
memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&cc[CC_id].RAR_pdu.payload[0], tx_req->TLVs[0].length); memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&cc[CC_id].RAR_pdu.payload[0], tx_req->TLVs[0].length);
/* mark the corresponding RBs as used */
uint8_t *vrb_map = cc[CC_id].vrb_map;
for (int rb = 0; rb < pdsch_pdu_rel15->rbSize; rb++)
vrb_map[rb + pdsch_pdu_rel15->rbStart] = 1;
} }
} }
......
...@@ -137,6 +137,11 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ ...@@ -137,6 +137,11 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){
dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag = 1; dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag = 1;
dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload = (*(uint32_t*)cc->MIB_pdu.payload) & ((1<<24)-1); dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload = (*(uint32_t*)cc->MIB_pdu.payload) & ((1<<24)-1);
dl_req->nPDUs++; dl_req->nPDUs++;
uint8_t *vrb_map = cc[CC_id].vrb_map;
const int rbStart = dl_config_pdu->ssb_pdu.ssb_pdu_rel15.ssbOffsetPointA;
for (int rb = 0; rb < 20; rb++)
vrb_map[rbStart + rb] = 1;
} }
} }
} }
......
...@@ -517,9 +517,19 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id, ...@@ -517,9 +517,19 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id,
sched_ctrl->time_domain_allocation = 2; sched_ctrl->time_domain_allocation = 2;
// Freq-demain allocation // Freq-demain allocation
uint8_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275); const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
sched_ctrl->rbSize = bwpSize; int rbStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
sched_ctrl->rbStart = 0; while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++;
int rbSize = 1;
while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize]) rbSize++;
DevAssert(rbSize >= 3); /* just ensure we have at least 3 RBs */
sched_ctrl->rbSize = rbSize;
sched_ctrl->rbStart = rbStart;
/* mark the corresponding RBs as used */
for (int rb = 0; rb < sched_ctrl->rbSize; rb++)
vrb_map[rb + sched_ctrl->rbStart] = 1;
// modulation scheme // modulation scheme
sched_ctrl->mcsTableIdx = 0; sched_ctrl->mcsTableIdx = 0;
......
...@@ -172,9 +172,9 @@ typedef struct { ...@@ -172,9 +172,9 @@ typedef struct {
/// Template for RA computations /// Template for RA computations
NR_RA_t ra[NR_NB_RA_PROC_MAX]; NR_RA_t ra[NR_NB_RA_PROC_MAX];
/// VRB map for common channels /// VRB map for common channels
uint8_t vrb_map[100]; uint8_t vrb_map[275];
/// VRB map for common channels and retransmissions by PHICH /// VRB map for common channels and retransmissions by PHICH
uint8_t vrb_map_UL[100]; uint8_t vrb_map_UL[275];
/// number of subframe allocation pattern available for MBSFN sync area /// number of subframe allocation pattern available for MBSFN sync area
uint8_t num_sf_allocation_pattern; uint8_t num_sf_allocation_pattern;
} NR_COMMON_channels_t; } NR_COMMON_channels_t;
......
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