Added support for MM channel configuration, Keyhole feature support  and addressed customer issues

MM Channel configuration
Keyhole feature support
resolve the page allocation issues

QDMA DPDK 2020.2.1 Driver Release to support DPDK v20.11 Framework Changes

2020.2 QDMA Linux Driver README File updated with proper simlink

2020.2 QDMA Linux Driver Release

2020.2 QDMA DPDK Driver Release

2020.2 QDMA Windows Driver Release

XDMA: dma_from/to_device: do NOT mark partial completion as failure. the bw is not calculated in the case of underflow (partial completion).

XDMA: 1. split module parameter sgdma_timeout to h2c_timeout & c2h_timeout. 2. value of 0 means no timeout (i.e., wait forever).

Fix warnings

2020.2 XVSEC Driver Release documentation updates pointing to https://xilinx.github.io/dma_ip_drivers/

2020.2 XVSEC Driver Release - Supports the MCAP functionality for US/US+ and Versal Devices

no need to use __init and __exit. Attributes are set by the the
module_init/module_exit macros

set name length to 16 and use snprintf

XDMA: fix build for Centos and RHEL

libxdma: fix next adjacent descriptors

Various fixes

XDMA: Mark engine as not running when stopping after timeouts

Change the checks for kernel versions to include checks for RHEL
versions in case they are present.
Add HAS_MMIOWB, ACCESS_OK_2_ARGS, HAS_WAKE_UP, and HAS_WAKE_UP_ONE
and use them

Updated the apps/include/qdma_nl.h

Updated the qdma_nl.h

Updated the license header for QDMA Linux Driver application include files

Fix the setting of the next adjacent fields in descriptors.

Following commit 5faf23ec the next_adj field of all descriptors is set
according to the index of the descriptor rather than its address which
causes issues when dma_alloc_coherent doesn't return an address which is
page aligned (which happens).
Moreover, in the case of a transfer which number of descriptors is
bigger than a full page, the next_adj field is set to the maximum (63)
for all descriptors untill the last page of descriptors where it starts
decreasing.
Last, even before this commit, the next_adj field inside a block of
adjacent descriptors is not decreasing untill coming near page end,
which is not compliant with what the documentation says :

"Every descriptor in the descriptor list must accurately describe the descriptor
or block ofdescriptors that follows. In a block of adjacent descriptors, the
Nxt_adj value decrements from the first descriptor to the second to last
descriptor which has a value of zero. Likewise, eachdescriptor in the block
points to the next descriptor in the block, except for the last descriptor
which might point to a new block or might terminate the list."

This commit aligns the blocks of adjacent descriptors to
XDMA_MAX_ADJ_BLOCK_SIZE and makes the next_adj field decrease inside
each block untill the second to last descriptor in the block or in the
full transfer. The size of the page being a multiple of the size of the
block (4096 = sizeof(xdma_desc) * 128 =
sizeof(xdma_desc) * 2 * XDMA_MAX_ADJ_BLOCK_SIZE

Resolved HW errors observed with QDMA4.0 MM only design

If pci_read_config_byte of register PCI_INTERRUPT_PIN returns 0, it
means that legacy interrupts are not supported so return an error
instead of trying to request an interrupt with val = 0.

pci_cleanup_aer_uncorrect_error_status replaced by
pci_aer_clear_nonfatal_status

To keep compatibility, 0 for MSI-x is replaced by 0 for Auto since Auto
will try MSI-x first.
Add 3 - MSI-x for MSI-x mode.

Currently err_engine and all following errors try to release the
resource they failed to create.

Unlike engine_start, which sets the engine's running field itself,
engine_stop instead requires its callers to clear the field. However,
not all of them do, and notably the timeout handlers do not, meaning
that after a request times out and we stop the engine we never start it
again, causing all future transfers on the channel to hit the software
timeout.

Instead, set running to 0 inside xdma_engine_stop to mirror engine_start
to both fix the bug and prevent future ones creeping in.